1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 20 #ifndef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x00201000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #define RESET_VECTOR_OFFSET 0x27FFC 31 #define BOOT_PAGE_OFFSET 0x27000 32 33 #ifdef CONFIG_SDCARD 34 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 35 #define CONFIG_SPL_MMC_MINIMAL 36 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 37 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 38 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 39 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 40 #ifndef CONFIG_SPL_BUILD 41 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 42 #endif 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 44 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 45 #define CONFIG_SPL_MMC_BOOT 46 #endif 47 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_SKIP_RELOCATE 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 52 #endif 53 54 #endif 55 #endif /* CONFIG_RAMBOOT_PBL */ 56 57 #define CONFIG_DDR_ECC 58 59 #define CONFIG_CMD_REGINFO 60 61 /* High Level Configuration Options */ 62 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 63 #define CONFIG_MP /* support multiple processors */ 64 65 #ifndef CONFIG_SYS_TEXT_BASE 66 #define CONFIG_SYS_TEXT_BASE 0xeff40000 67 #endif 68 69 #ifndef CONFIG_RESET_VECTOR_ADDRESS 70 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 71 #endif 72 73 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 74 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 75 #define CONFIG_PCIE1 /* PCIE controller 1 */ 76 #define CONFIG_PCIE2 /* PCIE controller 2 */ 77 #define CONFIG_PCIE3 /* PCIE controller 3 */ 78 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 79 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 80 81 #define CONFIG_ENV_OVERWRITE 82 83 /* 84 * These can be toggled for performance analysis, otherwise use default. 85 */ 86 #define CONFIG_SYS_CACHE_STASHING 87 #define CONFIG_BTB /* toggle branch predition */ 88 #ifdef CONFIG_DDR_ECC 89 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 90 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 91 #endif 92 93 #define CONFIG_ENABLE_36BIT_PHYS 94 95 #define CONFIG_ADDR_MAP 96 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 97 98 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 99 #define CONFIG_SYS_MEMTEST_END 0x00400000 100 #define CONFIG_SYS_ALT_MEMTEST 101 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 102 103 /* 104 * Config the L3 Cache as L3 SRAM 105 */ 106 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 107 #define CONFIG_SYS_L3_SIZE (512 << 10) 108 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 109 #ifdef CONFIG_RAMBOOT_PBL 110 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 111 #endif 112 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 113 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 114 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 115 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 116 117 #define CONFIG_SYS_DCSRBAR 0xf0000000 118 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 119 120 /* 121 * DDR Setup 122 */ 123 #define CONFIG_VERY_BIG_RAM 124 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 125 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 126 127 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 128 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 129 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 130 131 #define CONFIG_DDR_SPD 132 133 /* 134 * IFC Definitions 135 */ 136 #define CONFIG_SYS_FLASH_BASE 0xe0000000 137 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 138 139 #ifdef CONFIG_SPL_BUILD 140 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 141 #else 142 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 143 #endif 144 145 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 146 #define CONFIG_MISC_INIT_R 147 148 #define CONFIG_HWCONFIG 149 150 /* define to use L1 as initial stack */ 151 #define CONFIG_L1_INIT_RAM 152 #define CONFIG_SYS_INIT_RAM_LOCK 153 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 154 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 155 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 156 /* The assembler doesn't like typecast */ 157 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 158 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 159 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 160 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 161 162 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 163 GENERATED_GBL_DATA_SIZE) 164 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 165 166 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 167 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 168 169 /* Serial Port - controlled on board with jumper J8 170 * open - index 2 171 * shorted - index 1 172 */ 173 #define CONFIG_CONS_INDEX 1 174 #define CONFIG_SYS_NS16550_SERIAL 175 #define CONFIG_SYS_NS16550_REG_SIZE 1 176 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 177 178 #define CONFIG_SYS_BAUDRATE_TABLE \ 179 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 180 181 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 182 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 183 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 184 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 185 186 /* I2C */ 187 #define CONFIG_SYS_I2C 188 #define CONFIG_SYS_I2C_FSL 189 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 190 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 191 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 192 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 193 194 /* 195 * General PCI 196 * Memory space is mapped 1-1, but I/O space must start from 0. 197 */ 198 199 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 200 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 201 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 202 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 203 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 204 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 205 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 206 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 207 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 208 209 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 210 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 211 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 212 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 213 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 214 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 215 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 216 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 217 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 218 219 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 220 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 221 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 222 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 223 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 224 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 225 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 226 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 227 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 228 229 /* controller 4, Base address 203000 */ 230 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 231 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 232 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 233 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 234 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 235 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 236 237 #ifdef CONFIG_PCI 238 #define CONFIG_PCI_INDIRECT_BRIDGE 239 240 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 241 #endif /* CONFIG_PCI */ 242 243 /* SATA */ 244 #ifdef CONFIG_FSL_SATA_V2 245 #define CONFIG_LIBATA 246 #define CONFIG_FSL_SATA 247 248 #define CONFIG_SYS_SATA_MAX_DEVICE 2 249 #define CONFIG_SATA1 250 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 251 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 252 #define CONFIG_SATA2 253 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 254 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 255 256 #define CONFIG_LBA48 257 #endif 258 259 #ifdef CONFIG_FMAN_ENET 260 #define CONFIG_MII /* MII PHY management */ 261 #define CONFIG_ETHPRIME "FM1@DTSEC1" 262 #endif 263 264 /* 265 * Environment 266 */ 267 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 268 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 269 270 /* 271 * Command line configuration. 272 */ 273 274 #ifdef CONFIG_PCI 275 #define CONFIG_CMD_PCI 276 #endif 277 278 /* 279 * Miscellaneous configurable options 280 */ 281 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 282 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 283 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 284 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 285 #ifdef CONFIG_CMD_KGDB 286 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 287 #else 288 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 289 #endif 290 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 291 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 292 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 293 294 /* 295 * For booting Linux, the board info and command line data 296 * have to be in the first 64 MB of memory, since this is 297 * the maximum mapped by the Linux kernel during initialization. 298 */ 299 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 300 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 301 302 #ifdef CONFIG_CMD_KGDB 303 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 304 #endif 305 306 /* 307 * Environment Configuration 308 */ 309 #define CONFIG_ROOTPATH "/opt/nfsroot" 310 #define CONFIG_BOOTFILE "uImage" 311 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 312 313 /* default location for tftp and bootm */ 314 #define CONFIG_LOADADDR 1000000 315 316 #define CONFIG_HVBOOT \ 317 "setenv bootargs config-addr=0x60000000; " \ 318 "bootm 0x01000000 - 0x00f00000" 319 320 #ifndef CONFIG_MTD_NOR_FLASH 321 #else 322 #define CONFIG_FLASH_CFI_DRIVER 323 #define CONFIG_SYS_FLASH_CFI 324 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 325 #endif 326 327 #if defined(CONFIG_SPIFLASH) 328 #define CONFIG_SYS_EXTRA_ENV_RELOC 329 #define CONFIG_ENV_SPI_BUS 0 330 #define CONFIG_ENV_SPI_CS 0 331 #define CONFIG_ENV_SPI_MAX_HZ 10000000 332 #define CONFIG_ENV_SPI_MODE 0 333 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 334 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 335 #define CONFIG_ENV_SECT_SIZE 0x10000 336 #elif defined(CONFIG_SDCARD) 337 #define CONFIG_SYS_EXTRA_ENV_RELOC 338 #define CONFIG_SYS_MMC_ENV_DEV 0 339 #define CONFIG_ENV_SIZE 0x2000 340 #define CONFIG_ENV_OFFSET (512 * 0x800) 341 #elif defined(CONFIG_NAND) 342 #define CONFIG_SYS_EXTRA_ENV_RELOC 343 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 344 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 345 #elif defined(CONFIG_ENV_IS_NOWHERE) 346 #define CONFIG_ENV_SIZE 0x2000 347 #else 348 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 349 #define CONFIG_ENV_SIZE 0x2000 350 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 351 #endif 352 353 #define CONFIG_SYS_CLK_FREQ 66666666 354 #define CONFIG_DDR_CLK_FREQ 133333333 355 356 #ifndef __ASSEMBLY__ 357 unsigned long get_board_sys_clk(void); 358 unsigned long get_board_ddr_clk(void); 359 #endif 360 361 /* 362 * DDR Setup 363 */ 364 #define CONFIG_SYS_SPD_BUS_NUM 0 365 #define SPD_EEPROM_ADDRESS1 0x52 366 #define SPD_EEPROM_ADDRESS2 0x54 367 #define SPD_EEPROM_ADDRESS3 0x56 368 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 369 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 370 371 /* 372 * IFC Definitions 373 */ 374 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 375 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 376 + 0x8000000) | \ 377 CSPR_PORT_SIZE_16 | \ 378 CSPR_MSEL_NOR | \ 379 CSPR_V) 380 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 381 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 382 CSPR_PORT_SIZE_16 | \ 383 CSPR_MSEL_NOR | \ 384 CSPR_V) 385 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 386 /* NOR Flash Timing Params */ 387 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 388 389 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 390 FTIM0_NOR_TEADC(0x5) | \ 391 FTIM0_NOR_TEAHC(0x5)) 392 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 393 FTIM1_NOR_TRAD_NOR(0x1A) |\ 394 FTIM1_NOR_TSEQRAD_NOR(0x13)) 395 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 396 FTIM2_NOR_TCH(0x4) | \ 397 FTIM2_NOR_TWPH(0x0E) | \ 398 FTIM2_NOR_TWP(0x1c)) 399 #define CONFIG_SYS_NOR_FTIM3 0x0 400 401 #define CONFIG_SYS_FLASH_QUIET_TEST 402 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 403 404 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 405 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 406 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 407 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 408 409 #define CONFIG_SYS_FLASH_EMPTY_INFO 410 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 411 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 412 413 /* NAND Flash on IFC */ 414 #define CONFIG_NAND_FSL_IFC 415 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 416 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 417 #define CONFIG_SYS_NAND_BASE 0xff800000 418 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 419 420 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 421 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 422 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 423 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 424 | CSPR_V) 425 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 426 427 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 428 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 429 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 430 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 431 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 432 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 433 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 434 435 #define CONFIG_SYS_NAND_ONFI_DETECTION 436 437 /* ONFI NAND Flash mode0 Timing Params */ 438 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 439 FTIM0_NAND_TWP(0x18) | \ 440 FTIM0_NAND_TWCHT(0x07) | \ 441 FTIM0_NAND_TWH(0x0a)) 442 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 443 FTIM1_NAND_TWBE(0x39) | \ 444 FTIM1_NAND_TRR(0x0e) | \ 445 FTIM1_NAND_TRP(0x18)) 446 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 447 FTIM2_NAND_TREH(0x0a) | \ 448 FTIM2_NAND_TWHRE(0x1e)) 449 #define CONFIG_SYS_NAND_FTIM3 0x0 450 451 #define CONFIG_SYS_NAND_DDR_LAW 11 452 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 453 #define CONFIG_SYS_MAX_NAND_DEVICE 1 454 455 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 456 457 #if defined(CONFIG_NAND) 458 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 459 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 460 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 461 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 462 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 463 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 464 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 465 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 466 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 467 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 468 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 469 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 470 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 471 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 472 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 473 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 474 #else 475 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 476 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 477 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 478 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 479 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 480 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 481 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 482 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 483 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 484 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 485 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 486 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 487 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 488 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 489 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 490 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 491 #endif 492 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 493 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 494 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 495 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 496 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 497 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 498 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 499 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 500 501 /* CPLD on IFC */ 502 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 503 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 504 #define CONFIG_SYS_CSPR3_EXT (0xf) 505 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 506 | CSPR_PORT_SIZE_8 \ 507 | CSPR_MSEL_GPCM \ 508 | CSPR_V) 509 510 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 511 #define CONFIG_SYS_CSOR3 0x0 512 513 /* CPLD Timing parameters for IFC CS3 */ 514 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 515 FTIM0_GPCM_TEADC(0x0e) | \ 516 FTIM0_GPCM_TEAHC(0x0e)) 517 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 518 FTIM1_GPCM_TRAD(0x1f)) 519 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 520 FTIM2_GPCM_TCH(0x8) | \ 521 FTIM2_GPCM_TWP(0x1f)) 522 #define CONFIG_SYS_CS3_FTIM3 0x0 523 524 #if defined(CONFIG_RAMBOOT_PBL) 525 #define CONFIG_SYS_RAMBOOT 526 #endif 527 528 /* I2C */ 529 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 530 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 531 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 532 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 533 534 #define I2C_MUX_CH_DEFAULT 0x8 535 #define I2C_MUX_CH_VOL_MONITOR 0xa 536 #define I2C_MUX_CH_VSC3316_FS 0xc 537 #define I2C_MUX_CH_VSC3316_BS 0xd 538 539 /* Voltage monitor on channel 2*/ 540 #define I2C_VOL_MONITOR_ADDR 0x40 541 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 542 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 543 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 544 545 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 546 #ifndef CONFIG_SPL_BUILD 547 #define CONFIG_VID 548 #endif 549 #define CONFIG_VOL_MONITOR_IR36021_SET 550 #define CONFIG_VOL_MONITOR_IR36021_READ 551 /* The lowest and highest voltage allowed for T4240RDB */ 552 #define VDD_MV_MIN 819 553 #define VDD_MV_MAX 1212 554 555 /* 556 * eSPI - Enhanced SPI 557 */ 558 #define CONFIG_SF_DEFAULT_SPEED 10000000 559 #define CONFIG_SF_DEFAULT_MODE 0 560 561 /* Qman/Bman */ 562 #ifndef CONFIG_NOBQFMAN 563 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 564 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 565 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 566 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 567 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 568 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 569 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 570 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 571 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 572 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 573 CONFIG_SYS_BMAN_CENA_SIZE) 574 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 575 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 576 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 577 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 578 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 579 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 580 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 581 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 582 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 583 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 584 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 585 CONFIG_SYS_QMAN_CENA_SIZE) 586 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 587 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 588 589 #define CONFIG_SYS_DPAA_FMAN 590 #define CONFIG_SYS_DPAA_PME 591 #define CONFIG_SYS_PMAN 592 #define CONFIG_SYS_DPAA_DCE 593 #define CONFIG_SYS_DPAA_RMAN 594 #define CONFIG_SYS_INTERLAKEN 595 596 /* Default address of microcode for the Linux Fman driver */ 597 #if defined(CONFIG_SPIFLASH) 598 /* 599 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 600 * env, so we got 0x110000. 601 */ 602 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 603 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 604 #elif defined(CONFIG_SDCARD) 605 /* 606 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 607 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 608 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 609 */ 610 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 611 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 612 #elif defined(CONFIG_NAND) 613 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 614 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 615 #else 616 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 617 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 618 #endif 619 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 620 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 621 #endif /* CONFIG_NOBQFMAN */ 622 623 #ifdef CONFIG_SYS_DPAA_FMAN 624 #define CONFIG_FMAN_ENET 625 #define CONFIG_PHYLIB_10G 626 #define CONFIG_PHY_VITESSE 627 #define CONFIG_PHY_CORTINA 628 #define CONFIG_SYS_CORTINA_FW_IN_NOR 629 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 630 #define CONFIG_CORTINA_FW_LENGTH 0x40000 631 #define CONFIG_PHY_TERANETICS 632 #define SGMII_PHY_ADDR1 0x0 633 #define SGMII_PHY_ADDR2 0x1 634 #define SGMII_PHY_ADDR3 0x2 635 #define SGMII_PHY_ADDR4 0x3 636 #define SGMII_PHY_ADDR5 0x4 637 #define SGMII_PHY_ADDR6 0x5 638 #define SGMII_PHY_ADDR7 0x6 639 #define SGMII_PHY_ADDR8 0x7 640 #define FM1_10GEC1_PHY_ADDR 0x10 641 #define FM1_10GEC2_PHY_ADDR 0x11 642 #define FM2_10GEC1_PHY_ADDR 0x12 643 #define FM2_10GEC2_PHY_ADDR 0x13 644 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 645 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 646 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 647 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 648 #endif 649 650 /* SATA */ 651 #ifdef CONFIG_FSL_SATA_V2 652 #define CONFIG_LIBATA 653 #define CONFIG_FSL_SATA 654 655 #define CONFIG_SYS_SATA_MAX_DEVICE 2 656 #define CONFIG_SATA1 657 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 658 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 659 #define CONFIG_SATA2 660 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 661 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 662 663 #define CONFIG_LBA48 664 #endif 665 666 #ifdef CONFIG_FMAN_ENET 667 #define CONFIG_MII /* MII PHY management */ 668 #define CONFIG_ETHPRIME "FM1@DTSEC1" 669 #endif 670 671 /* 672 * USB 673 */ 674 #define CONFIG_USB_EHCI_FSL 675 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 676 #define CONFIG_HAS_FSL_DR_USB 677 678 #ifdef CONFIG_MMC 679 #define CONFIG_FSL_ESDHC 680 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 681 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 682 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 683 #endif 684 685 686 #define __USB_PHY_TYPE utmi 687 688 /* 689 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 690 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 691 * interleaving. It can be cacheline, page, bank, superbank. 692 * See doc/README.fsl-ddr for details. 693 */ 694 #ifdef CONFIG_ARCH_T4240 695 #define CTRL_INTLV_PREFERED 3way_4KB 696 #else 697 #define CTRL_INTLV_PREFERED cacheline 698 #endif 699 700 #define CONFIG_EXTRA_ENV_SETTINGS \ 701 "hwconfig=fsl_ddr:" \ 702 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 703 "bank_intlv=auto;" \ 704 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 705 "netdev=eth0\0" \ 706 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 707 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 708 "tftpflash=tftpboot $loadaddr $uboot && " \ 709 "protect off $ubootaddr +$filesize && " \ 710 "erase $ubootaddr +$filesize && " \ 711 "cp.b $loadaddr $ubootaddr $filesize && " \ 712 "protect on $ubootaddr +$filesize && " \ 713 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 714 "consoledev=ttyS0\0" \ 715 "ramdiskaddr=2000000\0" \ 716 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 717 "fdtaddr=1e00000\0" \ 718 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 719 "bdev=sda3\0" 720 721 #define CONFIG_HVBOOT \ 722 "setenv bootargs config-addr=0x60000000; " \ 723 "bootm 0x01000000 - 0x00f00000" 724 725 #define CONFIG_LINUX \ 726 "setenv bootargs root=/dev/ram rw " \ 727 "console=$consoledev,$baudrate $othbootargs;" \ 728 "setenv ramdiskaddr 0x02000000;" \ 729 "setenv fdtaddr 0x00c00000;" \ 730 "setenv loadaddr 0x1000000;" \ 731 "bootm $loadaddr $ramdiskaddr $fdtaddr" 732 733 #define CONFIG_HDBOOT \ 734 "setenv bootargs root=/dev/$bdev rw " \ 735 "console=$consoledev,$baudrate $othbootargs;" \ 736 "tftp $loadaddr $bootfile;" \ 737 "tftp $fdtaddr $fdtfile;" \ 738 "bootm $loadaddr - $fdtaddr" 739 740 #define CONFIG_NFSBOOTCOMMAND \ 741 "setenv bootargs root=/dev/nfs rw " \ 742 "nfsroot=$serverip:$rootpath " \ 743 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 744 "console=$consoledev,$baudrate $othbootargs;" \ 745 "tftp $loadaddr $bootfile;" \ 746 "tftp $fdtaddr $fdtfile;" \ 747 "bootm $loadaddr - $fdtaddr" 748 749 #define CONFIG_RAMBOOTCOMMAND \ 750 "setenv bootargs root=/dev/ram rw " \ 751 "console=$consoledev,$baudrate $othbootargs;" \ 752 "tftp $ramdiskaddr $ramdiskfile;" \ 753 "tftp $loadaddr $bootfile;" \ 754 "tftp $fdtaddr $fdtfile;" \ 755 "bootm $loadaddr $ramdiskaddr $fdtaddr" 756 757 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 758 759 #include <asm/fsl_secure_boot.h> 760 761 #endif /* __CONFIG_H */ 762