1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240RDB 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_PCIE4 19 20 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 21 22 #ifdef CONFIG_RAMBOOT_PBL 23 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 24 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg 25 #ifndef CONFIG_SDCARD 26 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 28 #else 29 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 30 #define CONFIG_SPL_ENV_SUPPORT 31 #define CONFIG_SPL_SERIAL_SUPPORT 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 #define CONFIG_SPL_LIBGENERIC_SUPPORT 35 #define CONFIG_SPL_LIBCOMMON_SUPPORT 36 #define CONFIG_SPL_I2C_SUPPORT 37 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_SYS_TEXT_BASE 0x00201000 40 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 41 #define CONFIG_SPL_PAD_TO 0x40000 42 #define CONFIG_SPL_MAX_SIZE 0x28000 43 #define RESET_VECTOR_OFFSET 0x27FFC 44 #define BOOT_PAGE_OFFSET 0x27000 45 46 #ifdef CONFIG_SDCARD 47 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 48 #define CONFIG_SPL_MMC_SUPPORT 49 #define CONFIG_SPL_MMC_MINIMAL 50 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 52 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 54 #ifndef CONFIG_SPL_BUILD 55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 56 #endif 57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 58 #define CONFIG_SPL_MMC_BOOT 59 #endif 60 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_SKIP_RELOCATE 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 65 #define CONFIG_SYS_NO_FLASH 66 #endif 67 68 #endif 69 #endif /* CONFIG_RAMBOOT_PBL */ 70 71 #define CONFIG_DDR_ECC 72 73 #define CONFIG_CMD_REGINFO 74 75 /* High Level Configuration Options */ 76 #define CONFIG_BOOKE 77 #define CONFIG_E500 /* BOOKE e500 family */ 78 #define CONFIG_E500MC /* BOOKE e500mc family */ 79 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 80 #define CONFIG_MP /* support multiple processors */ 81 82 #ifndef CONFIG_SYS_TEXT_BASE 83 #define CONFIG_SYS_TEXT_BASE 0xeff40000 84 #endif 85 86 #ifndef CONFIG_RESET_VECTOR_ADDRESS 87 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 88 #endif 89 90 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 91 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 92 #define CONFIG_FSL_IFC /* Enable IFC Support */ 93 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 94 #define CONFIG_PCI /* Enable PCI/PCIE */ 95 #define CONFIG_PCIE1 /* PCIE controller 1 */ 96 #define CONFIG_PCIE2 /* PCIE controller 2 */ 97 #define CONFIG_PCIE3 /* PCIE controller 3 */ 98 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 99 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 100 101 #define CONFIG_FSL_LAW /* Use common FSL init code */ 102 103 #define CONFIG_ENV_OVERWRITE 104 105 /* 106 * These can be toggled for performance analysis, otherwise use default. 107 */ 108 #define CONFIG_SYS_CACHE_STASHING 109 #define CONFIG_BTB /* toggle branch predition */ 110 #ifdef CONFIG_DDR_ECC 111 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 112 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 113 #endif 114 115 #define CONFIG_ENABLE_36BIT_PHYS 116 117 #define CONFIG_ADDR_MAP 118 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 119 120 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 121 #define CONFIG_SYS_MEMTEST_END 0x00400000 122 #define CONFIG_SYS_ALT_MEMTEST 123 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 124 125 /* 126 * Config the L3 Cache as L3 SRAM 127 */ 128 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 129 #define CONFIG_SYS_L3_SIZE (512 << 10) 130 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 131 #ifdef CONFIG_RAMBOOT_PBL 132 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 133 #endif 134 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 135 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 136 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 137 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 138 139 #define CONFIG_SYS_DCSRBAR 0xf0000000 140 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 141 142 /* 143 * DDR Setup 144 */ 145 #define CONFIG_VERY_BIG_RAM 146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 148 149 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 151 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 152 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 153 154 #define CONFIG_DDR_SPD 155 #define CONFIG_SYS_FSL_DDR3 156 157 /* 158 * IFC Definitions 159 */ 160 #define CONFIG_SYS_FLASH_BASE 0xe0000000 161 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 162 163 #ifdef CONFIG_SPL_BUILD 164 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 165 #else 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 167 #endif 168 169 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 170 #define CONFIG_MISC_INIT_R 171 172 #define CONFIG_HWCONFIG 173 174 /* define to use L1 as initial stack */ 175 #define CONFIG_L1_INIT_RAM 176 #define CONFIG_SYS_INIT_RAM_LOCK 177 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 178 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 179 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 180 /* The assembler doesn't like typecast */ 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 182 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 183 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 184 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 185 186 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 187 GENERATED_GBL_DATA_SIZE) 188 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 189 190 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 191 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 192 193 /* Serial Port - controlled on board with jumper J8 194 * open - index 2 195 * shorted - index 1 196 */ 197 #define CONFIG_CONS_INDEX 1 198 #define CONFIG_SYS_NS16550_SERIAL 199 #define CONFIG_SYS_NS16550_REG_SIZE 1 200 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 201 202 #define CONFIG_SYS_BAUDRATE_TABLE \ 203 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 204 205 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 206 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 207 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 208 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 209 210 /* I2C */ 211 #define CONFIG_SYS_I2C 212 #define CONFIG_SYS_I2C_FSL 213 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 214 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 215 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 216 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 217 218 /* 219 * General PCI 220 * Memory space is mapped 1-1, but I/O space must start from 0. 221 */ 222 223 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 224 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 225 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 226 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 227 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 228 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 229 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 230 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 231 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 232 233 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 234 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 235 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 236 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 237 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 238 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 239 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 240 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 241 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 242 243 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 244 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 245 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 246 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 247 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 248 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 249 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 250 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 251 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 252 253 /* controller 4, Base address 203000 */ 254 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 255 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 256 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 257 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 258 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 259 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 260 261 #ifdef CONFIG_PCI 262 #define CONFIG_PCI_INDIRECT_BRIDGE 263 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 264 265 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 266 #define CONFIG_DOS_PARTITION 267 #endif /* CONFIG_PCI */ 268 269 /* SATA */ 270 #ifdef CONFIG_FSL_SATA_V2 271 #define CONFIG_LIBATA 272 #define CONFIG_FSL_SATA 273 274 #define CONFIG_SYS_SATA_MAX_DEVICE 2 275 #define CONFIG_SATA1 276 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 277 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 278 #define CONFIG_SATA2 279 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 280 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 281 282 #define CONFIG_LBA48 283 #define CONFIG_CMD_SATA 284 #define CONFIG_DOS_PARTITION 285 #endif 286 287 #ifdef CONFIG_FMAN_ENET 288 #define CONFIG_MII /* MII PHY management */ 289 #define CONFIG_ETHPRIME "FM1@DTSEC1" 290 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 291 #endif 292 293 /* 294 * Environment 295 */ 296 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 297 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 298 299 /* 300 * Command line configuration. 301 */ 302 #define CONFIG_CMD_ERRATA 303 #define CONFIG_CMD_IRQ 304 305 #ifdef CONFIG_PCI 306 #define CONFIG_CMD_PCI 307 #endif 308 309 /* 310 * Miscellaneous configurable options 311 */ 312 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 313 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 314 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 315 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 316 #ifdef CONFIG_CMD_KGDB 317 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 318 #else 319 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 320 #endif 321 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 322 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 323 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 324 325 /* 326 * For booting Linux, the board info and command line data 327 * have to be in the first 64 MB of memory, since this is 328 * the maximum mapped by the Linux kernel during initialization. 329 */ 330 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 331 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 332 333 #ifdef CONFIG_CMD_KGDB 334 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 335 #endif 336 337 /* 338 * Environment Configuration 339 */ 340 #define CONFIG_ROOTPATH "/opt/nfsroot" 341 #define CONFIG_BOOTFILE "uImage" 342 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 343 344 /* default location for tftp and bootm */ 345 #define CONFIG_LOADADDR 1000000 346 347 #define CONFIG_BAUDRATE 115200 348 349 #define CONFIG_HVBOOT \ 350 "setenv bootargs config-addr=0x60000000; " \ 351 "bootm 0x01000000 - 0x00f00000" 352 353 #ifdef CONFIG_SYS_NO_FLASH 354 #ifndef CONFIG_RAMBOOT_PBL 355 #define CONFIG_ENV_IS_NOWHERE 356 #endif 357 #else 358 #define CONFIG_FLASH_CFI_DRIVER 359 #define CONFIG_SYS_FLASH_CFI 360 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 361 #endif 362 363 #if defined(CONFIG_SPIFLASH) 364 #define CONFIG_SYS_EXTRA_ENV_RELOC 365 #define CONFIG_ENV_IS_IN_SPI_FLASH 366 #define CONFIG_ENV_SPI_BUS 0 367 #define CONFIG_ENV_SPI_CS 0 368 #define CONFIG_ENV_SPI_MAX_HZ 10000000 369 #define CONFIG_ENV_SPI_MODE 0 370 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 371 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 372 #define CONFIG_ENV_SECT_SIZE 0x10000 373 #elif defined(CONFIG_SDCARD) 374 #define CONFIG_SYS_EXTRA_ENV_RELOC 375 #define CONFIG_ENV_IS_IN_MMC 376 #define CONFIG_SYS_MMC_ENV_DEV 0 377 #define CONFIG_ENV_SIZE 0x2000 378 #define CONFIG_ENV_OFFSET (512 * 0x800) 379 #elif defined(CONFIG_NAND) 380 #define CONFIG_SYS_EXTRA_ENV_RELOC 381 #define CONFIG_ENV_IS_IN_NAND 382 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 383 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 384 #elif defined(CONFIG_ENV_IS_NOWHERE) 385 #define CONFIG_ENV_SIZE 0x2000 386 #else 387 #define CONFIG_ENV_IS_IN_FLASH 388 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 389 #define CONFIG_ENV_SIZE 0x2000 390 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 391 #endif 392 393 #define CONFIG_SYS_CLK_FREQ 66666666 394 #define CONFIG_DDR_CLK_FREQ 133333333 395 396 #ifndef __ASSEMBLY__ 397 unsigned long get_board_sys_clk(void); 398 unsigned long get_board_ddr_clk(void); 399 #endif 400 401 /* 402 * DDR Setup 403 */ 404 #define CONFIG_SYS_SPD_BUS_NUM 0 405 #define SPD_EEPROM_ADDRESS1 0x52 406 #define SPD_EEPROM_ADDRESS2 0x54 407 #define SPD_EEPROM_ADDRESS3 0x56 408 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 409 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 410 411 /* 412 * IFC Definitions 413 */ 414 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 415 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 416 + 0x8000000) | \ 417 CSPR_PORT_SIZE_16 | \ 418 CSPR_MSEL_NOR | \ 419 CSPR_V) 420 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 421 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 422 CSPR_PORT_SIZE_16 | \ 423 CSPR_MSEL_NOR | \ 424 CSPR_V) 425 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 426 /* NOR Flash Timing Params */ 427 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 428 429 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 430 FTIM0_NOR_TEADC(0x5) | \ 431 FTIM0_NOR_TEAHC(0x5)) 432 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 433 FTIM1_NOR_TRAD_NOR(0x1A) |\ 434 FTIM1_NOR_TSEQRAD_NOR(0x13)) 435 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 436 FTIM2_NOR_TCH(0x4) | \ 437 FTIM2_NOR_TWPH(0x0E) | \ 438 FTIM2_NOR_TWP(0x1c)) 439 #define CONFIG_SYS_NOR_FTIM3 0x0 440 441 #define CONFIG_SYS_FLASH_QUIET_TEST 442 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 443 444 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 445 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 446 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 447 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 448 449 #define CONFIG_SYS_FLASH_EMPTY_INFO 450 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 451 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 452 453 /* NAND Flash on IFC */ 454 #define CONFIG_NAND_FSL_IFC 455 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 456 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 457 #define CONFIG_SYS_NAND_BASE 0xff800000 458 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 459 460 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 461 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 462 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 463 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 464 | CSPR_V) 465 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 466 467 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 468 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 469 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 470 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 471 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 472 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 473 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 474 475 #define CONFIG_SYS_NAND_ONFI_DETECTION 476 477 /* ONFI NAND Flash mode0 Timing Params */ 478 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 479 FTIM0_NAND_TWP(0x18) | \ 480 FTIM0_NAND_TWCHT(0x07) | \ 481 FTIM0_NAND_TWH(0x0a)) 482 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 483 FTIM1_NAND_TWBE(0x39) | \ 484 FTIM1_NAND_TRR(0x0e) | \ 485 FTIM1_NAND_TRP(0x18)) 486 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 487 FTIM2_NAND_TREH(0x0a) | \ 488 FTIM2_NAND_TWHRE(0x1e)) 489 #define CONFIG_SYS_NAND_FTIM3 0x0 490 491 #define CONFIG_SYS_NAND_DDR_LAW 11 492 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 493 #define CONFIG_SYS_MAX_NAND_DEVICE 1 494 #define CONFIG_CMD_NAND 495 496 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 497 498 #if defined(CONFIG_NAND) 499 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 500 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 501 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 502 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 503 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 504 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 505 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 506 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 507 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 508 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 509 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 510 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 511 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 512 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 513 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 514 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 515 #else 516 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 517 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 518 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 519 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 520 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 521 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 522 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 523 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 524 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 525 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 526 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 527 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 528 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 529 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 530 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 531 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 532 #endif 533 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 534 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 535 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 536 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 537 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 538 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 539 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 540 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 541 542 /* CPLD on IFC */ 543 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 544 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 545 #define CONFIG_SYS_CSPR3_EXT (0xf) 546 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 547 | CSPR_PORT_SIZE_8 \ 548 | CSPR_MSEL_GPCM \ 549 | CSPR_V) 550 551 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 552 #define CONFIG_SYS_CSOR3 0x0 553 554 /* CPLD Timing parameters for IFC CS3 */ 555 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 556 FTIM0_GPCM_TEADC(0x0e) | \ 557 FTIM0_GPCM_TEAHC(0x0e)) 558 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 559 FTIM1_GPCM_TRAD(0x1f)) 560 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 561 FTIM2_GPCM_TCH(0x8) | \ 562 FTIM2_GPCM_TWP(0x1f)) 563 #define CONFIG_SYS_CS3_FTIM3 0x0 564 565 #if defined(CONFIG_RAMBOOT_PBL) 566 #define CONFIG_SYS_RAMBOOT 567 #endif 568 569 /* I2C */ 570 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 571 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 572 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 573 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 574 575 #define I2C_MUX_CH_DEFAULT 0x8 576 #define I2C_MUX_CH_VOL_MONITOR 0xa 577 #define I2C_MUX_CH_VSC3316_FS 0xc 578 #define I2C_MUX_CH_VSC3316_BS 0xd 579 580 /* Voltage monitor on channel 2*/ 581 #define I2C_VOL_MONITOR_ADDR 0x40 582 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 583 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 584 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 585 586 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 587 #ifndef CONFIG_SPL_BUILD 588 #define CONFIG_VID 589 #endif 590 #define CONFIG_VOL_MONITOR_IR36021_SET 591 #define CONFIG_VOL_MONITOR_IR36021_READ 592 /* The lowest and highest voltage allowed for T4240RDB */ 593 #define VDD_MV_MIN 819 594 #define VDD_MV_MAX 1212 595 596 /* 597 * eSPI - Enhanced SPI 598 */ 599 #define CONFIG_SF_DEFAULT_SPEED 10000000 600 #define CONFIG_SF_DEFAULT_MODE 0 601 602 /* Qman/Bman */ 603 #ifndef CONFIG_NOBQFMAN 604 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 605 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 606 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 607 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 608 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 609 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 610 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 611 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 612 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 613 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 614 CONFIG_SYS_BMAN_CENA_SIZE) 615 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 616 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 617 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 618 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 619 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 620 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 621 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 622 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 623 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 624 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 625 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 626 CONFIG_SYS_QMAN_CENA_SIZE) 627 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 628 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 629 630 #define CONFIG_SYS_DPAA_FMAN 631 #define CONFIG_SYS_DPAA_PME 632 #define CONFIG_SYS_PMAN 633 #define CONFIG_SYS_DPAA_DCE 634 #define CONFIG_SYS_DPAA_RMAN 635 #define CONFIG_SYS_INTERLAKEN 636 637 /* Default address of microcode for the Linux Fman driver */ 638 #if defined(CONFIG_SPIFLASH) 639 /* 640 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 641 * env, so we got 0x110000. 642 */ 643 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 644 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 645 #elif defined(CONFIG_SDCARD) 646 /* 647 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 648 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 649 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 650 */ 651 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 652 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 653 #elif defined(CONFIG_NAND) 654 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 655 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 656 #else 657 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 658 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 659 #endif 660 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 661 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 662 #endif /* CONFIG_NOBQFMAN */ 663 664 #ifdef CONFIG_SYS_DPAA_FMAN 665 #define CONFIG_FMAN_ENET 666 #define CONFIG_PHYLIB_10G 667 #define CONFIG_PHY_VITESSE 668 #define CONFIG_PHY_CORTINA 669 #define CONFIG_SYS_CORTINA_FW_IN_NOR 670 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 671 #define CONFIG_CORTINA_FW_LENGTH 0x40000 672 #define CONFIG_PHY_TERANETICS 673 #define SGMII_PHY_ADDR1 0x0 674 #define SGMII_PHY_ADDR2 0x1 675 #define SGMII_PHY_ADDR3 0x2 676 #define SGMII_PHY_ADDR4 0x3 677 #define SGMII_PHY_ADDR5 0x4 678 #define SGMII_PHY_ADDR6 0x5 679 #define SGMII_PHY_ADDR7 0x6 680 #define SGMII_PHY_ADDR8 0x7 681 #define FM1_10GEC1_PHY_ADDR 0x10 682 #define FM1_10GEC2_PHY_ADDR 0x11 683 #define FM2_10GEC1_PHY_ADDR 0x12 684 #define FM2_10GEC2_PHY_ADDR 0x13 685 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 686 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 687 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 688 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 689 #endif 690 691 /* SATA */ 692 #ifdef CONFIG_FSL_SATA_V2 693 #define CONFIG_LIBATA 694 #define CONFIG_FSL_SATA 695 696 #define CONFIG_SYS_SATA_MAX_DEVICE 2 697 #define CONFIG_SATA1 698 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 699 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 700 #define CONFIG_SATA2 701 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 702 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 703 704 #define CONFIG_LBA48 705 #define CONFIG_CMD_SATA 706 #define CONFIG_DOS_PARTITION 707 #endif 708 709 #ifdef CONFIG_FMAN_ENET 710 #define CONFIG_MII /* MII PHY management */ 711 #define CONFIG_ETHPRIME "FM1@DTSEC1" 712 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 713 #endif 714 715 /* 716 * USB 717 */ 718 #define CONFIG_USB_STORAGE 719 #define CONFIG_USB_EHCI 720 #define CONFIG_USB_EHCI_FSL 721 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 722 #define CONFIG_HAS_FSL_DR_USB 723 724 #define CONFIG_MMC 725 726 #ifdef CONFIG_MMC 727 #define CONFIG_FSL_ESDHC 728 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 729 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 730 #define CONFIG_GENERIC_MMC 731 #define CONFIG_DOS_PARTITION 732 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 733 #endif 734 735 /* Hash command with SHA acceleration supported in hardware */ 736 #ifdef CONFIG_FSL_CAAM 737 #define CONFIG_CMD_HASH 738 #define CONFIG_SHA_HW_ACCEL 739 #endif 740 741 742 #define __USB_PHY_TYPE utmi 743 744 /* 745 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 746 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 747 * interleaving. It can be cacheline, page, bank, superbank. 748 * See doc/README.fsl-ddr for details. 749 */ 750 #ifdef CONFIG_PPC_T4240 751 #define CTRL_INTLV_PREFERED 3way_4KB 752 #else 753 #define CTRL_INTLV_PREFERED cacheline 754 #endif 755 756 #define CONFIG_EXTRA_ENV_SETTINGS \ 757 "hwconfig=fsl_ddr:" \ 758 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 759 "bank_intlv=auto;" \ 760 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 761 "netdev=eth0\0" \ 762 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 763 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 764 "tftpflash=tftpboot $loadaddr $uboot && " \ 765 "protect off $ubootaddr +$filesize && " \ 766 "erase $ubootaddr +$filesize && " \ 767 "cp.b $loadaddr $ubootaddr $filesize && " \ 768 "protect on $ubootaddr +$filesize && " \ 769 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 770 "consoledev=ttyS0\0" \ 771 "ramdiskaddr=2000000\0" \ 772 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 773 "fdtaddr=c00000\0" \ 774 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 775 "bdev=sda3\0" 776 777 #define CONFIG_HVBOOT \ 778 "setenv bootargs config-addr=0x60000000; " \ 779 "bootm 0x01000000 - 0x00f00000" 780 781 #define CONFIG_LINUX \ 782 "setenv bootargs root=/dev/ram rw " \ 783 "console=$consoledev,$baudrate $othbootargs;" \ 784 "setenv ramdiskaddr 0x02000000;" \ 785 "setenv fdtaddr 0x00c00000;" \ 786 "setenv loadaddr 0x1000000;" \ 787 "bootm $loadaddr $ramdiskaddr $fdtaddr" 788 789 #define CONFIG_HDBOOT \ 790 "setenv bootargs root=/dev/$bdev rw " \ 791 "console=$consoledev,$baudrate $othbootargs;" \ 792 "tftp $loadaddr $bootfile;" \ 793 "tftp $fdtaddr $fdtfile;" \ 794 "bootm $loadaddr - $fdtaddr" 795 796 #define CONFIG_NFSBOOTCOMMAND \ 797 "setenv bootargs root=/dev/nfs rw " \ 798 "nfsroot=$serverip:$rootpath " \ 799 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 800 "console=$consoledev,$baudrate $othbootargs;" \ 801 "tftp $loadaddr $bootfile;" \ 802 "tftp $fdtaddr $fdtfile;" \ 803 "bootm $loadaddr - $fdtaddr" 804 805 #define CONFIG_RAMBOOTCOMMAND \ 806 "setenv bootargs root=/dev/ram rw " \ 807 "console=$consoledev,$baudrate $othbootargs;" \ 808 "tftp $ramdiskaddr $ramdiskfile;" \ 809 "tftp $loadaddr $bootfile;" \ 810 "tftp $fdtaddr $fdtfile;" \ 811 "bootm $loadaddr $ramdiskaddr $fdtaddr" 812 813 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 814 815 #include <asm/fsl_secure_boot.h> 816 817 #endif /* __CONFIG_H */ 818