1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 20 #ifndef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 27 #define CONFIG_SPL_PAD_TO 0x40000 28 #define CONFIG_SPL_MAX_SIZE 0x28000 29 #define RESET_VECTOR_OFFSET 0x27FFC 30 #define BOOT_PAGE_OFFSET 0x27000 31 32 #ifdef CONFIG_SDCARD 33 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 34 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 35 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 36 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 37 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 38 #ifndef CONFIG_SPL_BUILD 39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 40 #endif 41 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 42 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 43 #define CONFIG_SPL_MMC_BOOT 44 #endif 45 46 #ifdef CONFIG_SPL_BUILD 47 #define CONFIG_SPL_SKIP_RELOCATE 48 #define CONFIG_SPL_COMMON_INIT_DDR 49 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 50 #endif 51 52 #endif 53 #endif /* CONFIG_RAMBOOT_PBL */ 54 55 #define CONFIG_DDR_ECC 56 57 /* High Level Configuration Options */ 58 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 59 #define CONFIG_MP /* support multiple processors */ 60 61 #ifndef CONFIG_RESET_VECTOR_ADDRESS 62 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 63 #endif 64 65 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 66 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 67 #define CONFIG_PCIE1 /* PCIE controller 1 */ 68 #define CONFIG_PCIE2 /* PCIE controller 2 */ 69 #define CONFIG_PCIE3 /* PCIE controller 3 */ 70 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 71 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 72 73 #define CONFIG_ENV_OVERWRITE 74 75 /* 76 * These can be toggled for performance analysis, otherwise use default. 77 */ 78 #define CONFIG_SYS_CACHE_STASHING 79 #define CONFIG_BTB /* toggle branch predition */ 80 #ifdef CONFIG_DDR_ECC 81 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 82 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 83 #endif 84 85 #define CONFIG_ENABLE_36BIT_PHYS 86 87 #define CONFIG_ADDR_MAP 88 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 89 90 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 91 #define CONFIG_SYS_MEMTEST_END 0x00400000 92 93 /* 94 * Config the L3 Cache as L3 SRAM 95 */ 96 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 97 #define CONFIG_SYS_L3_SIZE (512 << 10) 98 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 99 #ifdef CONFIG_RAMBOOT_PBL 100 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 101 #endif 102 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 103 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 104 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 105 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 106 107 #define CONFIG_SYS_DCSRBAR 0xf0000000 108 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 109 110 /* 111 * DDR Setup 112 */ 113 #define CONFIG_VERY_BIG_RAM 114 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 115 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 116 117 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 118 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 119 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 120 121 #define CONFIG_DDR_SPD 122 123 /* 124 * IFC Definitions 125 */ 126 #define CONFIG_SYS_FLASH_BASE 0xe0000000 127 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 128 129 #ifdef CONFIG_SPL_BUILD 130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 131 #else 132 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 133 #endif 134 135 #define CONFIG_MISC_INIT_R 136 137 #define CONFIG_HWCONFIG 138 139 /* define to use L1 as initial stack */ 140 #define CONFIG_L1_INIT_RAM 141 #define CONFIG_SYS_INIT_RAM_LOCK 142 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 143 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 144 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 145 /* The assembler doesn't like typecast */ 146 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 147 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 148 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 149 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 150 151 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 152 GENERATED_GBL_DATA_SIZE) 153 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 154 155 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 156 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 157 158 /* Serial Port - controlled on board with jumper J8 159 * open - index 2 160 * shorted - index 1 161 */ 162 #define CONFIG_SYS_NS16550_SERIAL 163 #define CONFIG_SYS_NS16550_REG_SIZE 1 164 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 165 166 #define CONFIG_SYS_BAUDRATE_TABLE \ 167 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 168 169 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 170 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 171 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 172 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 173 174 /* I2C */ 175 #define CONFIG_SYS_I2C 176 #define CONFIG_SYS_I2C_FSL 177 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 178 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 179 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 180 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 181 182 /* 183 * General PCI 184 * Memory space is mapped 1-1, but I/O space must start from 0. 185 */ 186 187 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 188 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 189 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 190 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 191 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 192 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 193 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 194 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 195 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 196 197 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 198 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 199 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 200 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 201 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 202 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 203 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 204 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 205 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 206 207 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 208 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 209 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 210 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 211 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 212 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 213 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 214 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 215 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 216 217 /* controller 4, Base address 203000 */ 218 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 219 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 220 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 221 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 222 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 223 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 224 225 #ifdef CONFIG_PCI 226 #define CONFIG_PCI_INDIRECT_BRIDGE 227 228 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 229 #endif /* CONFIG_PCI */ 230 231 /* SATA */ 232 #ifdef CONFIG_FSL_SATA_V2 233 #define CONFIG_SYS_SATA_MAX_DEVICE 2 234 #define CONFIG_SATA1 235 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 236 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 237 #define CONFIG_SATA2 238 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 239 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 240 241 #define CONFIG_LBA48 242 #endif 243 244 #ifdef CONFIG_FMAN_ENET 245 #define CONFIG_MII /* MII PHY management */ 246 #define CONFIG_ETHPRIME "FM1@DTSEC1" 247 #endif 248 249 /* 250 * Environment 251 */ 252 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 253 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 254 255 /* 256 * Command line configuration. 257 */ 258 259 /* 260 * Miscellaneous configurable options 261 */ 262 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 263 264 /* 265 * For booting Linux, the board info and command line data 266 * have to be in the first 64 MB of memory, since this is 267 * the maximum mapped by the Linux kernel during initialization. 268 */ 269 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 270 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 271 272 #ifdef CONFIG_CMD_KGDB 273 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 274 #endif 275 276 /* 277 * Environment Configuration 278 */ 279 #define CONFIG_ROOTPATH "/opt/nfsroot" 280 #define CONFIG_BOOTFILE "uImage" 281 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 282 283 /* default location for tftp and bootm */ 284 #define CONFIG_LOADADDR 1000000 285 286 #define CONFIG_HVBOOT \ 287 "setenv bootargs config-addr=0x60000000; " \ 288 "bootm 0x01000000 - 0x00f00000" 289 290 #ifndef CONFIG_MTD_NOR_FLASH 291 #else 292 #define CONFIG_FLASH_CFI_DRIVER 293 #define CONFIG_SYS_FLASH_CFI 294 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 295 #endif 296 297 #if defined(CONFIG_SPIFLASH) 298 #define CONFIG_SYS_EXTRA_ENV_RELOC 299 #define CONFIG_ENV_SPI_BUS 0 300 #define CONFIG_ENV_SPI_CS 0 301 #define CONFIG_ENV_SPI_MAX_HZ 10000000 302 #define CONFIG_ENV_SPI_MODE 0 303 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 304 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 305 #define CONFIG_ENV_SECT_SIZE 0x10000 306 #elif defined(CONFIG_SDCARD) 307 #define CONFIG_SYS_EXTRA_ENV_RELOC 308 #define CONFIG_SYS_MMC_ENV_DEV 0 309 #define CONFIG_ENV_SIZE 0x2000 310 #define CONFIG_ENV_OFFSET (512 * 0x800) 311 #elif defined(CONFIG_NAND) 312 #define CONFIG_SYS_EXTRA_ENV_RELOC 313 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 314 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 315 #elif defined(CONFIG_ENV_IS_NOWHERE) 316 #define CONFIG_ENV_SIZE 0x2000 317 #else 318 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 319 #define CONFIG_ENV_SIZE 0x2000 320 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 321 #endif 322 323 #define CONFIG_SYS_CLK_FREQ 66666666 324 #define CONFIG_DDR_CLK_FREQ 133333333 325 326 #ifndef __ASSEMBLY__ 327 unsigned long get_board_sys_clk(void); 328 unsigned long get_board_ddr_clk(void); 329 #endif 330 331 /* 332 * DDR Setup 333 */ 334 #define CONFIG_SYS_SPD_BUS_NUM 0 335 #define SPD_EEPROM_ADDRESS1 0x52 336 #define SPD_EEPROM_ADDRESS2 0x54 337 #define SPD_EEPROM_ADDRESS3 0x56 338 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 339 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 340 341 /* 342 * IFC Definitions 343 */ 344 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 345 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 346 + 0x8000000) | \ 347 CSPR_PORT_SIZE_16 | \ 348 CSPR_MSEL_NOR | \ 349 CSPR_V) 350 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 351 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 352 CSPR_PORT_SIZE_16 | \ 353 CSPR_MSEL_NOR | \ 354 CSPR_V) 355 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 356 /* NOR Flash Timing Params */ 357 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 358 359 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 360 FTIM0_NOR_TEADC(0x5) | \ 361 FTIM0_NOR_TEAHC(0x5)) 362 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 363 FTIM1_NOR_TRAD_NOR(0x1A) |\ 364 FTIM1_NOR_TSEQRAD_NOR(0x13)) 365 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 366 FTIM2_NOR_TCH(0x4) | \ 367 FTIM2_NOR_TWPH(0x0E) | \ 368 FTIM2_NOR_TWP(0x1c)) 369 #define CONFIG_SYS_NOR_FTIM3 0x0 370 371 #define CONFIG_SYS_FLASH_QUIET_TEST 372 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 373 374 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 375 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 376 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 377 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 378 379 #define CONFIG_SYS_FLASH_EMPTY_INFO 380 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 381 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 382 383 /* NAND Flash on IFC */ 384 #define CONFIG_NAND_FSL_IFC 385 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 386 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 387 #define CONFIG_SYS_NAND_BASE 0xff800000 388 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 389 390 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 391 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 392 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 393 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 394 | CSPR_V) 395 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 396 397 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 398 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 399 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 400 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 401 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 402 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 403 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 404 405 #define CONFIG_SYS_NAND_ONFI_DETECTION 406 407 /* ONFI NAND Flash mode0 Timing Params */ 408 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 409 FTIM0_NAND_TWP(0x18) | \ 410 FTIM0_NAND_TWCHT(0x07) | \ 411 FTIM0_NAND_TWH(0x0a)) 412 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 413 FTIM1_NAND_TWBE(0x39) | \ 414 FTIM1_NAND_TRR(0x0e) | \ 415 FTIM1_NAND_TRP(0x18)) 416 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 417 FTIM2_NAND_TREH(0x0a) | \ 418 FTIM2_NAND_TWHRE(0x1e)) 419 #define CONFIG_SYS_NAND_FTIM3 0x0 420 421 #define CONFIG_SYS_NAND_DDR_LAW 11 422 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 423 #define CONFIG_SYS_MAX_NAND_DEVICE 1 424 425 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 426 427 #if defined(CONFIG_NAND) 428 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 429 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 430 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 431 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 432 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 433 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 434 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 435 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 436 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 437 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 438 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 439 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 440 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 441 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 442 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 443 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 444 #else 445 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 446 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 447 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 448 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 449 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 450 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 451 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 452 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 453 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 454 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 455 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 456 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 457 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 458 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 459 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 460 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 461 #endif 462 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 463 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 464 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 465 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 466 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 467 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 468 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 469 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 470 471 /* CPLD on IFC */ 472 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 473 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 474 #define CONFIG_SYS_CSPR3_EXT (0xf) 475 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 476 | CSPR_PORT_SIZE_8 \ 477 | CSPR_MSEL_GPCM \ 478 | CSPR_V) 479 480 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 481 #define CONFIG_SYS_CSOR3 0x0 482 483 /* CPLD Timing parameters for IFC CS3 */ 484 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 485 FTIM0_GPCM_TEADC(0x0e) | \ 486 FTIM0_GPCM_TEAHC(0x0e)) 487 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 488 FTIM1_GPCM_TRAD(0x1f)) 489 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 490 FTIM2_GPCM_TCH(0x8) | \ 491 FTIM2_GPCM_TWP(0x1f)) 492 #define CONFIG_SYS_CS3_FTIM3 0x0 493 494 #if defined(CONFIG_RAMBOOT_PBL) 495 #define CONFIG_SYS_RAMBOOT 496 #endif 497 498 /* I2C */ 499 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 500 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 501 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 502 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 503 504 #define I2C_MUX_CH_DEFAULT 0x8 505 #define I2C_MUX_CH_VOL_MONITOR 0xa 506 #define I2C_MUX_CH_VSC3316_FS 0xc 507 #define I2C_MUX_CH_VSC3316_BS 0xd 508 509 /* Voltage monitor on channel 2*/ 510 #define I2C_VOL_MONITOR_ADDR 0x40 511 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 512 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 513 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 514 515 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 516 #ifndef CONFIG_SPL_BUILD 517 #define CONFIG_VID 518 #endif 519 #define CONFIG_VOL_MONITOR_IR36021_SET 520 #define CONFIG_VOL_MONITOR_IR36021_READ 521 /* The lowest and highest voltage allowed for T4240RDB */ 522 #define VDD_MV_MIN 819 523 #define VDD_MV_MAX 1212 524 525 /* 526 * eSPI - Enhanced SPI 527 */ 528 #define CONFIG_SF_DEFAULT_SPEED 10000000 529 #define CONFIG_SF_DEFAULT_MODE 0 530 531 /* Qman/Bman */ 532 #ifndef CONFIG_NOBQFMAN 533 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 534 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 535 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 536 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 537 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 538 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 539 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 540 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 541 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 542 CONFIG_SYS_BMAN_CENA_SIZE) 543 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 544 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 545 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 546 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 547 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 548 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 549 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 550 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 551 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 552 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 553 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 554 CONFIG_SYS_QMAN_CENA_SIZE) 555 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 556 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 557 558 #define CONFIG_SYS_DPAA_FMAN 559 #define CONFIG_SYS_DPAA_PME 560 #define CONFIG_SYS_PMAN 561 #define CONFIG_SYS_DPAA_DCE 562 #define CONFIG_SYS_DPAA_RMAN 563 #define CONFIG_SYS_INTERLAKEN 564 565 /* Default address of microcode for the Linux Fman driver */ 566 #if defined(CONFIG_SPIFLASH) 567 /* 568 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 569 * env, so we got 0x110000. 570 */ 571 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 572 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 573 #elif defined(CONFIG_SDCARD) 574 /* 575 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 576 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 577 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 578 */ 579 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 580 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 581 #elif defined(CONFIG_NAND) 582 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 583 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 584 #else 585 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 586 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 587 #endif 588 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 589 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 590 #endif /* CONFIG_NOBQFMAN */ 591 592 #ifdef CONFIG_SYS_DPAA_FMAN 593 #define CONFIG_FMAN_ENET 594 #define CONFIG_PHYLIB_10G 595 #define CONFIG_PHY_VITESSE 596 #define CONFIG_PHY_CORTINA 597 #define CONFIG_SYS_CORTINA_FW_IN_NOR 598 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 599 #define CONFIG_CORTINA_FW_LENGTH 0x40000 600 #define CONFIG_PHY_TERANETICS 601 #define SGMII_PHY_ADDR1 0x0 602 #define SGMII_PHY_ADDR2 0x1 603 #define SGMII_PHY_ADDR3 0x2 604 #define SGMII_PHY_ADDR4 0x3 605 #define SGMII_PHY_ADDR5 0x4 606 #define SGMII_PHY_ADDR6 0x5 607 #define SGMII_PHY_ADDR7 0x6 608 #define SGMII_PHY_ADDR8 0x7 609 #define FM1_10GEC1_PHY_ADDR 0x10 610 #define FM1_10GEC2_PHY_ADDR 0x11 611 #define FM2_10GEC1_PHY_ADDR 0x12 612 #define FM2_10GEC2_PHY_ADDR 0x13 613 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 614 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 615 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 616 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 617 #endif 618 619 /* SATA */ 620 #ifdef CONFIG_FSL_SATA_V2 621 #define CONFIG_SYS_SATA_MAX_DEVICE 2 622 #define CONFIG_SATA1 623 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 624 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 625 #define CONFIG_SATA2 626 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 627 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 628 629 #define CONFIG_LBA48 630 #endif 631 632 #ifdef CONFIG_FMAN_ENET 633 #define CONFIG_MII /* MII PHY management */ 634 #define CONFIG_ETHPRIME "FM1@DTSEC1" 635 #endif 636 637 /* 638 * USB 639 */ 640 #define CONFIG_USB_EHCI_FSL 641 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 642 #define CONFIG_HAS_FSL_DR_USB 643 644 #ifdef CONFIG_MMC 645 #define CONFIG_FSL_ESDHC 646 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 647 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 648 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 649 #endif 650 651 652 #define __USB_PHY_TYPE utmi 653 654 /* 655 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 656 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 657 * interleaving. It can be cacheline, page, bank, superbank. 658 * See doc/README.fsl-ddr for details. 659 */ 660 #ifdef CONFIG_ARCH_T4240 661 #define CTRL_INTLV_PREFERED 3way_4KB 662 #else 663 #define CTRL_INTLV_PREFERED cacheline 664 #endif 665 666 #define CONFIG_EXTRA_ENV_SETTINGS \ 667 "hwconfig=fsl_ddr:" \ 668 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 669 "bank_intlv=auto;" \ 670 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 671 "netdev=eth0\0" \ 672 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 673 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 674 "tftpflash=tftpboot $loadaddr $uboot && " \ 675 "protect off $ubootaddr +$filesize && " \ 676 "erase $ubootaddr +$filesize && " \ 677 "cp.b $loadaddr $ubootaddr $filesize && " \ 678 "protect on $ubootaddr +$filesize && " \ 679 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 680 "consoledev=ttyS0\0" \ 681 "ramdiskaddr=2000000\0" \ 682 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 683 "fdtaddr=1e00000\0" \ 684 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 685 "bdev=sda3\0" 686 687 #define CONFIG_HVBOOT \ 688 "setenv bootargs config-addr=0x60000000; " \ 689 "bootm 0x01000000 - 0x00f00000" 690 691 #define CONFIG_LINUX \ 692 "setenv bootargs root=/dev/ram rw " \ 693 "console=$consoledev,$baudrate $othbootargs;" \ 694 "setenv ramdiskaddr 0x02000000;" \ 695 "setenv fdtaddr 0x00c00000;" \ 696 "setenv loadaddr 0x1000000;" \ 697 "bootm $loadaddr $ramdiskaddr $fdtaddr" 698 699 #define CONFIG_HDBOOT \ 700 "setenv bootargs root=/dev/$bdev rw " \ 701 "console=$consoledev,$baudrate $othbootargs;" \ 702 "tftp $loadaddr $bootfile;" \ 703 "tftp $fdtaddr $fdtfile;" \ 704 "bootm $loadaddr - $fdtaddr" 705 706 #define CONFIG_NFSBOOTCOMMAND \ 707 "setenv bootargs root=/dev/nfs rw " \ 708 "nfsroot=$serverip:$rootpath " \ 709 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 710 "console=$consoledev,$baudrate $othbootargs;" \ 711 "tftp $loadaddr $bootfile;" \ 712 "tftp $fdtaddr $fdtfile;" \ 713 "bootm $loadaddr - $fdtaddr" 714 715 #define CONFIG_RAMBOOTCOMMAND \ 716 "setenv bootargs root=/dev/ram rw " \ 717 "console=$consoledev,$baudrate $othbootargs;" \ 718 "tftp $ramdiskaddr $ramdiskfile;" \ 719 "tftp $loadaddr $bootfile;" \ 720 "tftp $fdtaddr $fdtfile;" \ 721 "bootm $loadaddr $ramdiskaddr $fdtaddr" 722 723 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 724 725 #include <asm/fsl_secure_boot.h> 726 727 #endif /* __CONFIG_H */ 728