1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 20 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x00201000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #define RESET_VECTOR_OFFSET 0x27FFC 31 #define BOOT_PAGE_OFFSET 0x27000 32 33 #ifdef CONFIG_NAND 34 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 35 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 36 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 37 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 38 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 39 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg 40 #define CONFIG_SPL_NAND_BOOT 41 #endif 42 43 #ifdef CONFIG_SDCARD 44 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 45 #define CONFIG_SPL_MMC_MINIMAL 46 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 47 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 48 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 49 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 50 #ifndef CONFIG_SPL_BUILD 51 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 52 #endif 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg 55 #define CONFIG_SPL_MMC_BOOT 56 #endif 57 58 #ifdef CONFIG_SPL_BUILD 59 #define CONFIG_SPL_SKIP_RELOCATE 60 #define CONFIG_SPL_COMMON_INIT_DDR 61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 62 #endif 63 64 #endif 65 #endif /* CONFIG_RAMBOOT_PBL */ 66 67 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 68 /* Set 1M boot space */ 69 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 70 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 71 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 72 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 73 #endif 74 75 #define CONFIG_SRIO_PCIE_BOOT_MASTER 76 #define CONFIG_DDR_ECC 77 78 #include "t4qds.h" 79 80 #ifndef CONFIG_MTD_NOR_FLASH 81 #else 82 #define CONFIG_FLASH_CFI_DRIVER 83 #define CONFIG_SYS_FLASH_CFI 84 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 85 #endif 86 87 #if defined(CONFIG_SPIFLASH) 88 #define CONFIG_SYS_EXTRA_ENV_RELOC 89 #define CONFIG_ENV_SPI_BUS 0 90 #define CONFIG_ENV_SPI_CS 0 91 #define CONFIG_ENV_SPI_MAX_HZ 10000000 92 #define CONFIG_ENV_SPI_MODE 0 93 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 94 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 95 #define CONFIG_ENV_SECT_SIZE 0x10000 96 #elif defined(CONFIG_SDCARD) 97 #define CONFIG_SYS_EXTRA_ENV_RELOC 98 #define CONFIG_SYS_MMC_ENV_DEV 0 99 #define CONFIG_ENV_SIZE 0x2000 100 #define CONFIG_ENV_OFFSET (512 * 0x800) 101 #elif defined(CONFIG_NAND) 102 #define CONFIG_SYS_EXTRA_ENV_RELOC 103 #define CONFIG_ENV_SIZE 0x2000 104 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 105 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 106 #define CONFIG_ENV_ADDR 0xffe20000 107 #define CONFIG_ENV_SIZE 0x2000 108 #elif defined(CONFIG_ENV_IS_NOWHERE) 109 #define CONFIG_ENV_SIZE 0x2000 110 #else 111 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 112 #define CONFIG_ENV_SIZE 0x2000 113 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 114 #endif 115 116 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 117 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 118 119 #ifndef __ASSEMBLY__ 120 unsigned long get_board_sys_clk(void); 121 unsigned long get_board_ddr_clk(void); 122 #endif 123 124 /* EEPROM */ 125 #define CONFIG_ID_EEPROM 126 #define CONFIG_SYS_I2C_EEPROM_NXID 127 #define CONFIG_SYS_EEPROM_BUS_NUM 0 128 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 129 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 130 131 /* 132 * DDR Setup 133 */ 134 #define CONFIG_SYS_SPD_BUS_NUM 0 135 #define SPD_EEPROM_ADDRESS1 0x51 136 #define SPD_EEPROM_ADDRESS2 0x52 137 #define SPD_EEPROM_ADDRESS3 0x53 138 #define SPD_EEPROM_ADDRESS4 0x54 139 #define SPD_EEPROM_ADDRESS5 0x55 140 #define SPD_EEPROM_ADDRESS6 0x56 141 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 142 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 143 144 /* 145 * IFC Definitions 146 */ 147 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 148 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 149 + 0x8000000) | \ 150 CSPR_PORT_SIZE_16 | \ 151 CSPR_MSEL_NOR | \ 152 CSPR_V) 153 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 154 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 155 CSPR_PORT_SIZE_16 | \ 156 CSPR_MSEL_NOR | \ 157 CSPR_V) 158 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 159 /* NOR Flash Timing Params */ 160 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 161 162 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 163 FTIM0_NOR_TEADC(0x5) | \ 164 FTIM0_NOR_TEAHC(0x5)) 165 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 166 FTIM1_NOR_TRAD_NOR(0x1A) |\ 167 FTIM1_NOR_TSEQRAD_NOR(0x13)) 168 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 169 FTIM2_NOR_TCH(0x4) | \ 170 FTIM2_NOR_TWPH(0x0E) | \ 171 FTIM2_NOR_TWP(0x1c)) 172 #define CONFIG_SYS_NOR_FTIM3 0x0 173 174 #define CONFIG_SYS_FLASH_QUIET_TEST 175 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 176 177 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 178 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 179 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 180 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 181 182 #define CONFIG_SYS_FLASH_EMPTY_INFO 183 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 184 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 185 186 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 187 #define QIXIS_BASE 0xffdf0000 188 #define QIXIS_LBMAP_SWITCH 6 189 #define QIXIS_LBMAP_MASK 0x0f 190 #define QIXIS_LBMAP_SHIFT 0 191 #define QIXIS_LBMAP_DFLTBANK 0x00 192 #define QIXIS_LBMAP_ALTBANK 0x04 193 #define QIXIS_RST_CTL_RESET 0x83 194 #define QIXIS_RST_FORCE_MEM 0x1 195 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 196 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 197 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 198 #define QIXIS_BRDCFG5 0x55 199 #define QIXIS_MUX_SDHC 2 200 #define QIXIS_MUX_SDHC_WIDTH8 1 201 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 202 203 #define CONFIG_SYS_CSPR3_EXT (0xf) 204 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 205 | CSPR_PORT_SIZE_8 \ 206 | CSPR_MSEL_GPCM \ 207 | CSPR_V) 208 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 209 #define CONFIG_SYS_CSOR3 0x0 210 /* QIXIS Timing parameters for IFC CS3 */ 211 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 212 FTIM0_GPCM_TEADC(0x0e) | \ 213 FTIM0_GPCM_TEAHC(0x0e)) 214 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 215 FTIM1_GPCM_TRAD(0x3f)) 216 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 217 FTIM2_GPCM_TCH(0x8) | \ 218 FTIM2_GPCM_TWP(0x1f)) 219 #define CONFIG_SYS_CS3_FTIM3 0x0 220 221 /* NAND Flash on IFC */ 222 #define CONFIG_NAND_FSL_IFC 223 #define CONFIG_SYS_NAND_BASE 0xff800000 224 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 225 226 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 227 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 228 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 229 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 230 | CSPR_V) 231 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 232 233 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 234 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 235 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 236 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 237 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 238 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 239 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 240 241 #define CONFIG_SYS_NAND_ONFI_DETECTION 242 243 /* ONFI NAND Flash mode0 Timing Params */ 244 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 245 FTIM0_NAND_TWP(0x18) | \ 246 FTIM0_NAND_TWCHT(0x07) | \ 247 FTIM0_NAND_TWH(0x0a)) 248 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 249 FTIM1_NAND_TWBE(0x39) | \ 250 FTIM1_NAND_TRR(0x0e) | \ 251 FTIM1_NAND_TRP(0x18)) 252 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 253 FTIM2_NAND_TREH(0x0a) | \ 254 FTIM2_NAND_TWHRE(0x1e)) 255 #define CONFIG_SYS_NAND_FTIM3 0x0 256 257 #define CONFIG_SYS_NAND_DDR_LAW 11 258 259 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 260 #define CONFIG_SYS_MAX_NAND_DEVICE 1 261 262 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 263 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 264 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 265 266 #if defined(CONFIG_NAND) 267 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 268 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 269 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 270 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 271 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 272 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 273 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 274 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 275 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 276 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 277 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 278 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 279 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 280 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 281 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 282 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 283 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 284 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 285 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 286 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 287 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 288 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 289 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 290 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 291 #else 292 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 293 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 294 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 295 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 296 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 297 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 298 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 299 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 300 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 301 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 302 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 303 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 304 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 305 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 306 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 307 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 308 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 309 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 310 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 311 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 312 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 313 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 314 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 315 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 316 #endif 317 318 #if defined(CONFIG_RAMBOOT_PBL) 319 #define CONFIG_SYS_RAMBOOT 320 #endif 321 322 /* I2C */ 323 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 324 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 325 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 326 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 327 328 #define I2C_MUX_CH_DEFAULT 0x8 329 #define I2C_MUX_CH_VOL_MONITOR 0xa 330 #define I2C_MUX_CH_VSC3316_FS 0xc 331 #define I2C_MUX_CH_VSC3316_BS 0xd 332 333 /* Voltage monitor on channel 2*/ 334 #define I2C_VOL_MONITOR_ADDR 0x40 335 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 336 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 337 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 338 339 /* VSC Crossbar switches */ 340 #define CONFIG_VSC_CROSSBAR 341 #define VSC3316_FSM_TX_ADDR 0x70 342 #define VSC3316_FSM_RX_ADDR 0x71 343 344 /* 345 * RapidIO 346 */ 347 348 /* 349 * for slave u-boot IMAGE instored in master memory space, 350 * PHYS must be aligned based on the SIZE 351 */ 352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 353 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 354 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 355 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 356 /* 357 * for slave UCODE and ENV instored in master memory space, 358 * PHYS must be aligned based on the SIZE 359 */ 360 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 361 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 362 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 363 364 /* slave core release by master*/ 365 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 366 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 367 368 /* 369 * SRIO_PCIE_BOOT - SLAVE 370 */ 371 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 372 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 373 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 374 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 375 #endif 376 /* 377 * eSPI - Enhanced SPI 378 */ 379 #define CONFIG_SF_DEFAULT_SPEED 10000000 380 #define CONFIG_SF_DEFAULT_MODE 0 381 382 /* Qman/Bman */ 383 #ifndef CONFIG_NOBQFMAN 384 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 385 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 386 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 387 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 388 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 389 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 390 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 391 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 392 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 393 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 394 CONFIG_SYS_BMAN_CENA_SIZE) 395 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 396 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 397 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 398 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 399 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 400 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 401 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 402 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 403 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 404 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 405 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 406 CONFIG_SYS_QMAN_CENA_SIZE) 407 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 408 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 409 410 #define CONFIG_SYS_DPAA_FMAN 411 #define CONFIG_SYS_DPAA_PME 412 #define CONFIG_SYS_PMAN 413 #define CONFIG_SYS_DPAA_DCE 414 #define CONFIG_SYS_DPAA_RMAN 415 #define CONFIG_SYS_INTERLAKEN 416 417 /* Default address of microcode for the Linux Fman driver */ 418 #if defined(CONFIG_SPIFLASH) 419 /* 420 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 421 * env, so we got 0x110000. 422 */ 423 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 424 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 425 #elif defined(CONFIG_SDCARD) 426 /* 427 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 428 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 429 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 430 */ 431 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 432 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 433 #elif defined(CONFIG_NAND) 434 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 435 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 436 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 437 /* 438 * Slave has no ucode locally, it can fetch this from remote. When implementing 439 * in two corenet boards, slave's ucode could be stored in master's memory 440 * space, the address can be mapped from slave TLB->slave LAW-> 441 * slave SRIO or PCIE outbound window->master inbound window-> 442 * master LAW->the ucode address in master's memory space. 443 */ 444 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 445 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 446 #else 447 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 448 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 449 #endif 450 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 451 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 452 #endif /* CONFIG_NOBQFMAN */ 453 454 #ifdef CONFIG_SYS_DPAA_FMAN 455 #define CONFIG_FMAN_ENET 456 #define CONFIG_PHYLIB_10G 457 #define CONFIG_PHY_VITESSE 458 #define CONFIG_PHY_TERANETICS 459 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 460 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 461 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 462 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 463 #define FM1_10GEC1_PHY_ADDR 0x0 464 #define FM1_10GEC2_PHY_ADDR 0x1 465 #define FM2_10GEC1_PHY_ADDR 0x2 466 #define FM2_10GEC2_PHY_ADDR 0x3 467 #endif 468 469 /* SATA */ 470 #ifdef CONFIG_FSL_SATA_V2 471 #define CONFIG_SYS_SATA_MAX_DEVICE 2 472 #define CONFIG_SATA1 473 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 474 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 475 #define CONFIG_SATA2 476 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 477 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 478 479 #define CONFIG_LBA48 480 #endif 481 482 #ifdef CONFIG_FMAN_ENET 483 #define CONFIG_MII /* MII PHY management */ 484 #define CONFIG_ETHPRIME "FM1@DTSEC1" 485 #endif 486 487 /* 488 * USB 489 */ 490 #define CONFIG_USB_EHCI_FSL 491 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 492 #define CONFIG_HAS_FSL_DR_USB 493 494 #ifdef CONFIG_MMC 495 #define CONFIG_FSL_ESDHC 496 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 497 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 498 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 499 #define CONFIG_ESDHC_DETECT_QUIRK \ 500 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 501 IS_SVR_REV(get_svr(), 1, 0)) 502 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 503 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 504 #endif 505 506 507 #define __USB_PHY_TYPE utmi 508 509 /* 510 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 511 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 512 * interleaving. It can be cacheline, page, bank, superbank. 513 * See doc/README.fsl-ddr for details. 514 */ 515 #ifdef CONFIG_ARCH_T4240 516 #define CTRL_INTLV_PREFERED 3way_4KB 517 #else 518 #define CTRL_INTLV_PREFERED cacheline 519 #endif 520 521 #define CONFIG_EXTRA_ENV_SETTINGS \ 522 "hwconfig=fsl_ddr:" \ 523 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 524 "bank_intlv=auto;" \ 525 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 526 "netdev=eth0\0" \ 527 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 528 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 529 "tftpflash=tftpboot $loadaddr $uboot && " \ 530 "protect off $ubootaddr +$filesize && " \ 531 "erase $ubootaddr +$filesize && " \ 532 "cp.b $loadaddr $ubootaddr $filesize && " \ 533 "protect on $ubootaddr +$filesize && " \ 534 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 535 "consoledev=ttyS0\0" \ 536 "ramdiskaddr=2000000\0" \ 537 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 538 "fdtaddr=1e00000\0" \ 539 "fdtfile=t4240qds/t4240qds.dtb\0" \ 540 "bdev=sda3\0" 541 542 #define CONFIG_HVBOOT \ 543 "setenv bootargs config-addr=0x60000000; " \ 544 "bootm 0x01000000 - 0x00f00000" 545 546 #define CONFIG_ALU \ 547 "setenv bootargs root=/dev/$bdev rw " \ 548 "console=$consoledev,$baudrate $othbootargs;" \ 549 "cpu 1 release 0x01000000 - - -;" \ 550 "cpu 2 release 0x01000000 - - -;" \ 551 "cpu 3 release 0x01000000 - - -;" \ 552 "cpu 4 release 0x01000000 - - -;" \ 553 "cpu 5 release 0x01000000 - - -;" \ 554 "cpu 6 release 0x01000000 - - -;" \ 555 "cpu 7 release 0x01000000 - - -;" \ 556 "go 0x01000000" 557 558 #define CONFIG_LINUX \ 559 "setenv bootargs root=/dev/ram rw " \ 560 "console=$consoledev,$baudrate $othbootargs;" \ 561 "setenv ramdiskaddr 0x02000000;" \ 562 "setenv fdtaddr 0x00c00000;" \ 563 "setenv loadaddr 0x1000000;" \ 564 "bootm $loadaddr $ramdiskaddr $fdtaddr" 565 566 #define CONFIG_HDBOOT \ 567 "setenv bootargs root=/dev/$bdev rw " \ 568 "console=$consoledev,$baudrate $othbootargs;" \ 569 "tftp $loadaddr $bootfile;" \ 570 "tftp $fdtaddr $fdtfile;" \ 571 "bootm $loadaddr - $fdtaddr" 572 573 #define CONFIG_NFSBOOTCOMMAND \ 574 "setenv bootargs root=/dev/nfs rw " \ 575 "nfsroot=$serverip:$rootpath " \ 576 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 577 "console=$consoledev,$baudrate $othbootargs;" \ 578 "tftp $loadaddr $bootfile;" \ 579 "tftp $fdtaddr $fdtfile;" \ 580 "bootm $loadaddr - $fdtaddr" 581 582 #define CONFIG_RAMBOOTCOMMAND \ 583 "setenv bootargs root=/dev/ram rw " \ 584 "console=$consoledev,$baudrate $othbootargs;" \ 585 "tftp $ramdiskaddr $ramdiskfile;" \ 586 "tftp $loadaddr $bootfile;" \ 587 "tftp $fdtaddr $fdtfile;" \ 588 "bootm $loadaddr $ramdiskaddr $fdtaddr" 589 590 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 591 592 #include <asm/fsl_secure_boot.h> 593 594 #endif /* __CONFIG_H */ 595