1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240QDS 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 23 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg 24 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 25 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 26 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 27 #else 28 #define CONFIG_SPL_FLUSH_IMAGE 29 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 30 #define CONFIG_FSL_LAW /* Use common FSL init code */ 31 #define CONFIG_SYS_TEXT_BASE 0x00201000 32 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 33 #define CONFIG_SPL_PAD_TO 0x40000 34 #define CONFIG_SPL_MAX_SIZE 0x28000 35 #define RESET_VECTOR_OFFSET 0x27FFC 36 #define BOOT_PAGE_OFFSET 0x27000 37 38 #ifdef CONFIG_NAND 39 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 40 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 41 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 42 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 44 #define CONFIG_SPL_NAND_BOOT 45 #endif 46 47 #ifdef CONFIG_SDCARD 48 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 49 #define CONFIG_SPL_MMC_MINIMAL 50 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 52 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 54 #ifndef CONFIG_SPL_BUILD 55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 56 #endif 57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 58 #define CONFIG_SPL_MMC_BOOT 59 #endif 60 61 #ifdef CONFIG_SPL_BUILD 62 #define CONFIG_SPL_SKIP_RELOCATE 63 #define CONFIG_SPL_COMMON_INIT_DDR 64 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 65 #define CONFIG_SYS_NO_FLASH 66 #endif 67 68 #endif 69 #endif /* CONFIG_RAMBOOT_PBL */ 70 71 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 72 /* Set 1M boot space */ 73 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 74 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 75 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 76 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 77 #define CONFIG_SYS_NO_FLASH 78 #endif 79 80 #define CONFIG_SRIO_PCIE_BOOT_MASTER 81 #define CONFIG_DDR_ECC 82 83 #include "t4qds.h" 84 85 #ifdef CONFIG_SYS_NO_FLASH 86 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 87 #define CONFIG_ENV_IS_NOWHERE 88 #endif 89 #else 90 #define CONFIG_FLASH_CFI_DRIVER 91 #define CONFIG_SYS_FLASH_CFI 92 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 93 #endif 94 95 #if defined(CONFIG_SPIFLASH) 96 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_ENV_IS_IN_SPI_FLASH 98 #define CONFIG_ENV_SPI_BUS 0 99 #define CONFIG_ENV_SPI_CS 0 100 #define CONFIG_ENV_SPI_MAX_HZ 10000000 101 #define CONFIG_ENV_SPI_MODE 0 102 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 103 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 104 #define CONFIG_ENV_SECT_SIZE 0x10000 105 #elif defined(CONFIG_SDCARD) 106 #define CONFIG_SYS_EXTRA_ENV_RELOC 107 #define CONFIG_ENV_IS_IN_MMC 108 #define CONFIG_SYS_MMC_ENV_DEV 0 109 #define CONFIG_ENV_SIZE 0x2000 110 #define CONFIG_ENV_OFFSET (512 * 0x800) 111 #elif defined(CONFIG_NAND) 112 #define CONFIG_SYS_EXTRA_ENV_RELOC 113 #define CONFIG_ENV_IS_IN_NAND 114 #define CONFIG_ENV_SIZE 0x2000 115 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 116 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 117 #define CONFIG_ENV_IS_IN_REMOTE 118 #define CONFIG_ENV_ADDR 0xffe20000 119 #define CONFIG_ENV_SIZE 0x2000 120 #elif defined(CONFIG_ENV_IS_NOWHERE) 121 #define CONFIG_ENV_SIZE 0x2000 122 #else 123 #define CONFIG_ENV_IS_IN_FLASH 124 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 125 #define CONFIG_ENV_SIZE 0x2000 126 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 127 #endif 128 129 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 130 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 131 132 #ifndef __ASSEMBLY__ 133 unsigned long get_board_sys_clk(void); 134 unsigned long get_board_ddr_clk(void); 135 #endif 136 137 /* EEPROM */ 138 #define CONFIG_ID_EEPROM 139 #define CONFIG_SYS_I2C_EEPROM_NXID 140 #define CONFIG_SYS_EEPROM_BUS_NUM 0 141 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 142 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 143 144 /* 145 * DDR Setup 146 */ 147 #define CONFIG_SYS_SPD_BUS_NUM 0 148 #define SPD_EEPROM_ADDRESS1 0x51 149 #define SPD_EEPROM_ADDRESS2 0x52 150 #define SPD_EEPROM_ADDRESS3 0x53 151 #define SPD_EEPROM_ADDRESS4 0x54 152 #define SPD_EEPROM_ADDRESS5 0x55 153 #define SPD_EEPROM_ADDRESS6 0x56 154 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 155 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 156 157 /* 158 * IFC Definitions 159 */ 160 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 161 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 162 + 0x8000000) | \ 163 CSPR_PORT_SIZE_16 | \ 164 CSPR_MSEL_NOR | \ 165 CSPR_V) 166 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 167 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 168 CSPR_PORT_SIZE_16 | \ 169 CSPR_MSEL_NOR | \ 170 CSPR_V) 171 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 172 /* NOR Flash Timing Params */ 173 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 174 175 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 176 FTIM0_NOR_TEADC(0x5) | \ 177 FTIM0_NOR_TEAHC(0x5)) 178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 179 FTIM1_NOR_TRAD_NOR(0x1A) |\ 180 FTIM1_NOR_TSEQRAD_NOR(0x13)) 181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 182 FTIM2_NOR_TCH(0x4) | \ 183 FTIM2_NOR_TWPH(0x0E) | \ 184 FTIM2_NOR_TWP(0x1c)) 185 #define CONFIG_SYS_NOR_FTIM3 0x0 186 187 #define CONFIG_SYS_FLASH_QUIET_TEST 188 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 189 190 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 191 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 194 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 197 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 198 199 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 200 #define QIXIS_BASE 0xffdf0000 201 #define QIXIS_LBMAP_SWITCH 6 202 #define QIXIS_LBMAP_MASK 0x0f 203 #define QIXIS_LBMAP_SHIFT 0 204 #define QIXIS_LBMAP_DFLTBANK 0x00 205 #define QIXIS_LBMAP_ALTBANK 0x04 206 #define QIXIS_RST_CTL_RESET 0x83 207 #define QIXIS_RST_FORCE_MEM 0x1 208 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 209 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 210 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 211 #define QIXIS_BRDCFG5 0x55 212 #define QIXIS_MUX_SDHC 2 213 #define QIXIS_MUX_SDHC_WIDTH8 1 214 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 215 216 #define CONFIG_SYS_CSPR3_EXT (0xf) 217 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 218 | CSPR_PORT_SIZE_8 \ 219 | CSPR_MSEL_GPCM \ 220 | CSPR_V) 221 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 222 #define CONFIG_SYS_CSOR3 0x0 223 /* QIXIS Timing parameters for IFC CS3 */ 224 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 225 FTIM0_GPCM_TEADC(0x0e) | \ 226 FTIM0_GPCM_TEAHC(0x0e)) 227 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 228 FTIM1_GPCM_TRAD(0x3f)) 229 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 230 FTIM2_GPCM_TCH(0x8) | \ 231 FTIM2_GPCM_TWP(0x1f)) 232 #define CONFIG_SYS_CS3_FTIM3 0x0 233 234 /* NAND Flash on IFC */ 235 #define CONFIG_NAND_FSL_IFC 236 #define CONFIG_SYS_NAND_BASE 0xff800000 237 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 238 239 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 240 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 241 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 242 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 243 | CSPR_V) 244 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 245 246 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 247 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 248 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 249 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 250 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 251 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 252 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 253 254 #define CONFIG_SYS_NAND_ONFI_DETECTION 255 256 /* ONFI NAND Flash mode0 Timing Params */ 257 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 258 FTIM0_NAND_TWP(0x18) | \ 259 FTIM0_NAND_TWCHT(0x07) | \ 260 FTIM0_NAND_TWH(0x0a)) 261 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 262 FTIM1_NAND_TWBE(0x39) | \ 263 FTIM1_NAND_TRR(0x0e) | \ 264 FTIM1_NAND_TRP(0x18)) 265 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 266 FTIM2_NAND_TREH(0x0a) | \ 267 FTIM2_NAND_TWHRE(0x1e)) 268 #define CONFIG_SYS_NAND_FTIM3 0x0 269 270 #define CONFIG_SYS_NAND_DDR_LAW 11 271 272 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 273 #define CONFIG_SYS_MAX_NAND_DEVICE 1 274 #define CONFIG_CMD_NAND 275 276 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 277 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 278 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 279 280 #if defined(CONFIG_NAND) 281 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 282 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 283 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 284 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 285 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 286 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 287 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 288 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 289 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 290 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 291 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 292 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 293 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 294 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 295 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 296 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 297 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 298 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 299 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 300 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 301 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 302 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 303 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 304 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 305 #else 306 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 307 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 308 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 309 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 310 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 311 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 312 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 313 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 314 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 315 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 316 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 317 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 318 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 319 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 320 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 321 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 322 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 323 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 324 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 325 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 326 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 327 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 328 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 329 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 330 #endif 331 332 #if defined(CONFIG_RAMBOOT_PBL) 333 #define CONFIG_SYS_RAMBOOT 334 #endif 335 336 /* I2C */ 337 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 338 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 339 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 340 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 341 342 #define I2C_MUX_CH_DEFAULT 0x8 343 #define I2C_MUX_CH_VOL_MONITOR 0xa 344 #define I2C_MUX_CH_VSC3316_FS 0xc 345 #define I2C_MUX_CH_VSC3316_BS 0xd 346 347 /* Voltage monitor on channel 2*/ 348 #define I2C_VOL_MONITOR_ADDR 0x40 349 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 350 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 351 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 352 353 /* VSC Crossbar switches */ 354 #define CONFIG_VSC_CROSSBAR 355 #define VSC3316_FSM_TX_ADDR 0x70 356 #define VSC3316_FSM_RX_ADDR 0x71 357 358 /* 359 * RapidIO 360 */ 361 362 /* 363 * for slave u-boot IMAGE instored in master memory space, 364 * PHYS must be aligned based on the SIZE 365 */ 366 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 367 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 368 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 369 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 370 /* 371 * for slave UCODE and ENV instored in master memory space, 372 * PHYS must be aligned based on the SIZE 373 */ 374 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 375 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 376 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 377 378 /* slave core release by master*/ 379 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 380 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 381 382 /* 383 * SRIO_PCIE_BOOT - SLAVE 384 */ 385 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 386 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 387 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 388 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 389 #endif 390 /* 391 * eSPI - Enhanced SPI 392 */ 393 #define CONFIG_SF_DEFAULT_SPEED 10000000 394 #define CONFIG_SF_DEFAULT_MODE 0 395 396 /* Qman/Bman */ 397 #ifndef CONFIG_NOBQFMAN 398 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 399 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 400 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 401 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 402 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 403 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 404 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 405 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 406 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 407 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 408 CONFIG_SYS_BMAN_CENA_SIZE) 409 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 410 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 411 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 412 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 413 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 414 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 415 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 416 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 417 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 418 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 419 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 420 CONFIG_SYS_QMAN_CENA_SIZE) 421 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 422 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 423 424 #define CONFIG_SYS_DPAA_FMAN 425 #define CONFIG_SYS_DPAA_PME 426 #define CONFIG_SYS_PMAN 427 #define CONFIG_SYS_DPAA_DCE 428 #define CONFIG_SYS_DPAA_RMAN 429 #define CONFIG_SYS_INTERLAKEN 430 431 /* Default address of microcode for the Linux Fman driver */ 432 #if defined(CONFIG_SPIFLASH) 433 /* 434 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 435 * env, so we got 0x110000. 436 */ 437 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 438 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 439 #elif defined(CONFIG_SDCARD) 440 /* 441 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 442 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 443 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 444 */ 445 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 446 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 447 #elif defined(CONFIG_NAND) 448 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 449 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 450 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 451 /* 452 * Slave has no ucode locally, it can fetch this from remote. When implementing 453 * in two corenet boards, slave's ucode could be stored in master's memory 454 * space, the address can be mapped from slave TLB->slave LAW-> 455 * slave SRIO or PCIE outbound window->master inbound window-> 456 * master LAW->the ucode address in master's memory space. 457 */ 458 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 459 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 460 #else 461 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 462 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 463 #endif 464 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 465 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 466 #endif /* CONFIG_NOBQFMAN */ 467 468 #ifdef CONFIG_SYS_DPAA_FMAN 469 #define CONFIG_FMAN_ENET 470 #define CONFIG_PHYLIB_10G 471 #define CONFIG_PHY_VITESSE 472 #define CONFIG_PHY_TERANETICS 473 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 474 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 475 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 476 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 477 #define FM1_10GEC1_PHY_ADDR 0x0 478 #define FM1_10GEC2_PHY_ADDR 0x1 479 #define FM2_10GEC1_PHY_ADDR 0x2 480 #define FM2_10GEC2_PHY_ADDR 0x3 481 #endif 482 483 /* SATA */ 484 #ifdef CONFIG_FSL_SATA_V2 485 #define CONFIG_LIBATA 486 #define CONFIG_FSL_SATA 487 488 #define CONFIG_SYS_SATA_MAX_DEVICE 2 489 #define CONFIG_SATA1 490 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 491 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 492 #define CONFIG_SATA2 493 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 494 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 495 496 #define CONFIG_LBA48 497 #define CONFIG_CMD_SATA 498 #define CONFIG_DOS_PARTITION 499 #endif 500 501 #ifdef CONFIG_FMAN_ENET 502 #define CONFIG_MII /* MII PHY management */ 503 #define CONFIG_ETHPRIME "FM1@DTSEC1" 504 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 505 #endif 506 507 /* Hash command with SHA acceleration supported in hardware */ 508 #ifdef CONFIG_FSL_CAAM 509 #define CONFIG_CMD_HASH 510 #define CONFIG_SHA_HW_ACCEL 511 #endif 512 513 /* 514 * USB 515 */ 516 #define CONFIG_USB_EHCI 517 #define CONFIG_USB_EHCI_FSL 518 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 519 #define CONFIG_HAS_FSL_DR_USB 520 521 #define CONFIG_MMC 522 523 #ifdef CONFIG_MMC 524 #define CONFIG_FSL_ESDHC 525 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 526 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 527 #define CONFIG_GENERIC_MMC 528 #define CONFIG_DOS_PARTITION 529 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 530 #define CONFIG_ESDHC_DETECT_QUIRK \ 531 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 532 IS_SVR_REV(get_svr(), 1, 0)) 533 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 534 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 535 #endif 536 537 538 #define __USB_PHY_TYPE utmi 539 540 /* 541 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 542 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 543 * interleaving. It can be cacheline, page, bank, superbank. 544 * See doc/README.fsl-ddr for details. 545 */ 546 #ifdef CONFIG_PPC_T4240 547 #define CTRL_INTLV_PREFERED 3way_4KB 548 #else 549 #define CTRL_INTLV_PREFERED cacheline 550 #endif 551 552 #define CONFIG_EXTRA_ENV_SETTINGS \ 553 "hwconfig=fsl_ddr:" \ 554 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 555 "bank_intlv=auto;" \ 556 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 557 "netdev=eth0\0" \ 558 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 559 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 560 "tftpflash=tftpboot $loadaddr $uboot && " \ 561 "protect off $ubootaddr +$filesize && " \ 562 "erase $ubootaddr +$filesize && " \ 563 "cp.b $loadaddr $ubootaddr $filesize && " \ 564 "protect on $ubootaddr +$filesize && " \ 565 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 566 "consoledev=ttyS0\0" \ 567 "ramdiskaddr=2000000\0" \ 568 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 569 "fdtaddr=1e00000\0" \ 570 "fdtfile=t4240qds/t4240qds.dtb\0" \ 571 "bdev=sda3\0" 572 573 #define CONFIG_HVBOOT \ 574 "setenv bootargs config-addr=0x60000000; " \ 575 "bootm 0x01000000 - 0x00f00000" 576 577 #define CONFIG_ALU \ 578 "setenv bootargs root=/dev/$bdev rw " \ 579 "console=$consoledev,$baudrate $othbootargs;" \ 580 "cpu 1 release 0x01000000 - - -;" \ 581 "cpu 2 release 0x01000000 - - -;" \ 582 "cpu 3 release 0x01000000 - - -;" \ 583 "cpu 4 release 0x01000000 - - -;" \ 584 "cpu 5 release 0x01000000 - - -;" \ 585 "cpu 6 release 0x01000000 - - -;" \ 586 "cpu 7 release 0x01000000 - - -;" \ 587 "go 0x01000000" 588 589 #define CONFIG_LINUX \ 590 "setenv bootargs root=/dev/ram rw " \ 591 "console=$consoledev,$baudrate $othbootargs;" \ 592 "setenv ramdiskaddr 0x02000000;" \ 593 "setenv fdtaddr 0x00c00000;" \ 594 "setenv loadaddr 0x1000000;" \ 595 "bootm $loadaddr $ramdiskaddr $fdtaddr" 596 597 #define CONFIG_HDBOOT \ 598 "setenv bootargs root=/dev/$bdev rw " \ 599 "console=$consoledev,$baudrate $othbootargs;" \ 600 "tftp $loadaddr $bootfile;" \ 601 "tftp $fdtaddr $fdtfile;" \ 602 "bootm $loadaddr - $fdtaddr" 603 604 #define CONFIG_NFSBOOTCOMMAND \ 605 "setenv bootargs root=/dev/nfs rw " \ 606 "nfsroot=$serverip:$rootpath " \ 607 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 608 "console=$consoledev,$baudrate $othbootargs;" \ 609 "tftp $loadaddr $bootfile;" \ 610 "tftp $fdtaddr $fdtfile;" \ 611 "bootm $loadaddr - $fdtaddr" 612 613 #define CONFIG_RAMBOOTCOMMAND \ 614 "setenv bootargs root=/dev/ram rw " \ 615 "console=$consoledev,$baudrate $othbootargs;" \ 616 "tftp $ramdiskaddr $ramdiskfile;" \ 617 "tftp $loadaddr $bootfile;" \ 618 "tftp $fdtaddr $fdtfile;" \ 619 "bootm $loadaddr $ramdiskaddr $fdtaddr" 620 621 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 622 623 #include <asm/fsl_secure_boot.h> 624 625 #endif /* __CONFIG_H */ 626