1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 16 17 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 21 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 22 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 23 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 24 #else 25 #define CONFIG_SPL_FLUSH_IMAGE 26 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 27 #define CONFIG_FSL_LAW /* Use common FSL init code */ 28 #define CONFIG_SYS_TEXT_BASE 0x00201000 29 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 30 #define CONFIG_SPL_PAD_TO 0x40000 31 #define CONFIG_SPL_MAX_SIZE 0x28000 32 #define RESET_VECTOR_OFFSET 0x27FFC 33 #define BOOT_PAGE_OFFSET 0x27000 34 35 #ifdef CONFIG_NAND 36 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 37 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 38 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 39 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 40 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 41 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg 42 #define CONFIG_SPL_NAND_BOOT 43 #endif 44 45 #ifdef CONFIG_SDCARD 46 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 47 #define CONFIG_SPL_MMC_MINIMAL 48 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 49 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 50 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 51 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 52 #ifndef CONFIG_SPL_BUILD 53 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 54 #endif 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg 57 #define CONFIG_SPL_MMC_BOOT 58 #endif 59 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SPL_SKIP_RELOCATE 62 #define CONFIG_SPL_COMMON_INIT_DDR 63 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 64 #define CONFIG_SYS_NO_FLASH 65 #endif 66 67 #endif 68 #endif /* CONFIG_RAMBOOT_PBL */ 69 70 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 71 /* Set 1M boot space */ 72 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 73 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 74 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 75 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 76 #define CONFIG_SYS_NO_FLASH 77 #endif 78 79 #define CONFIG_SRIO_PCIE_BOOT_MASTER 80 #define CONFIG_DDR_ECC 81 82 #include "t4qds.h" 83 84 #ifdef CONFIG_SYS_NO_FLASH 85 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 86 #define CONFIG_ENV_IS_NOWHERE 87 #endif 88 #else 89 #define CONFIG_FLASH_CFI_DRIVER 90 #define CONFIG_SYS_FLASH_CFI 91 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 92 #endif 93 94 #if defined(CONFIG_SPIFLASH) 95 #define CONFIG_SYS_EXTRA_ENV_RELOC 96 #define CONFIG_ENV_IS_IN_SPI_FLASH 97 #define CONFIG_ENV_SPI_BUS 0 98 #define CONFIG_ENV_SPI_CS 0 99 #define CONFIG_ENV_SPI_MAX_HZ 10000000 100 #define CONFIG_ENV_SPI_MODE 0 101 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 102 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 103 #define CONFIG_ENV_SECT_SIZE 0x10000 104 #elif defined(CONFIG_SDCARD) 105 #define CONFIG_SYS_EXTRA_ENV_RELOC 106 #define CONFIG_ENV_IS_IN_MMC 107 #define CONFIG_SYS_MMC_ENV_DEV 0 108 #define CONFIG_ENV_SIZE 0x2000 109 #define CONFIG_ENV_OFFSET (512 * 0x800) 110 #elif defined(CONFIG_NAND) 111 #define CONFIG_SYS_EXTRA_ENV_RELOC 112 #define CONFIG_ENV_IS_IN_NAND 113 #define CONFIG_ENV_SIZE 0x2000 114 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 115 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 116 #define CONFIG_ENV_IS_IN_REMOTE 117 #define CONFIG_ENV_ADDR 0xffe20000 118 #define CONFIG_ENV_SIZE 0x2000 119 #elif defined(CONFIG_ENV_IS_NOWHERE) 120 #define CONFIG_ENV_SIZE 0x2000 121 #else 122 #define CONFIG_ENV_IS_IN_FLASH 123 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 124 #define CONFIG_ENV_SIZE 0x2000 125 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 126 #endif 127 128 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 129 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 130 131 #ifndef __ASSEMBLY__ 132 unsigned long get_board_sys_clk(void); 133 unsigned long get_board_ddr_clk(void); 134 #endif 135 136 /* EEPROM */ 137 #define CONFIG_ID_EEPROM 138 #define CONFIG_SYS_I2C_EEPROM_NXID 139 #define CONFIG_SYS_EEPROM_BUS_NUM 0 140 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 141 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 142 143 /* 144 * DDR Setup 145 */ 146 #define CONFIG_SYS_SPD_BUS_NUM 0 147 #define SPD_EEPROM_ADDRESS1 0x51 148 #define SPD_EEPROM_ADDRESS2 0x52 149 #define SPD_EEPROM_ADDRESS3 0x53 150 #define SPD_EEPROM_ADDRESS4 0x54 151 #define SPD_EEPROM_ADDRESS5 0x55 152 #define SPD_EEPROM_ADDRESS6 0x56 153 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 154 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 155 156 /* 157 * IFC Definitions 158 */ 159 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 160 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 161 + 0x8000000) | \ 162 CSPR_PORT_SIZE_16 | \ 163 CSPR_MSEL_NOR | \ 164 CSPR_V) 165 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 166 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 167 CSPR_PORT_SIZE_16 | \ 168 CSPR_MSEL_NOR | \ 169 CSPR_V) 170 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 171 /* NOR Flash Timing Params */ 172 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 173 174 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 175 FTIM0_NOR_TEADC(0x5) | \ 176 FTIM0_NOR_TEAHC(0x5)) 177 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 178 FTIM1_NOR_TRAD_NOR(0x1A) |\ 179 FTIM1_NOR_TSEQRAD_NOR(0x13)) 180 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 181 FTIM2_NOR_TCH(0x4) | \ 182 FTIM2_NOR_TWPH(0x0E) | \ 183 FTIM2_NOR_TWP(0x1c)) 184 #define CONFIG_SYS_NOR_FTIM3 0x0 185 186 #define CONFIG_SYS_FLASH_QUIET_TEST 187 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 188 189 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 190 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 191 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 192 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 193 194 #define CONFIG_SYS_FLASH_EMPTY_INFO 195 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 196 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 197 198 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 199 #define QIXIS_BASE 0xffdf0000 200 #define QIXIS_LBMAP_SWITCH 6 201 #define QIXIS_LBMAP_MASK 0x0f 202 #define QIXIS_LBMAP_SHIFT 0 203 #define QIXIS_LBMAP_DFLTBANK 0x00 204 #define QIXIS_LBMAP_ALTBANK 0x04 205 #define QIXIS_RST_CTL_RESET 0x83 206 #define QIXIS_RST_FORCE_MEM 0x1 207 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 208 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 209 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 210 #define QIXIS_BRDCFG5 0x55 211 #define QIXIS_MUX_SDHC 2 212 #define QIXIS_MUX_SDHC_WIDTH8 1 213 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 214 215 #define CONFIG_SYS_CSPR3_EXT (0xf) 216 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 217 | CSPR_PORT_SIZE_8 \ 218 | CSPR_MSEL_GPCM \ 219 | CSPR_V) 220 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 221 #define CONFIG_SYS_CSOR3 0x0 222 /* QIXIS Timing parameters for IFC CS3 */ 223 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 224 FTIM0_GPCM_TEADC(0x0e) | \ 225 FTIM0_GPCM_TEAHC(0x0e)) 226 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 227 FTIM1_GPCM_TRAD(0x3f)) 228 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 229 FTIM2_GPCM_TCH(0x8) | \ 230 FTIM2_GPCM_TWP(0x1f)) 231 #define CONFIG_SYS_CS3_FTIM3 0x0 232 233 /* NAND Flash on IFC */ 234 #define CONFIG_NAND_FSL_IFC 235 #define CONFIG_SYS_NAND_BASE 0xff800000 236 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 237 238 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 239 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 240 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 241 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 242 | CSPR_V) 243 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 244 245 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 246 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 247 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 248 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 249 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 250 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 251 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 252 253 #define CONFIG_SYS_NAND_ONFI_DETECTION 254 255 /* ONFI NAND Flash mode0 Timing Params */ 256 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 257 FTIM0_NAND_TWP(0x18) | \ 258 FTIM0_NAND_TWCHT(0x07) | \ 259 FTIM0_NAND_TWH(0x0a)) 260 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 261 FTIM1_NAND_TWBE(0x39) | \ 262 FTIM1_NAND_TRR(0x0e) | \ 263 FTIM1_NAND_TRP(0x18)) 264 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 265 FTIM2_NAND_TREH(0x0a) | \ 266 FTIM2_NAND_TWHRE(0x1e)) 267 #define CONFIG_SYS_NAND_FTIM3 0x0 268 269 #define CONFIG_SYS_NAND_DDR_LAW 11 270 271 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 272 #define CONFIG_SYS_MAX_NAND_DEVICE 1 273 #define CONFIG_CMD_NAND 274 275 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 276 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 277 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 278 279 #if defined(CONFIG_NAND) 280 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 281 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 282 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 283 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 284 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 285 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 286 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 287 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 288 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 289 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 290 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 291 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 292 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 293 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 294 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 295 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 296 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 297 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 298 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 299 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 300 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 301 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 302 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 303 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 304 #else 305 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 306 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 307 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 308 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 309 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 310 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 311 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 312 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 313 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 314 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 315 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 316 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 317 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 318 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 319 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 320 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 321 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 322 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 323 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 324 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 325 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 326 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 327 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 328 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 329 #endif 330 331 #if defined(CONFIG_RAMBOOT_PBL) 332 #define CONFIG_SYS_RAMBOOT 333 #endif 334 335 /* I2C */ 336 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 337 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 338 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 339 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 340 341 #define I2C_MUX_CH_DEFAULT 0x8 342 #define I2C_MUX_CH_VOL_MONITOR 0xa 343 #define I2C_MUX_CH_VSC3316_FS 0xc 344 #define I2C_MUX_CH_VSC3316_BS 0xd 345 346 /* Voltage monitor on channel 2*/ 347 #define I2C_VOL_MONITOR_ADDR 0x40 348 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 349 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 350 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 351 352 /* VSC Crossbar switches */ 353 #define CONFIG_VSC_CROSSBAR 354 #define VSC3316_FSM_TX_ADDR 0x70 355 #define VSC3316_FSM_RX_ADDR 0x71 356 357 /* 358 * RapidIO 359 */ 360 361 /* 362 * for slave u-boot IMAGE instored in master memory space, 363 * PHYS must be aligned based on the SIZE 364 */ 365 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 366 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 367 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 368 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 369 /* 370 * for slave UCODE and ENV instored in master memory space, 371 * PHYS must be aligned based on the SIZE 372 */ 373 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 374 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 375 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 376 377 /* slave core release by master*/ 378 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 379 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 380 381 /* 382 * SRIO_PCIE_BOOT - SLAVE 383 */ 384 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 385 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 386 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 387 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 388 #endif 389 /* 390 * eSPI - Enhanced SPI 391 */ 392 #define CONFIG_SF_DEFAULT_SPEED 10000000 393 #define CONFIG_SF_DEFAULT_MODE 0 394 395 /* Qman/Bman */ 396 #ifndef CONFIG_NOBQFMAN 397 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 398 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 399 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 400 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 401 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 402 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 403 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 404 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 405 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 406 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 407 CONFIG_SYS_BMAN_CENA_SIZE) 408 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 409 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 410 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 411 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 412 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 413 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 414 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 415 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 416 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 417 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 418 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 419 CONFIG_SYS_QMAN_CENA_SIZE) 420 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 421 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 422 423 #define CONFIG_SYS_DPAA_FMAN 424 #define CONFIG_SYS_DPAA_PME 425 #define CONFIG_SYS_PMAN 426 #define CONFIG_SYS_DPAA_DCE 427 #define CONFIG_SYS_DPAA_RMAN 428 #define CONFIG_SYS_INTERLAKEN 429 430 /* Default address of microcode for the Linux Fman driver */ 431 #if defined(CONFIG_SPIFLASH) 432 /* 433 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 434 * env, so we got 0x110000. 435 */ 436 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 437 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 438 #elif defined(CONFIG_SDCARD) 439 /* 440 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 441 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 442 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 443 */ 444 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 445 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 446 #elif defined(CONFIG_NAND) 447 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 448 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 449 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 450 /* 451 * Slave has no ucode locally, it can fetch this from remote. When implementing 452 * in two corenet boards, slave's ucode could be stored in master's memory 453 * space, the address can be mapped from slave TLB->slave LAW-> 454 * slave SRIO or PCIE outbound window->master inbound window-> 455 * master LAW->the ucode address in master's memory space. 456 */ 457 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 458 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 459 #else 460 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 461 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 462 #endif 463 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 464 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 465 #endif /* CONFIG_NOBQFMAN */ 466 467 #ifdef CONFIG_SYS_DPAA_FMAN 468 #define CONFIG_FMAN_ENET 469 #define CONFIG_PHYLIB_10G 470 #define CONFIG_PHY_VITESSE 471 #define CONFIG_PHY_TERANETICS 472 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 473 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 474 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 475 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 476 #define FM1_10GEC1_PHY_ADDR 0x0 477 #define FM1_10GEC2_PHY_ADDR 0x1 478 #define FM2_10GEC1_PHY_ADDR 0x2 479 #define FM2_10GEC2_PHY_ADDR 0x3 480 #endif 481 482 /* SATA */ 483 #ifdef CONFIG_FSL_SATA_V2 484 #define CONFIG_LIBATA 485 #define CONFIG_FSL_SATA 486 487 #define CONFIG_SYS_SATA_MAX_DEVICE 2 488 #define CONFIG_SATA1 489 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 490 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 491 #define CONFIG_SATA2 492 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 493 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 494 495 #define CONFIG_LBA48 496 #define CONFIG_CMD_SATA 497 #define CONFIG_DOS_PARTITION 498 #endif 499 500 #ifdef CONFIG_FMAN_ENET 501 #define CONFIG_MII /* MII PHY management */ 502 #define CONFIG_ETHPRIME "FM1@DTSEC1" 503 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 504 #endif 505 506 /* Hash command with SHA acceleration supported in hardware */ 507 #ifdef CONFIG_FSL_CAAM 508 #define CONFIG_CMD_HASH 509 #define CONFIG_SHA_HW_ACCEL 510 #endif 511 512 /* 513 * USB 514 */ 515 #define CONFIG_USB_EHCI 516 #define CONFIG_USB_EHCI_FSL 517 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 518 #define CONFIG_HAS_FSL_DR_USB 519 520 #define CONFIG_MMC 521 522 #ifdef CONFIG_MMC 523 #define CONFIG_FSL_ESDHC 524 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 525 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 526 #define CONFIG_GENERIC_MMC 527 #define CONFIG_DOS_PARTITION 528 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 529 #define CONFIG_ESDHC_DETECT_QUIRK \ 530 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 531 IS_SVR_REV(get_svr(), 1, 0)) 532 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 533 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 534 #endif 535 536 537 #define __USB_PHY_TYPE utmi 538 539 /* 540 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 541 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 542 * interleaving. It can be cacheline, page, bank, superbank. 543 * See doc/README.fsl-ddr for details. 544 */ 545 #ifdef CONFIG_ARCH_T4240 546 #define CTRL_INTLV_PREFERED 3way_4KB 547 #else 548 #define CTRL_INTLV_PREFERED cacheline 549 #endif 550 551 #define CONFIG_EXTRA_ENV_SETTINGS \ 552 "hwconfig=fsl_ddr:" \ 553 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 554 "bank_intlv=auto;" \ 555 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 556 "netdev=eth0\0" \ 557 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 558 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 559 "tftpflash=tftpboot $loadaddr $uboot && " \ 560 "protect off $ubootaddr +$filesize && " \ 561 "erase $ubootaddr +$filesize && " \ 562 "cp.b $loadaddr $ubootaddr $filesize && " \ 563 "protect on $ubootaddr +$filesize && " \ 564 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 565 "consoledev=ttyS0\0" \ 566 "ramdiskaddr=2000000\0" \ 567 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 568 "fdtaddr=1e00000\0" \ 569 "fdtfile=t4240qds/t4240qds.dtb\0" \ 570 "bdev=sda3\0" 571 572 #define CONFIG_HVBOOT \ 573 "setenv bootargs config-addr=0x60000000; " \ 574 "bootm 0x01000000 - 0x00f00000" 575 576 #define CONFIG_ALU \ 577 "setenv bootargs root=/dev/$bdev rw " \ 578 "console=$consoledev,$baudrate $othbootargs;" \ 579 "cpu 1 release 0x01000000 - - -;" \ 580 "cpu 2 release 0x01000000 - - -;" \ 581 "cpu 3 release 0x01000000 - - -;" \ 582 "cpu 4 release 0x01000000 - - -;" \ 583 "cpu 5 release 0x01000000 - - -;" \ 584 "cpu 6 release 0x01000000 - - -;" \ 585 "cpu 7 release 0x01000000 - - -;" \ 586 "go 0x01000000" 587 588 #define CONFIG_LINUX \ 589 "setenv bootargs root=/dev/ram rw " \ 590 "console=$consoledev,$baudrate $othbootargs;" \ 591 "setenv ramdiskaddr 0x02000000;" \ 592 "setenv fdtaddr 0x00c00000;" \ 593 "setenv loadaddr 0x1000000;" \ 594 "bootm $loadaddr $ramdiskaddr $fdtaddr" 595 596 #define CONFIG_HDBOOT \ 597 "setenv bootargs root=/dev/$bdev rw " \ 598 "console=$consoledev,$baudrate $othbootargs;" \ 599 "tftp $loadaddr $bootfile;" \ 600 "tftp $fdtaddr $fdtfile;" \ 601 "bootm $loadaddr - $fdtaddr" 602 603 #define CONFIG_NFSBOOTCOMMAND \ 604 "setenv bootargs root=/dev/nfs rw " \ 605 "nfsroot=$serverip:$rootpath " \ 606 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 607 "console=$consoledev,$baudrate $othbootargs;" \ 608 "tftp $loadaddr $bootfile;" \ 609 "tftp $fdtaddr $fdtfile;" \ 610 "bootm $loadaddr - $fdtaddr" 611 612 #define CONFIG_RAMBOOTCOMMAND \ 613 "setenv bootargs root=/dev/ram rw " \ 614 "console=$consoledev,$baudrate $othbootargs;" \ 615 "tftp $ramdiskaddr $ramdiskfile;" \ 616 "tftp $loadaddr $bootfile;" \ 617 "tftp $fdtaddr $fdtfile;" \ 618 "bootm $loadaddr $ramdiskaddr $fdtaddr" 619 620 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 621 622 #include <asm/fsl_secure_boot.h> 623 624 #endif /* __CONFIG_H */ 625