xref: /openbmc/u-boot/include/configs/T4240QDS.h (revision 85231c08)
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * T4240 QDS board configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #define CONFIG_FSL_SATA_V2
14 #define CONFIG_PCIE4
15 
16 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
17 
18 #ifdef CONFIG_RAMBOOT_PBL
19 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
20 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
23 #else
24 #define CONFIG_SPL_FLUSH_IMAGE
25 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
26 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
27 #define CONFIG_SPL_PAD_TO		0x40000
28 #define CONFIG_SPL_MAX_SIZE		0x28000
29 #define RESET_VECTOR_OFFSET		0x27FFC
30 #define BOOT_PAGE_OFFSET		0x27000
31 
32 #ifdef	CONFIG_NAND
33 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
34 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
35 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
36 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
37 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
38 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg
39 #define CONFIG_SPL_NAND_BOOT
40 #endif
41 
42 #ifdef	CONFIG_SDCARD
43 #define	CONFIG_RESET_VECTOR_ADDRESS	0x200FFC
44 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
45 #define CONFIG_SYS_MMC_U_BOOT_DST	0x00200000
46 #define CONFIG_SYS_MMC_U_BOOT_START	0x00200000
47 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
48 #ifndef CONFIG_SPL_BUILD
49 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
50 #endif
51 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg
53 #define CONFIG_SPL_MMC_BOOT
54 #endif
55 
56 #ifdef CONFIG_SPL_BUILD
57 #define CONFIG_SPL_SKIP_RELOCATE
58 #define CONFIG_SPL_COMMON_INIT_DDR
59 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
60 #endif
61 
62 #endif
63 #endif /* CONFIG_RAMBOOT_PBL */
64 
65 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
66 /* Set 1M boot space */
67 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
68 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
69 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
70 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
71 #endif
72 
73 #define CONFIG_SRIO_PCIE_BOOT_MASTER
74 #define CONFIG_DDR_ECC
75 
76 #include "t4qds.h"
77 
78 #ifndef CONFIG_MTD_NOR_FLASH
79 #else
80 #define CONFIG_FLASH_CFI_DRIVER
81 #define CONFIG_SYS_FLASH_CFI
82 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
83 #endif
84 
85 #if defined(CONFIG_SPIFLASH)
86 #define CONFIG_SYS_EXTRA_ENV_RELOC
87 #define CONFIG_ENV_SPI_BUS              0
88 #define CONFIG_ENV_SPI_CS               0
89 #define CONFIG_ENV_SPI_MAX_HZ           10000000
90 #define CONFIG_ENV_SPI_MODE             0
91 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
92 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
93 #define CONFIG_ENV_SECT_SIZE            0x10000
94 #elif defined(CONFIG_SDCARD)
95 #define CONFIG_SYS_EXTRA_ENV_RELOC
96 #define CONFIG_SYS_MMC_ENV_DEV          0
97 #define CONFIG_ENV_SIZE			0x2000
98 #define CONFIG_ENV_OFFSET		(512 * 0x800)
99 #elif defined(CONFIG_NAND)
100 #define CONFIG_SYS_EXTRA_ENV_RELOC
101 #define CONFIG_ENV_SIZE			0x2000
102 #define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
103 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
104 #define CONFIG_ENV_ADDR		0xffe20000
105 #define CONFIG_ENV_SIZE		0x2000
106 #elif defined(CONFIG_ENV_IS_NOWHERE)
107 #define CONFIG_ENV_SIZE		0x2000
108 #else
109 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
110 #define CONFIG_ENV_SIZE		0x2000
111 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
112 #endif
113 
114 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
115 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
116 
117 #ifndef __ASSEMBLY__
118 unsigned long get_board_sys_clk(void);
119 unsigned long get_board_ddr_clk(void);
120 #endif
121 
122 /* EEPROM */
123 #define CONFIG_ID_EEPROM
124 #define CONFIG_SYS_I2C_EEPROM_NXID
125 #define CONFIG_SYS_EEPROM_BUS_NUM	0
126 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
127 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
128 
129 /*
130  * DDR Setup
131  */
132 #define CONFIG_SYS_SPD_BUS_NUM	0
133 #define SPD_EEPROM_ADDRESS1	0x51
134 #define SPD_EEPROM_ADDRESS2	0x52
135 #define SPD_EEPROM_ADDRESS3	0x53
136 #define SPD_EEPROM_ADDRESS4	0x54
137 #define SPD_EEPROM_ADDRESS5	0x55
138 #define SPD_EEPROM_ADDRESS6	0x56
139 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
140 #define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
141 
142 /*
143  * IFC Definitions
144  */
145 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
146 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
147 				+ 0x8000000) | \
148 				CSPR_PORT_SIZE_16 | \
149 				CSPR_MSEL_NOR | \
150 				CSPR_V)
151 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
152 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
153 				CSPR_PORT_SIZE_16 | \
154 				CSPR_MSEL_NOR | \
155 				CSPR_V)
156 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
157 /* NOR Flash Timing Params */
158 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
159 
160 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
161 				FTIM0_NOR_TEADC(0x5) | \
162 				FTIM0_NOR_TEAHC(0x5))
163 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
164 				FTIM1_NOR_TRAD_NOR(0x1A) |\
165 				FTIM1_NOR_TSEQRAD_NOR(0x13))
166 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
167 				FTIM2_NOR_TCH(0x4) | \
168 				FTIM2_NOR_TWPH(0x0E) | \
169 				FTIM2_NOR_TWP(0x1c))
170 #define CONFIG_SYS_NOR_FTIM3	0x0
171 
172 #define CONFIG_SYS_FLASH_QUIET_TEST
173 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
174 
175 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
176 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
177 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
178 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
179 
180 #define CONFIG_SYS_FLASH_EMPTY_INFO
181 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
182 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
183 
184 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
185 #define QIXIS_BASE			0xffdf0000
186 #define QIXIS_LBMAP_SWITCH		6
187 #define QIXIS_LBMAP_MASK		0x0f
188 #define QIXIS_LBMAP_SHIFT		0
189 #define QIXIS_LBMAP_DFLTBANK		0x00
190 #define QIXIS_LBMAP_ALTBANK		0x04
191 #define QIXIS_RST_CTL_RESET		0x83
192 #define QIXIS_RST_FORCE_MEM		0x1
193 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
194 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
195 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
196 #define QIXIS_BRDCFG5			0x55
197 #define QIXIS_MUX_SDHC			2
198 #define QIXIS_MUX_SDHC_WIDTH8		1
199 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
200 
201 #define CONFIG_SYS_CSPR3_EXT	(0xf)
202 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
203 				| CSPR_PORT_SIZE_8 \
204 				| CSPR_MSEL_GPCM \
205 				| CSPR_V)
206 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
207 #define CONFIG_SYS_CSOR3	0x0
208 /* QIXIS Timing parameters for IFC CS3 */
209 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
210 					FTIM0_GPCM_TEADC(0x0e) | \
211 					FTIM0_GPCM_TEAHC(0x0e))
212 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
213 					FTIM1_GPCM_TRAD(0x3f))
214 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
215 					FTIM2_GPCM_TCH(0x8) | \
216 					FTIM2_GPCM_TWP(0x1f))
217 #define CONFIG_SYS_CS3_FTIM3		0x0
218 
219 /* NAND Flash on IFC */
220 #define CONFIG_NAND_FSL_IFC
221 #define CONFIG_SYS_NAND_BASE		0xff800000
222 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
223 
224 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
225 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
226 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
227 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
228 				| CSPR_V)
229 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
230 
231 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
232 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
233 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
234 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
235 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
236 				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
237 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
238 
239 #define CONFIG_SYS_NAND_ONFI_DETECTION
240 
241 /* ONFI NAND Flash mode0 Timing Params */
242 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
243 					FTIM0_NAND_TWP(0x18)   | \
244 					FTIM0_NAND_TWCHT(0x07) | \
245 					FTIM0_NAND_TWH(0x0a))
246 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
247 					FTIM1_NAND_TWBE(0x39)  | \
248 					FTIM1_NAND_TRR(0x0e)   | \
249 					FTIM1_NAND_TRP(0x18))
250 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
251 					FTIM2_NAND_TREH(0x0a) | \
252 					FTIM2_NAND_TWHRE(0x1e))
253 #define CONFIG_SYS_NAND_FTIM3		0x0
254 
255 #define CONFIG_SYS_NAND_DDR_LAW		11
256 
257 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
258 #define CONFIG_SYS_MAX_NAND_DEVICE	1
259 
260 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
261 #define CONFIG_SYS_NAND_MAX_OOBFREE	2
262 #define CONFIG_SYS_NAND_MAX_ECCPOS	256
263 
264 #if defined(CONFIG_NAND)
265 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
266 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
267 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
268 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
269 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
270 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
271 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
272 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
273 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
274 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
275 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
276 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
277 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
278 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
279 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
280 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
281 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
282 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
283 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
284 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
285 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
286 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
287 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
288 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
289 #else
290 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
291 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
292 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
293 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
294 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
295 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
296 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
297 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
298 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
299 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
300 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
301 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
302 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
303 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
304 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
305 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
306 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
307 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
308 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
309 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
310 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
311 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
312 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
313 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
314 #endif
315 
316 #if defined(CONFIG_RAMBOOT_PBL)
317 #define CONFIG_SYS_RAMBOOT
318 #endif
319 
320 /* I2C */
321 #define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
322 #define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
323 #define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
324 #define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */
325 
326 #define I2C_MUX_CH_DEFAULT	0x8
327 #define I2C_MUX_CH_VOL_MONITOR	0xa
328 #define I2C_MUX_CH_VSC3316_FS	0xc
329 #define I2C_MUX_CH_VSC3316_BS	0xd
330 
331 /* Voltage monitor on channel 2*/
332 #define I2C_VOL_MONITOR_ADDR		0x40
333 #define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
334 #define I2C_VOL_MONITOR_BUS_V_OVF	0x1
335 #define I2C_VOL_MONITOR_BUS_V_SHIFT	3
336 
337 /* VSC Crossbar switches */
338 #define CONFIG_VSC_CROSSBAR
339 #define VSC3316_FSM_TX_ADDR	0x70
340 #define VSC3316_FSM_RX_ADDR	0x71
341 
342 /*
343  * RapidIO
344  */
345 
346 /*
347  * for slave u-boot IMAGE instored in master memory space,
348  * PHYS must be aligned based on the SIZE
349  */
350 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
351 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
352 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000	/* 1M */
353 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
354 /*
355  * for slave UCODE and ENV instored in master memory space,
356  * PHYS must be aligned based on the SIZE
357  */
358 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
359 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
360 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
361 
362 /* slave core release by master*/
363 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
364 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
365 
366 /*
367  * SRIO_PCIE_BOOT - SLAVE
368  */
369 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
370 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
371 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
372 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
373 #endif
374 /*
375  * eSPI - Enhanced SPI
376  */
377 #define CONFIG_SF_DEFAULT_SPEED         10000000
378 #define CONFIG_SF_DEFAULT_MODE          0
379 
380 /* Qman/Bman */
381 #ifndef CONFIG_NOBQFMAN
382 #define CONFIG_SYS_BMAN_NUM_PORTALS	50
383 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
384 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
385 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
386 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
387 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
388 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
389 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
390 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
391 					CONFIG_SYS_BMAN_CENA_SIZE)
392 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
393 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
394 #define CONFIG_SYS_QMAN_NUM_PORTALS	50
395 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
396 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
397 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
398 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
399 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
400 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
401 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
402 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
403 					CONFIG_SYS_QMAN_CENA_SIZE)
404 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
405 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
406 
407 #define CONFIG_SYS_DPAA_FMAN
408 #define CONFIG_SYS_DPAA_PME
409 #define CONFIG_SYS_PMAN
410 #define CONFIG_SYS_DPAA_DCE
411 #define CONFIG_SYS_DPAA_RMAN
412 #define CONFIG_SYS_INTERLAKEN
413 
414 /* Default address of microcode for the Linux Fman driver */
415 #if defined(CONFIG_SPIFLASH)
416 /*
417  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
418  * env, so we got 0x110000.
419  */
420 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
421 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
422 #elif defined(CONFIG_SDCARD)
423 /*
424  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
425  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
426  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
427  */
428 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
429 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
430 #elif defined(CONFIG_NAND)
431 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
432 #define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
433 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
434 /*
435  * Slave has no ucode locally, it can fetch this from remote. When implementing
436  * in two corenet boards, slave's ucode could be stored in master's memory
437  * space, the address can be mapped from slave TLB->slave LAW->
438  * slave SRIO or PCIE outbound window->master inbound window->
439  * master LAW->the ucode address in master's memory space.
440  */
441 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
442 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
443 #else
444 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
445 #define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
446 #endif
447 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
448 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
449 #endif /* CONFIG_NOBQFMAN */
450 
451 #ifdef CONFIG_SYS_DPAA_FMAN
452 #define CONFIG_FMAN_ENET
453 #define CONFIG_PHYLIB_10G
454 #define CONFIG_PHY_VITESSE
455 #define CONFIG_PHY_TERANETICS
456 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
457 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
458 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
459 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
460 #define FM1_10GEC1_PHY_ADDR	0x0
461 #define FM1_10GEC2_PHY_ADDR	0x1
462 #define FM2_10GEC1_PHY_ADDR	0x2
463 #define FM2_10GEC2_PHY_ADDR	0x3
464 #endif
465 
466 /* SATA */
467 #ifdef CONFIG_FSL_SATA_V2
468 #define CONFIG_SYS_SATA_MAX_DEVICE	2
469 #define CONFIG_SATA1
470 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
471 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
472 #define CONFIG_SATA2
473 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
474 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
475 
476 #define CONFIG_LBA48
477 #endif
478 
479 #ifdef CONFIG_FMAN_ENET
480 #define CONFIG_MII		/* MII PHY management */
481 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
482 #endif
483 
484 /*
485 * USB
486 */
487 #define CONFIG_USB_EHCI_FSL
488 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
489 #define CONFIG_HAS_FSL_DR_USB
490 
491 #ifdef CONFIG_MMC
492 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
493 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
494 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
495 #define CONFIG_ESDHC_DETECT_QUIRK \
496 	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
497 	IS_SVR_REV(get_svr(), 1, 0))
498 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
499 	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
500 #endif
501 
502 
503 #define __USB_PHY_TYPE	utmi
504 
505 /*
506  * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
507  * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
508  * interleaving. It can be cacheline, page, bank, superbank.
509  * See doc/README.fsl-ddr for details.
510  */
511 #ifdef CONFIG_ARCH_T4240
512 #define CTRL_INTLV_PREFERED 3way_4KB
513 #else
514 #define CTRL_INTLV_PREFERED cacheline
515 #endif
516 
517 #define	CONFIG_EXTRA_ENV_SETTINGS				\
518 	"hwconfig=fsl_ddr:"					\
519 	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
520 	"bank_intlv=auto;"					\
521 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
522 	"netdev=eth0\0"						\
523 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
524 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
525 	"tftpflash=tftpboot $loadaddr $uboot && "		\
526 	"protect off $ubootaddr +$filesize && "			\
527 	"erase $ubootaddr +$filesize && "			\
528 	"cp.b $loadaddr $ubootaddr $filesize && "		\
529 	"protect on $ubootaddr +$filesize && "			\
530 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
531 	"consoledev=ttyS0\0"					\
532 	"ramdiskaddr=2000000\0"					\
533 	"ramdiskfile=t4240qds/ramdisk.uboot\0"			\
534 	"fdtaddr=1e00000\0"					\
535 	"fdtfile=t4240qds/t4240qds.dtb\0"				\
536 	"bdev=sda3\0"
537 
538 #define CONFIG_HVBOOT				\
539 	"setenv bootargs config-addr=0x60000000; "	\
540 	"bootm 0x01000000 - 0x00f00000"
541 
542 #define CONFIG_ALU				\
543 	"setenv bootargs root=/dev/$bdev rw "		\
544 	"console=$consoledev,$baudrate $othbootargs;"	\
545 	"cpu 1 release 0x01000000 - - -;"		\
546 	"cpu 2 release 0x01000000 - - -;"		\
547 	"cpu 3 release 0x01000000 - - -;"		\
548 	"cpu 4 release 0x01000000 - - -;"		\
549 	"cpu 5 release 0x01000000 - - -;"		\
550 	"cpu 6 release 0x01000000 - - -;"		\
551 	"cpu 7 release 0x01000000 - - -;"		\
552 	"go 0x01000000"
553 
554 #define CONFIG_LINUX				\
555 	"setenv bootargs root=/dev/ram rw "		\
556 	"console=$consoledev,$baudrate $othbootargs;"	\
557 	"setenv ramdiskaddr 0x02000000;"		\
558 	"setenv fdtaddr 0x00c00000;"			\
559 	"setenv loadaddr 0x1000000;"			\
560 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
561 
562 #define CONFIG_HDBOOT					\
563 	"setenv bootargs root=/dev/$bdev rw "		\
564 	"console=$consoledev,$baudrate $othbootargs;"	\
565 	"tftp $loadaddr $bootfile;"			\
566 	"tftp $fdtaddr $fdtfile;"			\
567 	"bootm $loadaddr - $fdtaddr"
568 
569 #define CONFIG_NFSBOOTCOMMAND			\
570 	"setenv bootargs root=/dev/nfs rw "	\
571 	"nfsroot=$serverip:$rootpath "		\
572 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
573 	"console=$consoledev,$baudrate $othbootargs;"	\
574 	"tftp $loadaddr $bootfile;"		\
575 	"tftp $fdtaddr $fdtfile;"		\
576 	"bootm $loadaddr - $fdtaddr"
577 
578 #define CONFIG_RAMBOOTCOMMAND				\
579 	"setenv bootargs root=/dev/ram rw "		\
580 	"console=$consoledev,$baudrate $othbootargs;"	\
581 	"tftp $ramdiskaddr $ramdiskfile;"		\
582 	"tftp $loadaddr $bootfile;"			\
583 	"tftp $fdtaddr $fdtfile;"			\
584 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
585 
586 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
587 
588 #include <asm/fsl_secure_boot.h>
589 
590 #endif	/* __CONFIG_H */
591