1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_T4240QDS 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 18 19 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 23 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #else 27 #define CONFIG_SPL_FLUSH_IMAGE 28 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 29 #define CONFIG_FSL_LAW /* Use common FSL init code */ 30 #define CONFIG_SYS_TEXT_BASE 0x00201000 31 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 32 #define CONFIG_SPL_PAD_TO 0x40000 33 #define CONFIG_SPL_MAX_SIZE 0x28000 34 #define RESET_VECTOR_OFFSET 0x27FFC 35 #define BOOT_PAGE_OFFSET 0x27000 36 37 #ifdef CONFIG_NAND 38 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 39 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 40 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 41 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 42 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg 44 #define CONFIG_SPL_NAND_BOOT 45 #endif 46 47 #ifdef CONFIG_SDCARD 48 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 49 #define CONFIG_SPL_MMC_MINIMAL 50 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 52 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 54 #ifndef CONFIG_SPL_BUILD 55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 56 #endif 57 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg 59 #define CONFIG_SPL_MMC_BOOT 60 #endif 61 62 #ifdef CONFIG_SPL_BUILD 63 #define CONFIG_SPL_SKIP_RELOCATE 64 #define CONFIG_SPL_COMMON_INIT_DDR 65 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 66 #define CONFIG_SYS_NO_FLASH 67 #endif 68 69 #endif 70 #endif /* CONFIG_RAMBOOT_PBL */ 71 72 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 73 /* Set 1M boot space */ 74 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 75 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 76 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 77 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 78 #define CONFIG_SYS_NO_FLASH 79 #endif 80 81 #define CONFIG_SRIO_PCIE_BOOT_MASTER 82 #define CONFIG_DDR_ECC 83 84 #include "t4qds.h" 85 86 #ifdef CONFIG_SYS_NO_FLASH 87 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 88 #define CONFIG_ENV_IS_NOWHERE 89 #endif 90 #else 91 #define CONFIG_FLASH_CFI_DRIVER 92 #define CONFIG_SYS_FLASH_CFI 93 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 94 #endif 95 96 #if defined(CONFIG_SPIFLASH) 97 #define CONFIG_SYS_EXTRA_ENV_RELOC 98 #define CONFIG_ENV_IS_IN_SPI_FLASH 99 #define CONFIG_ENV_SPI_BUS 0 100 #define CONFIG_ENV_SPI_CS 0 101 #define CONFIG_ENV_SPI_MAX_HZ 10000000 102 #define CONFIG_ENV_SPI_MODE 0 103 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 104 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 105 #define CONFIG_ENV_SECT_SIZE 0x10000 106 #elif defined(CONFIG_SDCARD) 107 #define CONFIG_SYS_EXTRA_ENV_RELOC 108 #define CONFIG_ENV_IS_IN_MMC 109 #define CONFIG_SYS_MMC_ENV_DEV 0 110 #define CONFIG_ENV_SIZE 0x2000 111 #define CONFIG_ENV_OFFSET (512 * 0x800) 112 #elif defined(CONFIG_NAND) 113 #define CONFIG_SYS_EXTRA_ENV_RELOC 114 #define CONFIG_ENV_IS_IN_NAND 115 #define CONFIG_ENV_SIZE 0x2000 116 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 117 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 118 #define CONFIG_ENV_IS_IN_REMOTE 119 #define CONFIG_ENV_ADDR 0xffe20000 120 #define CONFIG_ENV_SIZE 0x2000 121 #elif defined(CONFIG_ENV_IS_NOWHERE) 122 #define CONFIG_ENV_SIZE 0x2000 123 #else 124 #define CONFIG_ENV_IS_IN_FLASH 125 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 126 #define CONFIG_ENV_SIZE 0x2000 127 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 128 #endif 129 130 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 131 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 132 133 #ifndef __ASSEMBLY__ 134 unsigned long get_board_sys_clk(void); 135 unsigned long get_board_ddr_clk(void); 136 #endif 137 138 /* EEPROM */ 139 #define CONFIG_ID_EEPROM 140 #define CONFIG_SYS_I2C_EEPROM_NXID 141 #define CONFIG_SYS_EEPROM_BUS_NUM 0 142 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 143 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 144 145 /* 146 * DDR Setup 147 */ 148 #define CONFIG_SYS_SPD_BUS_NUM 0 149 #define SPD_EEPROM_ADDRESS1 0x51 150 #define SPD_EEPROM_ADDRESS2 0x52 151 #define SPD_EEPROM_ADDRESS3 0x53 152 #define SPD_EEPROM_ADDRESS4 0x54 153 #define SPD_EEPROM_ADDRESS5 0x55 154 #define SPD_EEPROM_ADDRESS6 0x56 155 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 156 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 157 158 /* 159 * IFC Definitions 160 */ 161 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 162 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 163 + 0x8000000) | \ 164 CSPR_PORT_SIZE_16 | \ 165 CSPR_MSEL_NOR | \ 166 CSPR_V) 167 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 168 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 169 CSPR_PORT_SIZE_16 | \ 170 CSPR_MSEL_NOR | \ 171 CSPR_V) 172 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 173 /* NOR Flash Timing Params */ 174 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 175 176 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 177 FTIM0_NOR_TEADC(0x5) | \ 178 FTIM0_NOR_TEAHC(0x5)) 179 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 180 FTIM1_NOR_TRAD_NOR(0x1A) |\ 181 FTIM1_NOR_TSEQRAD_NOR(0x13)) 182 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 183 FTIM2_NOR_TCH(0x4) | \ 184 FTIM2_NOR_TWPH(0x0E) | \ 185 FTIM2_NOR_TWP(0x1c)) 186 #define CONFIG_SYS_NOR_FTIM3 0x0 187 188 #define CONFIG_SYS_FLASH_QUIET_TEST 189 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 190 191 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 192 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 193 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 194 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 195 196 #define CONFIG_SYS_FLASH_EMPTY_INFO 197 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 198 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 199 200 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 201 #define QIXIS_BASE 0xffdf0000 202 #define QIXIS_LBMAP_SWITCH 6 203 #define QIXIS_LBMAP_MASK 0x0f 204 #define QIXIS_LBMAP_SHIFT 0 205 #define QIXIS_LBMAP_DFLTBANK 0x00 206 #define QIXIS_LBMAP_ALTBANK 0x04 207 #define QIXIS_RST_CTL_RESET 0x83 208 #define QIXIS_RST_FORCE_MEM 0x1 209 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 210 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 211 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 212 #define QIXIS_BRDCFG5 0x55 213 #define QIXIS_MUX_SDHC 2 214 #define QIXIS_MUX_SDHC_WIDTH8 1 215 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 216 217 #define CONFIG_SYS_CSPR3_EXT (0xf) 218 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 219 | CSPR_PORT_SIZE_8 \ 220 | CSPR_MSEL_GPCM \ 221 | CSPR_V) 222 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 223 #define CONFIG_SYS_CSOR3 0x0 224 /* QIXIS Timing parameters for IFC CS3 */ 225 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 226 FTIM0_GPCM_TEADC(0x0e) | \ 227 FTIM0_GPCM_TEAHC(0x0e)) 228 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 229 FTIM1_GPCM_TRAD(0x3f)) 230 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 231 FTIM2_GPCM_TCH(0x8) | \ 232 FTIM2_GPCM_TWP(0x1f)) 233 #define CONFIG_SYS_CS3_FTIM3 0x0 234 235 /* NAND Flash on IFC */ 236 #define CONFIG_NAND_FSL_IFC 237 #define CONFIG_SYS_NAND_BASE 0xff800000 238 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 239 240 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 241 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 242 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 243 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 244 | CSPR_V) 245 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 246 247 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 248 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 249 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 250 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 251 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 252 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 253 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 254 255 #define CONFIG_SYS_NAND_ONFI_DETECTION 256 257 /* ONFI NAND Flash mode0 Timing Params */ 258 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 259 FTIM0_NAND_TWP(0x18) | \ 260 FTIM0_NAND_TWCHT(0x07) | \ 261 FTIM0_NAND_TWH(0x0a)) 262 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 263 FTIM1_NAND_TWBE(0x39) | \ 264 FTIM1_NAND_TRR(0x0e) | \ 265 FTIM1_NAND_TRP(0x18)) 266 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 267 FTIM2_NAND_TREH(0x0a) | \ 268 FTIM2_NAND_TWHRE(0x1e)) 269 #define CONFIG_SYS_NAND_FTIM3 0x0 270 271 #define CONFIG_SYS_NAND_DDR_LAW 11 272 273 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 274 #define CONFIG_SYS_MAX_NAND_DEVICE 1 275 #define CONFIG_CMD_NAND 276 277 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 278 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 279 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 280 281 #if defined(CONFIG_NAND) 282 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 283 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 284 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 285 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 286 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 287 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 288 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 289 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 290 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 291 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 292 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 293 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 294 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 295 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 296 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 297 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 298 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 299 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 300 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 301 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 302 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 303 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 304 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 305 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 306 #else 307 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 308 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 309 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 310 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 311 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 312 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 313 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 314 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 315 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 316 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 317 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 318 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 319 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 320 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 321 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 322 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 323 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 324 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 325 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 326 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 327 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 328 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 329 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 330 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 331 #endif 332 333 #if defined(CONFIG_RAMBOOT_PBL) 334 #define CONFIG_SYS_RAMBOOT 335 #endif 336 337 /* I2C */ 338 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 339 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 340 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 341 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 342 343 #define I2C_MUX_CH_DEFAULT 0x8 344 #define I2C_MUX_CH_VOL_MONITOR 0xa 345 #define I2C_MUX_CH_VSC3316_FS 0xc 346 #define I2C_MUX_CH_VSC3316_BS 0xd 347 348 /* Voltage monitor on channel 2*/ 349 #define I2C_VOL_MONITOR_ADDR 0x40 350 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 351 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 352 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 353 354 /* VSC Crossbar switches */ 355 #define CONFIG_VSC_CROSSBAR 356 #define VSC3316_FSM_TX_ADDR 0x70 357 #define VSC3316_FSM_RX_ADDR 0x71 358 359 /* 360 * RapidIO 361 */ 362 363 /* 364 * for slave u-boot IMAGE instored in master memory space, 365 * PHYS must be aligned based on the SIZE 366 */ 367 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 368 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 369 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 370 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 371 /* 372 * for slave UCODE and ENV instored in master memory space, 373 * PHYS must be aligned based on the SIZE 374 */ 375 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 376 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 377 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 378 379 /* slave core release by master*/ 380 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 381 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 382 383 /* 384 * SRIO_PCIE_BOOT - SLAVE 385 */ 386 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 387 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 388 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 389 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 390 #endif 391 /* 392 * eSPI - Enhanced SPI 393 */ 394 #define CONFIG_SF_DEFAULT_SPEED 10000000 395 #define CONFIG_SF_DEFAULT_MODE 0 396 397 /* Qman/Bman */ 398 #ifndef CONFIG_NOBQFMAN 399 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 400 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 401 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 402 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 403 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 404 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 405 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 406 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 407 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 408 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 409 CONFIG_SYS_BMAN_CENA_SIZE) 410 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 411 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 412 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 413 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 414 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 415 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 416 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 417 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 418 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 419 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 420 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 421 CONFIG_SYS_QMAN_CENA_SIZE) 422 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 423 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 424 425 #define CONFIG_SYS_DPAA_FMAN 426 #define CONFIG_SYS_DPAA_PME 427 #define CONFIG_SYS_PMAN 428 #define CONFIG_SYS_DPAA_DCE 429 #define CONFIG_SYS_DPAA_RMAN 430 #define CONFIG_SYS_INTERLAKEN 431 432 /* Default address of microcode for the Linux Fman driver */ 433 #if defined(CONFIG_SPIFLASH) 434 /* 435 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 436 * env, so we got 0x110000. 437 */ 438 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 439 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 440 #elif defined(CONFIG_SDCARD) 441 /* 442 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 443 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 444 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 445 */ 446 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 447 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 448 #elif defined(CONFIG_NAND) 449 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 450 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 451 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 452 /* 453 * Slave has no ucode locally, it can fetch this from remote. When implementing 454 * in two corenet boards, slave's ucode could be stored in master's memory 455 * space, the address can be mapped from slave TLB->slave LAW-> 456 * slave SRIO or PCIE outbound window->master inbound window-> 457 * master LAW->the ucode address in master's memory space. 458 */ 459 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 460 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 461 #else 462 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 463 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 464 #endif 465 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 466 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 467 #endif /* CONFIG_NOBQFMAN */ 468 469 #ifdef CONFIG_SYS_DPAA_FMAN 470 #define CONFIG_FMAN_ENET 471 #define CONFIG_PHYLIB_10G 472 #define CONFIG_PHY_VITESSE 473 #define CONFIG_PHY_TERANETICS 474 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 475 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 476 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 477 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 478 #define FM1_10GEC1_PHY_ADDR 0x0 479 #define FM1_10GEC2_PHY_ADDR 0x1 480 #define FM2_10GEC1_PHY_ADDR 0x2 481 #define FM2_10GEC2_PHY_ADDR 0x3 482 #endif 483 484 /* SATA */ 485 #ifdef CONFIG_FSL_SATA_V2 486 #define CONFIG_LIBATA 487 #define CONFIG_FSL_SATA 488 489 #define CONFIG_SYS_SATA_MAX_DEVICE 2 490 #define CONFIG_SATA1 491 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 492 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 493 #define CONFIG_SATA2 494 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 495 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 496 497 #define CONFIG_LBA48 498 #define CONFIG_CMD_SATA 499 #define CONFIG_DOS_PARTITION 500 #endif 501 502 #ifdef CONFIG_FMAN_ENET 503 #define CONFIG_MII /* MII PHY management */ 504 #define CONFIG_ETHPRIME "FM1@DTSEC1" 505 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 506 #endif 507 508 /* Hash command with SHA acceleration supported in hardware */ 509 #ifdef CONFIG_FSL_CAAM 510 #define CONFIG_CMD_HASH 511 #define CONFIG_SHA_HW_ACCEL 512 #endif 513 514 /* 515 * USB 516 */ 517 #define CONFIG_USB_EHCI 518 #define CONFIG_USB_EHCI_FSL 519 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 520 #define CONFIG_HAS_FSL_DR_USB 521 522 #define CONFIG_MMC 523 524 #ifdef CONFIG_MMC 525 #define CONFIG_FSL_ESDHC 526 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 527 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 528 #define CONFIG_GENERIC_MMC 529 #define CONFIG_DOS_PARTITION 530 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 531 #define CONFIG_ESDHC_DETECT_QUIRK \ 532 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 533 IS_SVR_REV(get_svr(), 1, 0)) 534 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 535 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 536 #endif 537 538 539 #define __USB_PHY_TYPE utmi 540 541 /* 542 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 543 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 544 * interleaving. It can be cacheline, page, bank, superbank. 545 * See doc/README.fsl-ddr for details. 546 */ 547 #ifdef CONFIG_PPC_T4240 548 #define CTRL_INTLV_PREFERED 3way_4KB 549 #else 550 #define CTRL_INTLV_PREFERED cacheline 551 #endif 552 553 #define CONFIG_EXTRA_ENV_SETTINGS \ 554 "hwconfig=fsl_ddr:" \ 555 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 556 "bank_intlv=auto;" \ 557 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 558 "netdev=eth0\0" \ 559 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 560 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 561 "tftpflash=tftpboot $loadaddr $uboot && " \ 562 "protect off $ubootaddr +$filesize && " \ 563 "erase $ubootaddr +$filesize && " \ 564 "cp.b $loadaddr $ubootaddr $filesize && " \ 565 "protect on $ubootaddr +$filesize && " \ 566 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 567 "consoledev=ttyS0\0" \ 568 "ramdiskaddr=2000000\0" \ 569 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 570 "fdtaddr=1e00000\0" \ 571 "fdtfile=t4240qds/t4240qds.dtb\0" \ 572 "bdev=sda3\0" 573 574 #define CONFIG_HVBOOT \ 575 "setenv bootargs config-addr=0x60000000; " \ 576 "bootm 0x01000000 - 0x00f00000" 577 578 #define CONFIG_ALU \ 579 "setenv bootargs root=/dev/$bdev rw " \ 580 "console=$consoledev,$baudrate $othbootargs;" \ 581 "cpu 1 release 0x01000000 - - -;" \ 582 "cpu 2 release 0x01000000 - - -;" \ 583 "cpu 3 release 0x01000000 - - -;" \ 584 "cpu 4 release 0x01000000 - - -;" \ 585 "cpu 5 release 0x01000000 - - -;" \ 586 "cpu 6 release 0x01000000 - - -;" \ 587 "cpu 7 release 0x01000000 - - -;" \ 588 "go 0x01000000" 589 590 #define CONFIG_LINUX \ 591 "setenv bootargs root=/dev/ram rw " \ 592 "console=$consoledev,$baudrate $othbootargs;" \ 593 "setenv ramdiskaddr 0x02000000;" \ 594 "setenv fdtaddr 0x00c00000;" \ 595 "setenv loadaddr 0x1000000;" \ 596 "bootm $loadaddr $ramdiskaddr $fdtaddr" 597 598 #define CONFIG_HDBOOT \ 599 "setenv bootargs root=/dev/$bdev rw " \ 600 "console=$consoledev,$baudrate $othbootargs;" \ 601 "tftp $loadaddr $bootfile;" \ 602 "tftp $fdtaddr $fdtfile;" \ 603 "bootm $loadaddr - $fdtaddr" 604 605 #define CONFIG_NFSBOOTCOMMAND \ 606 "setenv bootargs root=/dev/nfs rw " \ 607 "nfsroot=$serverip:$rootpath " \ 608 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 609 "console=$consoledev,$baudrate $othbootargs;" \ 610 "tftp $loadaddr $bootfile;" \ 611 "tftp $fdtaddr $fdtfile;" \ 612 "bootm $loadaddr - $fdtaddr" 613 614 #define CONFIG_RAMBOOTCOMMAND \ 615 "setenv bootargs root=/dev/ram rw " \ 616 "console=$consoledev,$baudrate $othbootargs;" \ 617 "tftp $ramdiskaddr $ramdiskfile;" \ 618 "tftp $loadaddr $bootfile;" \ 619 "tftp $fdtaddr $fdtfile;" \ 620 "bootm $loadaddr $ramdiskaddr $fdtaddr" 621 622 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 623 624 #include <asm/fsl_secure_boot.h> 625 626 #endif /* __CONFIG_H */ 627