1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 16 17 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 21 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 22 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 23 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 24 #else 25 #define CONFIG_SPL_FLUSH_IMAGE 26 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 27 #define CONFIG_SYS_TEXT_BASE 0x00201000 28 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 29 #define CONFIG_SPL_PAD_TO 0x40000 30 #define CONFIG_SPL_MAX_SIZE 0x28000 31 #define RESET_VECTOR_OFFSET 0x27FFC 32 #define BOOT_PAGE_OFFSET 0x27000 33 34 #ifdef CONFIG_NAND 35 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 36 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 37 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 38 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 39 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 40 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg 41 #define CONFIG_SPL_NAND_BOOT 42 #endif 43 44 #ifdef CONFIG_SDCARD 45 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 46 #define CONFIG_SPL_MMC_MINIMAL 47 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 48 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 49 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 50 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 51 #ifndef CONFIG_SPL_BUILD 52 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 53 #endif 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg 56 #define CONFIG_SPL_MMC_BOOT 57 #endif 58 59 #ifdef CONFIG_SPL_BUILD 60 #define CONFIG_SPL_SKIP_RELOCATE 61 #define CONFIG_SPL_COMMON_INIT_DDR 62 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 63 #define CONFIG_SYS_NO_FLASH 64 #endif 65 66 #endif 67 #endif /* CONFIG_RAMBOOT_PBL */ 68 69 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 70 /* Set 1M boot space */ 71 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 72 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 73 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 74 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 75 #define CONFIG_SYS_NO_FLASH 76 #endif 77 78 #define CONFIG_SRIO_PCIE_BOOT_MASTER 79 #define CONFIG_DDR_ECC 80 81 #include "t4qds.h" 82 83 #ifdef CONFIG_SYS_NO_FLASH 84 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 85 #define CONFIG_ENV_IS_NOWHERE 86 #endif 87 #else 88 #define CONFIG_FLASH_CFI_DRIVER 89 #define CONFIG_SYS_FLASH_CFI 90 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 91 #endif 92 93 #if defined(CONFIG_SPIFLASH) 94 #define CONFIG_SYS_EXTRA_ENV_RELOC 95 #define CONFIG_ENV_IS_IN_SPI_FLASH 96 #define CONFIG_ENV_SPI_BUS 0 97 #define CONFIG_ENV_SPI_CS 0 98 #define CONFIG_ENV_SPI_MAX_HZ 10000000 99 #define CONFIG_ENV_SPI_MODE 0 100 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 101 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 102 #define CONFIG_ENV_SECT_SIZE 0x10000 103 #elif defined(CONFIG_SDCARD) 104 #define CONFIG_SYS_EXTRA_ENV_RELOC 105 #define CONFIG_ENV_IS_IN_MMC 106 #define CONFIG_SYS_MMC_ENV_DEV 0 107 #define CONFIG_ENV_SIZE 0x2000 108 #define CONFIG_ENV_OFFSET (512 * 0x800) 109 #elif defined(CONFIG_NAND) 110 #define CONFIG_SYS_EXTRA_ENV_RELOC 111 #define CONFIG_ENV_IS_IN_NAND 112 #define CONFIG_ENV_SIZE 0x2000 113 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 114 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 115 #define CONFIG_ENV_IS_IN_REMOTE 116 #define CONFIG_ENV_ADDR 0xffe20000 117 #define CONFIG_ENV_SIZE 0x2000 118 #elif defined(CONFIG_ENV_IS_NOWHERE) 119 #define CONFIG_ENV_SIZE 0x2000 120 #else 121 #define CONFIG_ENV_IS_IN_FLASH 122 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 123 #define CONFIG_ENV_SIZE 0x2000 124 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 125 #endif 126 127 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 128 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 129 130 #ifndef __ASSEMBLY__ 131 unsigned long get_board_sys_clk(void); 132 unsigned long get_board_ddr_clk(void); 133 #endif 134 135 /* EEPROM */ 136 #define CONFIG_ID_EEPROM 137 #define CONFIG_SYS_I2C_EEPROM_NXID 138 #define CONFIG_SYS_EEPROM_BUS_NUM 0 139 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 140 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 141 142 /* 143 * DDR Setup 144 */ 145 #define CONFIG_SYS_SPD_BUS_NUM 0 146 #define SPD_EEPROM_ADDRESS1 0x51 147 #define SPD_EEPROM_ADDRESS2 0x52 148 #define SPD_EEPROM_ADDRESS3 0x53 149 #define SPD_EEPROM_ADDRESS4 0x54 150 #define SPD_EEPROM_ADDRESS5 0x55 151 #define SPD_EEPROM_ADDRESS6 0x56 152 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 153 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 154 155 /* 156 * IFC Definitions 157 */ 158 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 159 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 160 + 0x8000000) | \ 161 CSPR_PORT_SIZE_16 | \ 162 CSPR_MSEL_NOR | \ 163 CSPR_V) 164 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 165 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 166 CSPR_PORT_SIZE_16 | \ 167 CSPR_MSEL_NOR | \ 168 CSPR_V) 169 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 170 /* NOR Flash Timing Params */ 171 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 172 173 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 174 FTIM0_NOR_TEADC(0x5) | \ 175 FTIM0_NOR_TEAHC(0x5)) 176 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 177 FTIM1_NOR_TRAD_NOR(0x1A) |\ 178 FTIM1_NOR_TSEQRAD_NOR(0x13)) 179 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 180 FTIM2_NOR_TCH(0x4) | \ 181 FTIM2_NOR_TWPH(0x0E) | \ 182 FTIM2_NOR_TWP(0x1c)) 183 #define CONFIG_SYS_NOR_FTIM3 0x0 184 185 #define CONFIG_SYS_FLASH_QUIET_TEST 186 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 187 188 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 189 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 190 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 191 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 192 193 #define CONFIG_SYS_FLASH_EMPTY_INFO 194 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 195 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 196 197 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 198 #define QIXIS_BASE 0xffdf0000 199 #define QIXIS_LBMAP_SWITCH 6 200 #define QIXIS_LBMAP_MASK 0x0f 201 #define QIXIS_LBMAP_SHIFT 0 202 #define QIXIS_LBMAP_DFLTBANK 0x00 203 #define QIXIS_LBMAP_ALTBANK 0x04 204 #define QIXIS_RST_CTL_RESET 0x83 205 #define QIXIS_RST_FORCE_MEM 0x1 206 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 207 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 208 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 209 #define QIXIS_BRDCFG5 0x55 210 #define QIXIS_MUX_SDHC 2 211 #define QIXIS_MUX_SDHC_WIDTH8 1 212 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 213 214 #define CONFIG_SYS_CSPR3_EXT (0xf) 215 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 216 | CSPR_PORT_SIZE_8 \ 217 | CSPR_MSEL_GPCM \ 218 | CSPR_V) 219 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 220 #define CONFIG_SYS_CSOR3 0x0 221 /* QIXIS Timing parameters for IFC CS3 */ 222 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 223 FTIM0_GPCM_TEADC(0x0e) | \ 224 FTIM0_GPCM_TEAHC(0x0e)) 225 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 226 FTIM1_GPCM_TRAD(0x3f)) 227 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 228 FTIM2_GPCM_TCH(0x8) | \ 229 FTIM2_GPCM_TWP(0x1f)) 230 #define CONFIG_SYS_CS3_FTIM3 0x0 231 232 /* NAND Flash on IFC */ 233 #define CONFIG_NAND_FSL_IFC 234 #define CONFIG_SYS_NAND_BASE 0xff800000 235 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 236 237 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 238 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 239 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 240 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 241 | CSPR_V) 242 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 243 244 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 245 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 246 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 247 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 248 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 249 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 250 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 251 252 #define CONFIG_SYS_NAND_ONFI_DETECTION 253 254 /* ONFI NAND Flash mode0 Timing Params */ 255 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 256 FTIM0_NAND_TWP(0x18) | \ 257 FTIM0_NAND_TWCHT(0x07) | \ 258 FTIM0_NAND_TWH(0x0a)) 259 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 260 FTIM1_NAND_TWBE(0x39) | \ 261 FTIM1_NAND_TRR(0x0e) | \ 262 FTIM1_NAND_TRP(0x18)) 263 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 264 FTIM2_NAND_TREH(0x0a) | \ 265 FTIM2_NAND_TWHRE(0x1e)) 266 #define CONFIG_SYS_NAND_FTIM3 0x0 267 268 #define CONFIG_SYS_NAND_DDR_LAW 11 269 270 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 271 #define CONFIG_SYS_MAX_NAND_DEVICE 1 272 #define CONFIG_CMD_NAND 273 274 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 275 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 276 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 277 278 #if defined(CONFIG_NAND) 279 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 280 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 281 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 282 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 283 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 284 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 285 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 286 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 287 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 288 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 289 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 290 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 291 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 292 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 293 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 294 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 295 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 296 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 297 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 298 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 299 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 300 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 301 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 302 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 303 #else 304 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 305 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 306 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 307 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 308 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 309 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 310 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 311 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 312 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 313 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 314 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 315 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 316 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 317 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 318 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 319 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 320 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 321 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 322 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 323 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 324 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 325 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 326 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 327 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 328 #endif 329 330 #if defined(CONFIG_RAMBOOT_PBL) 331 #define CONFIG_SYS_RAMBOOT 332 #endif 333 334 /* I2C */ 335 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 336 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 337 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 338 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 339 340 #define I2C_MUX_CH_DEFAULT 0x8 341 #define I2C_MUX_CH_VOL_MONITOR 0xa 342 #define I2C_MUX_CH_VSC3316_FS 0xc 343 #define I2C_MUX_CH_VSC3316_BS 0xd 344 345 /* Voltage monitor on channel 2*/ 346 #define I2C_VOL_MONITOR_ADDR 0x40 347 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 348 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 349 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 350 351 /* VSC Crossbar switches */ 352 #define CONFIG_VSC_CROSSBAR 353 #define VSC3316_FSM_TX_ADDR 0x70 354 #define VSC3316_FSM_RX_ADDR 0x71 355 356 /* 357 * RapidIO 358 */ 359 360 /* 361 * for slave u-boot IMAGE instored in master memory space, 362 * PHYS must be aligned based on the SIZE 363 */ 364 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 365 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 366 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 367 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 368 /* 369 * for slave UCODE and ENV instored in master memory space, 370 * PHYS must be aligned based on the SIZE 371 */ 372 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 373 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 374 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 375 376 /* slave core release by master*/ 377 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 378 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 379 380 /* 381 * SRIO_PCIE_BOOT - SLAVE 382 */ 383 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 384 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 385 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 386 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 387 #endif 388 /* 389 * eSPI - Enhanced SPI 390 */ 391 #define CONFIG_SF_DEFAULT_SPEED 10000000 392 #define CONFIG_SF_DEFAULT_MODE 0 393 394 /* Qman/Bman */ 395 #ifndef CONFIG_NOBQFMAN 396 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 397 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 398 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 399 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 400 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 401 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 402 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 403 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 404 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 405 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 406 CONFIG_SYS_BMAN_CENA_SIZE) 407 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 408 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 409 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 410 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 411 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 412 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 413 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 414 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 415 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 416 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 417 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 418 CONFIG_SYS_QMAN_CENA_SIZE) 419 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 420 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 421 422 #define CONFIG_SYS_DPAA_FMAN 423 #define CONFIG_SYS_DPAA_PME 424 #define CONFIG_SYS_PMAN 425 #define CONFIG_SYS_DPAA_DCE 426 #define CONFIG_SYS_DPAA_RMAN 427 #define CONFIG_SYS_INTERLAKEN 428 429 /* Default address of microcode for the Linux Fman driver */ 430 #if defined(CONFIG_SPIFLASH) 431 /* 432 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 433 * env, so we got 0x110000. 434 */ 435 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 436 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 437 #elif defined(CONFIG_SDCARD) 438 /* 439 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 440 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 441 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 442 */ 443 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 444 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 445 #elif defined(CONFIG_NAND) 446 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 447 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 448 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 449 /* 450 * Slave has no ucode locally, it can fetch this from remote. When implementing 451 * in two corenet boards, slave's ucode could be stored in master's memory 452 * space, the address can be mapped from slave TLB->slave LAW-> 453 * slave SRIO or PCIE outbound window->master inbound window-> 454 * master LAW->the ucode address in master's memory space. 455 */ 456 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 457 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 458 #else 459 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 460 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 461 #endif 462 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 463 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 464 #endif /* CONFIG_NOBQFMAN */ 465 466 #ifdef CONFIG_SYS_DPAA_FMAN 467 #define CONFIG_FMAN_ENET 468 #define CONFIG_PHYLIB_10G 469 #define CONFIG_PHY_VITESSE 470 #define CONFIG_PHY_TERANETICS 471 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 472 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 473 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 474 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 475 #define FM1_10GEC1_PHY_ADDR 0x0 476 #define FM1_10GEC2_PHY_ADDR 0x1 477 #define FM2_10GEC1_PHY_ADDR 0x2 478 #define FM2_10GEC2_PHY_ADDR 0x3 479 #endif 480 481 /* SATA */ 482 #ifdef CONFIG_FSL_SATA_V2 483 #define CONFIG_LIBATA 484 #define CONFIG_FSL_SATA 485 486 #define CONFIG_SYS_SATA_MAX_DEVICE 2 487 #define CONFIG_SATA1 488 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 489 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 490 #define CONFIG_SATA2 491 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 492 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 493 494 #define CONFIG_LBA48 495 #define CONFIG_CMD_SATA 496 #define CONFIG_DOS_PARTITION 497 #endif 498 499 #ifdef CONFIG_FMAN_ENET 500 #define CONFIG_MII /* MII PHY management */ 501 #define CONFIG_ETHPRIME "FM1@DTSEC1" 502 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 503 #endif 504 505 /* Hash command with SHA acceleration supported in hardware */ 506 #ifdef CONFIG_FSL_CAAM 507 #define CONFIG_CMD_HASH 508 #define CONFIG_SHA_HW_ACCEL 509 #endif 510 511 /* 512 * USB 513 */ 514 #define CONFIG_USB_EHCI 515 #define CONFIG_USB_EHCI_FSL 516 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 517 #define CONFIG_HAS_FSL_DR_USB 518 519 #ifdef CONFIG_MMC 520 #define CONFIG_FSL_ESDHC 521 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 522 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 523 #define CONFIG_GENERIC_MMC 524 #define CONFIG_DOS_PARTITION 525 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 526 #define CONFIG_ESDHC_DETECT_QUIRK \ 527 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 528 IS_SVR_REV(get_svr(), 1, 0)) 529 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 530 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 531 #endif 532 533 534 #define __USB_PHY_TYPE utmi 535 536 /* 537 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 538 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 539 * interleaving. It can be cacheline, page, bank, superbank. 540 * See doc/README.fsl-ddr for details. 541 */ 542 #ifdef CONFIG_ARCH_T4240 543 #define CTRL_INTLV_PREFERED 3way_4KB 544 #else 545 #define CTRL_INTLV_PREFERED cacheline 546 #endif 547 548 #define CONFIG_EXTRA_ENV_SETTINGS \ 549 "hwconfig=fsl_ddr:" \ 550 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 551 "bank_intlv=auto;" \ 552 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 553 "netdev=eth0\0" \ 554 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 555 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 556 "tftpflash=tftpboot $loadaddr $uboot && " \ 557 "protect off $ubootaddr +$filesize && " \ 558 "erase $ubootaddr +$filesize && " \ 559 "cp.b $loadaddr $ubootaddr $filesize && " \ 560 "protect on $ubootaddr +$filesize && " \ 561 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 562 "consoledev=ttyS0\0" \ 563 "ramdiskaddr=2000000\0" \ 564 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 565 "fdtaddr=1e00000\0" \ 566 "fdtfile=t4240qds/t4240qds.dtb\0" \ 567 "bdev=sda3\0" 568 569 #define CONFIG_HVBOOT \ 570 "setenv bootargs config-addr=0x60000000; " \ 571 "bootm 0x01000000 - 0x00f00000" 572 573 #define CONFIG_ALU \ 574 "setenv bootargs root=/dev/$bdev rw " \ 575 "console=$consoledev,$baudrate $othbootargs;" \ 576 "cpu 1 release 0x01000000 - - -;" \ 577 "cpu 2 release 0x01000000 - - -;" \ 578 "cpu 3 release 0x01000000 - - -;" \ 579 "cpu 4 release 0x01000000 - - -;" \ 580 "cpu 5 release 0x01000000 - - -;" \ 581 "cpu 6 release 0x01000000 - - -;" \ 582 "cpu 7 release 0x01000000 - - -;" \ 583 "go 0x01000000" 584 585 #define CONFIG_LINUX \ 586 "setenv bootargs root=/dev/ram rw " \ 587 "console=$consoledev,$baudrate $othbootargs;" \ 588 "setenv ramdiskaddr 0x02000000;" \ 589 "setenv fdtaddr 0x00c00000;" \ 590 "setenv loadaddr 0x1000000;" \ 591 "bootm $loadaddr $ramdiskaddr $fdtaddr" 592 593 #define CONFIG_HDBOOT \ 594 "setenv bootargs root=/dev/$bdev rw " \ 595 "console=$consoledev,$baudrate $othbootargs;" \ 596 "tftp $loadaddr $bootfile;" \ 597 "tftp $fdtaddr $fdtfile;" \ 598 "bootm $loadaddr - $fdtaddr" 599 600 #define CONFIG_NFSBOOTCOMMAND \ 601 "setenv bootargs root=/dev/nfs rw " \ 602 "nfsroot=$serverip:$rootpath " \ 603 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 604 "console=$consoledev,$baudrate $othbootargs;" \ 605 "tftp $loadaddr $bootfile;" \ 606 "tftp $fdtaddr $fdtfile;" \ 607 "bootm $loadaddr - $fdtaddr" 608 609 #define CONFIG_RAMBOOTCOMMAND \ 610 "setenv bootargs root=/dev/ram rw " \ 611 "console=$consoledev,$baudrate $othbootargs;" \ 612 "tftp $ramdiskaddr $ramdiskfile;" \ 613 "tftp $loadaddr $bootfile;" \ 614 "tftp $fdtaddr $fdtfile;" \ 615 "bootm $loadaddr $ramdiskaddr $fdtaddr" 616 617 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 618 619 #include <asm/fsl_secure_boot.h> 620 621 #endif /* __CONFIG_H */ 622