1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T2080 RDB/PCIe board configuration file 8 */ 9 10 #ifndef __T2080RDB_H 11 #define __T2080RDB_H 12 13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 14 #define CONFIG_FSL_SATA_V2 15 16 /* High Level Configuration Options */ 17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 18 #define CONFIG_ENABLE_36BIT_PHYS 19 20 #ifdef CONFIG_PHYS_64BIT 21 #define CONFIG_ADDR_MAP 1 22 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 23 #endif 24 25 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 26 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 27 #define CONFIG_ENV_OVERWRITE 28 29 #ifdef CONFIG_RAMBOOT_PBL 30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 31 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 34 #define CONFIG_SPL_PAD_TO 0x40000 35 #define CONFIG_SPL_MAX_SIZE 0x28000 36 #define RESET_VECTOR_OFFSET 0x27FFC 37 #define BOOT_PAGE_OFFSET 0x27000 38 #ifdef CONFIG_SPL_BUILD 39 #define CONFIG_SPL_SKIP_RELOCATE 40 #define CONFIG_SPL_COMMON_INIT_DDR 41 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 42 #endif 43 44 #ifdef CONFIG_NAND 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 46 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 47 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 48 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 51 #define CONFIG_SPL_NAND_BOOT 52 #endif 53 54 #ifdef CONFIG_SPIFLASH 55 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 56 #define CONFIG_SPL_SPI_FLASH_MINIMAL 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 62 #ifndef CONFIG_SPL_BUILD 63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 64 #endif 65 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 66 #define CONFIG_SPL_SPI_BOOT 67 #endif 68 69 #ifdef CONFIG_SDCARD 70 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 71 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 72 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 73 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 74 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 76 #ifndef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 78 #endif 79 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 80 #define CONFIG_SPL_MMC_BOOT 81 #endif 82 83 #endif /* CONFIG_RAMBOOT_PBL */ 84 85 #define CONFIG_SRIO_PCIE_BOOT_MASTER 86 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 87 /* Set 1M boot space */ 88 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 90 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 91 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 92 #endif 93 94 #ifndef CONFIG_RESET_VECTOR_ADDRESS 95 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 96 #endif 97 98 /* 99 * These can be toggled for performance analysis, otherwise use default. 100 */ 101 #define CONFIG_SYS_CACHE_STASHING 102 #define CONFIG_BTB /* toggle branch predition */ 103 #define CONFIG_DDR_ECC 104 #ifdef CONFIG_DDR_ECC 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 106 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 107 #endif 108 109 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 110 #define CONFIG_SYS_MEMTEST_END 0x00400000 111 112 #ifdef CONFIG_MTD_NOR_FLASH 113 #define CONFIG_FLASH_CFI_DRIVER 114 #define CONFIG_SYS_FLASH_CFI 115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 116 #endif 117 118 #if defined(CONFIG_SPIFLASH) 119 #define CONFIG_ENV_SPI_BUS 0 120 #define CONFIG_ENV_SPI_CS 0 121 #define CONFIG_ENV_SPI_MAX_HZ 10000000 122 #define CONFIG_ENV_SPI_MODE 0 123 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 124 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 125 #define CONFIG_ENV_SECT_SIZE 0x10000 126 #elif defined(CONFIG_SDCARD) 127 #define CONFIG_SYS_MMC_ENV_DEV 0 128 #define CONFIG_ENV_SIZE 0x2000 129 #define CONFIG_ENV_OFFSET (512 * 0x800) 130 #elif defined(CONFIG_NAND) 131 #define CONFIG_ENV_SIZE 0x2000 132 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 133 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 134 #define CONFIG_ENV_ADDR 0xffe20000 135 #define CONFIG_ENV_SIZE 0x2000 136 #elif defined(CONFIG_ENV_IS_NOWHERE) 137 #define CONFIG_ENV_SIZE 0x2000 138 #else 139 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 140 #define CONFIG_ENV_SIZE 0x2000 141 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 142 #endif 143 144 #ifndef __ASSEMBLY__ 145 unsigned long get_board_sys_clk(void); 146 unsigned long get_board_ddr_clk(void); 147 #endif 148 149 #define CONFIG_SYS_CLK_FREQ 66660000 150 #define CONFIG_DDR_CLK_FREQ 133330000 151 152 /* 153 * Config the L3 Cache as L3 SRAM 154 */ 155 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 156 #define CONFIG_SYS_L3_SIZE (512 << 10) 157 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 158 #ifdef CONFIG_RAMBOOT_PBL 159 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 160 #endif 161 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 162 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 163 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 164 165 #define CONFIG_SYS_DCSRBAR 0xf0000000 166 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 167 168 /* EEPROM */ 169 #define CONFIG_ID_EEPROM 170 #define CONFIG_SYS_I2C_EEPROM_NXID 171 #define CONFIG_SYS_EEPROM_BUS_NUM 0 172 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 173 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 174 175 /* 176 * DDR Setup 177 */ 178 #define CONFIG_VERY_BIG_RAM 179 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 180 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 181 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 182 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 183 #define CONFIG_DDR_SPD 184 #undef CONFIG_FSL_DDR_INTERACTIVE 185 #define CONFIG_SYS_SPD_BUS_NUM 0 186 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 187 #define SPD_EEPROM_ADDRESS1 0x51 188 #define SPD_EEPROM_ADDRESS2 0x52 189 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 190 #define CTRL_INTLV_PREFERED cacheline 191 192 /* 193 * IFC Definitions 194 */ 195 #define CONFIG_SYS_FLASH_BASE 0xe8000000 196 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 197 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 198 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 199 CSPR_PORT_SIZE_16 | \ 200 CSPR_MSEL_NOR | \ 201 CSPR_V) 202 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 203 204 /* NOR Flash Timing Params */ 205 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 206 207 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 208 FTIM0_NOR_TEADC(0x5) | \ 209 FTIM0_NOR_TEAHC(0x5)) 210 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 211 FTIM1_NOR_TRAD_NOR(0x1A) |\ 212 FTIM1_NOR_TSEQRAD_NOR(0x13)) 213 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 214 FTIM2_NOR_TCH(0x4) | \ 215 FTIM2_NOR_TWPH(0x0E) | \ 216 FTIM2_NOR_TWP(0x1c)) 217 #define CONFIG_SYS_NOR_FTIM3 0x0 218 219 #define CONFIG_SYS_FLASH_QUIET_TEST 220 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 221 222 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 223 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 224 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 225 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 226 #define CONFIG_SYS_FLASH_EMPTY_INFO 227 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 228 229 /* CPLD on IFC */ 230 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 231 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 232 #define CONFIG_SYS_CSPR2_EXT (0xf) 233 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 234 | CSPR_PORT_SIZE_8 \ 235 | CSPR_MSEL_GPCM \ 236 | CSPR_V) 237 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 238 #define CONFIG_SYS_CSOR2 0x0 239 240 /* CPLD Timing parameters for IFC CS2 */ 241 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 242 FTIM0_GPCM_TEADC(0x0e) | \ 243 FTIM0_GPCM_TEAHC(0x0e)) 244 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 245 FTIM1_GPCM_TRAD(0x1f)) 246 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 247 FTIM2_GPCM_TCH(0x8) | \ 248 FTIM2_GPCM_TWP(0x1f)) 249 #define CONFIG_SYS_CS2_FTIM3 0x0 250 251 /* NAND Flash on IFC */ 252 #define CONFIG_NAND_FSL_IFC 253 #define CONFIG_SYS_NAND_BASE 0xff800000 254 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 255 256 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 257 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 258 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 259 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 260 | CSPR_V) 261 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 262 263 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 264 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 265 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 266 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 267 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 268 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 269 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 270 271 #define CONFIG_SYS_NAND_ONFI_DETECTION 272 273 /* ONFI NAND Flash mode0 Timing Params */ 274 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 275 FTIM0_NAND_TWP(0x18) | \ 276 FTIM0_NAND_TWCHT(0x07) | \ 277 FTIM0_NAND_TWH(0x0a)) 278 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 279 FTIM1_NAND_TWBE(0x39) | \ 280 FTIM1_NAND_TRR(0x0e) | \ 281 FTIM1_NAND_TRP(0x18)) 282 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 283 FTIM2_NAND_TREH(0x0a) | \ 284 FTIM2_NAND_TWHRE(0x1e)) 285 #define CONFIG_SYS_NAND_FTIM3 0x0 286 287 #define CONFIG_SYS_NAND_DDR_LAW 11 288 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 289 #define CONFIG_SYS_MAX_NAND_DEVICE 1 290 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 291 292 #if defined(CONFIG_NAND) 293 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 294 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 295 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 296 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 297 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 298 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 299 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 300 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 301 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 302 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 303 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 304 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 305 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 306 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 307 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 308 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 309 #else 310 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 311 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 312 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 313 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 314 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 315 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 316 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 317 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 318 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 319 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 320 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 321 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 322 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 323 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 324 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 325 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 326 #endif 327 328 #if defined(CONFIG_RAMBOOT_PBL) 329 #define CONFIG_SYS_RAMBOOT 330 #endif 331 332 #ifdef CONFIG_SPL_BUILD 333 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 334 #else 335 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 336 #endif 337 338 #define CONFIG_HWCONFIG 339 340 /* define to use L1 as initial stack */ 341 #define CONFIG_L1_INIT_RAM 342 #define CONFIG_SYS_INIT_RAM_LOCK 343 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 344 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 345 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 346 /* The assembler doesn't like typecast */ 347 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 348 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 349 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 350 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 351 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 352 GENERATED_GBL_DATA_SIZE) 353 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 354 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 355 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 356 357 /* 358 * Serial Port 359 */ 360 #define CONFIG_SYS_NS16550_SERIAL 361 #define CONFIG_SYS_NS16550_REG_SIZE 1 362 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 363 #define CONFIG_SYS_BAUDRATE_TABLE \ 364 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 365 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 366 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 367 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 368 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 369 370 /* 371 * I2C 372 */ 373 #define CONFIG_SYS_I2C 374 #define CONFIG_SYS_I2C_FSL 375 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 376 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 377 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 378 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 379 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 380 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 381 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 382 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 383 #define CONFIG_SYS_FSL_I2C_SPEED 100000 384 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 385 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 386 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 387 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 388 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 389 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 390 #define I2C_MUX_CH_DEFAULT 0x8 391 392 #define I2C_MUX_CH_VOL_MONITOR 0xa 393 394 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 395 #ifndef CONFIG_SPL_BUILD 396 #define CONFIG_VID 397 #endif 398 #define CONFIG_VOL_MONITOR_IR36021_SET 399 #define CONFIG_VOL_MONITOR_IR36021_READ 400 /* The lowest and highest voltage allowed for T208xRDB */ 401 #define VDD_MV_MIN 819 402 #define VDD_MV_MAX 1212 403 404 /* 405 * RapidIO 406 */ 407 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 408 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 409 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 410 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 411 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 412 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 413 /* 414 * for slave u-boot IMAGE instored in master memory space, 415 * PHYS must be aligned based on the SIZE 416 */ 417 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 418 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 419 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 420 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 421 /* 422 * for slave UCODE and ENV instored in master memory space, 423 * PHYS must be aligned based on the SIZE 424 */ 425 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 426 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 427 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 428 429 /* slave core release by master*/ 430 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 431 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 432 433 /* 434 * SRIO_PCIE_BOOT - SLAVE 435 */ 436 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 437 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 438 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 439 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 440 #endif 441 442 /* 443 * eSPI - Enhanced SPI 444 */ 445 #ifdef CONFIG_SPI_FLASH 446 #define CONFIG_SPI_FLASH_BAR 447 #define CONFIG_SF_DEFAULT_SPEED 10000000 448 #define CONFIG_SF_DEFAULT_MODE 0 449 #endif 450 451 /* 452 * General PCI 453 * Memory space is mapped 1-1, but I/O space must start from 0. 454 */ 455 #define CONFIG_PCIE1 /* PCIE controller 1 */ 456 #define CONFIG_PCIE2 /* PCIE controller 2 */ 457 #define CONFIG_PCIE3 /* PCIE controller 3 */ 458 #define CONFIG_PCIE4 /* PCIE controller 4 */ 459 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 460 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 461 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 462 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 463 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 464 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 465 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 466 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 467 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 468 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 469 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 470 471 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 472 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 473 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 474 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 475 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 476 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 477 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 478 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 479 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 480 481 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 482 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 483 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 484 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 485 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 486 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 487 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 488 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 489 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 490 491 /* controller 4, Base address 203000 */ 492 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 493 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 494 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 495 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 496 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 497 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 498 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 499 500 #ifdef CONFIG_PCI 501 #define CONFIG_PCI_INDIRECT_BRIDGE 502 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 503 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 504 #endif 505 506 /* Qman/Bman */ 507 #ifndef CONFIG_NOBQFMAN 508 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 509 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 510 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 511 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 512 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 513 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 514 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 515 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 516 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 517 CONFIG_SYS_BMAN_CENA_SIZE) 518 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 519 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 520 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 521 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 522 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 523 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 524 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 525 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 526 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 527 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 528 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 529 CONFIG_SYS_QMAN_CENA_SIZE) 530 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 531 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 532 533 #define CONFIG_SYS_DPAA_FMAN 534 #define CONFIG_SYS_DPAA_PME 535 #define CONFIG_SYS_PMAN 536 #define CONFIG_SYS_DPAA_DCE 537 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 538 #define CONFIG_SYS_INTERLAKEN 539 540 /* Default address of microcode for the Linux Fman driver */ 541 #if defined(CONFIG_SPIFLASH) 542 /* 543 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 544 * env, so we got 0x110000. 545 */ 546 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 547 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 548 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 549 #define CONFIG_CORTINA_FW_ADDR 0x120000 550 551 #elif defined(CONFIG_SDCARD) 552 /* 553 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 554 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 555 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 556 */ 557 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 558 #define CONFIG_SYS_CORTINA_FW_IN_MMC 559 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 560 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 561 562 #elif defined(CONFIG_NAND) 563 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 564 #define CONFIG_SYS_CORTINA_FW_IN_NAND 565 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 566 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 567 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 568 /* 569 * Slave has no ucode locally, it can fetch this from remote. When implementing 570 * in two corenet boards, slave's ucode could be stored in master's memory 571 * space, the address can be mapped from slave TLB->slave LAW-> 572 * slave SRIO or PCIE outbound window->master inbound window-> 573 * master LAW->the ucode address in master's memory space. 574 */ 575 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 576 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 577 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 578 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 579 #else 580 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 581 #define CONFIG_SYS_CORTINA_FW_IN_NOR 582 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 583 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 584 #endif 585 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 586 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 587 #endif /* CONFIG_NOBQFMAN */ 588 589 #ifdef CONFIG_SYS_DPAA_FMAN 590 #define CONFIG_FMAN_ENET 591 #define CONFIG_PHYLIB_10G 592 #define CONFIG_PHY_AQUANTIA 593 #define CONFIG_PHY_CORTINA 594 #define CONFIG_PHY_REALTEK 595 #define CONFIG_CORTINA_FW_LENGTH 0x40000 596 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 597 #define RGMII_PHY2_ADDR 0x02 598 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 599 #define CORTINA_PHY_ADDR2 0x0d 600 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 601 #define FM1_10GEC4_PHY_ADDR 0x01 602 #endif 603 604 #ifdef CONFIG_FMAN_ENET 605 #define CONFIG_ETHPRIME "FM1@DTSEC3" 606 #endif 607 608 /* 609 * SATA 610 */ 611 #ifdef CONFIG_FSL_SATA_V2 612 #define CONFIG_SYS_SATA_MAX_DEVICE 2 613 #define CONFIG_SATA1 614 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 615 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 616 #define CONFIG_SATA2 617 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 618 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 619 #define CONFIG_LBA48 620 #endif 621 622 /* 623 * USB 624 */ 625 #ifdef CONFIG_USB_EHCI_HCD 626 #define CONFIG_USB_EHCI_FSL 627 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 628 #define CONFIG_HAS_FSL_DR_USB 629 #endif 630 631 /* 632 * SDHC 633 */ 634 #ifdef CONFIG_MMC 635 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 636 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 637 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 638 #endif 639 640 /* 641 * Dynamic MTD Partition support with mtdparts 642 */ 643 #ifdef CONFIG_MTD_NOR_FLASH 644 #define CONFIG_FLASH_CFI_MTD 645 #endif 646 647 /* 648 * Environment 649 */ 650 651 /* 652 * Miscellaneous configurable options 653 */ 654 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 655 656 /* 657 * For booting Linux, the board info and command line data 658 * have to be in the first 64 MB of memory, since this is 659 * the maximum mapped by the Linux kernel during initialization. 660 */ 661 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 662 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 663 664 #ifdef CONFIG_CMD_KGDB 665 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 666 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 667 #endif 668 669 /* 670 * Environment Configuration 671 */ 672 #define CONFIG_ROOTPATH "/opt/nfsroot" 673 #define CONFIG_BOOTFILE "uImage" 674 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 675 676 /* default location for tftp and bootm */ 677 #define CONFIG_LOADADDR 1000000 678 #define __USB_PHY_TYPE utmi 679 680 #define CONFIG_EXTRA_ENV_SETTINGS \ 681 "hwconfig=fsl_ddr:" \ 682 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 683 "bank_intlv=auto;" \ 684 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 685 "netdev=eth0\0" \ 686 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 687 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 688 "tftpflash=tftpboot $loadaddr $uboot && " \ 689 "protect off $ubootaddr +$filesize && " \ 690 "erase $ubootaddr +$filesize && " \ 691 "cp.b $loadaddr $ubootaddr $filesize && " \ 692 "protect on $ubootaddr +$filesize && " \ 693 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 694 "consoledev=ttyS0\0" \ 695 "ramdiskaddr=2000000\0" \ 696 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 697 "fdtaddr=1e00000\0" \ 698 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 699 "bdev=sda3\0" 700 701 /* 702 * For emulation this causes u-boot to jump to the start of the 703 * proof point app code automatically 704 */ 705 #define CONFIG_PROOF_POINTS \ 706 "setenv bootargs root=/dev/$bdev rw " \ 707 "console=$consoledev,$baudrate $othbootargs;" \ 708 "cpu 1 release 0x29000000 - - -;" \ 709 "cpu 2 release 0x29000000 - - -;" \ 710 "cpu 3 release 0x29000000 - - -;" \ 711 "cpu 4 release 0x29000000 - - -;" \ 712 "cpu 5 release 0x29000000 - - -;" \ 713 "cpu 6 release 0x29000000 - - -;" \ 714 "cpu 7 release 0x29000000 - - -;" \ 715 "go 0x29000000" 716 717 #define CONFIG_HVBOOT \ 718 "setenv bootargs config-addr=0x60000000; " \ 719 "bootm 0x01000000 - 0x00f00000" 720 721 #define CONFIG_ALU \ 722 "setenv bootargs root=/dev/$bdev rw " \ 723 "console=$consoledev,$baudrate $othbootargs;" \ 724 "cpu 1 release 0x01000000 - - -;" \ 725 "cpu 2 release 0x01000000 - - -;" \ 726 "cpu 3 release 0x01000000 - - -;" \ 727 "cpu 4 release 0x01000000 - - -;" \ 728 "cpu 5 release 0x01000000 - - -;" \ 729 "cpu 6 release 0x01000000 - - -;" \ 730 "cpu 7 release 0x01000000 - - -;" \ 731 "go 0x01000000" 732 733 #define CONFIG_LINUX \ 734 "setenv bootargs root=/dev/ram rw " \ 735 "console=$consoledev,$baudrate $othbootargs;" \ 736 "setenv ramdiskaddr 0x02000000;" \ 737 "setenv fdtaddr 0x00c00000;" \ 738 "setenv loadaddr 0x1000000;" \ 739 "bootm $loadaddr $ramdiskaddr $fdtaddr" 740 741 #define CONFIG_HDBOOT \ 742 "setenv bootargs root=/dev/$bdev rw " \ 743 "console=$consoledev,$baudrate $othbootargs;" \ 744 "tftp $loadaddr $bootfile;" \ 745 "tftp $fdtaddr $fdtfile;" \ 746 "bootm $loadaddr - $fdtaddr" 747 748 #define CONFIG_NFSBOOTCOMMAND \ 749 "setenv bootargs root=/dev/nfs rw " \ 750 "nfsroot=$serverip:$rootpath " \ 751 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 752 "console=$consoledev,$baudrate $othbootargs;" \ 753 "tftp $loadaddr $bootfile;" \ 754 "tftp $fdtaddr $fdtfile;" \ 755 "bootm $loadaddr - $fdtaddr" 756 757 #define CONFIG_RAMBOOTCOMMAND \ 758 "setenv bootargs root=/dev/ram rw " \ 759 "console=$consoledev,$baudrate $othbootargs;" \ 760 "tftp $ramdiskaddr $ramdiskfile;" \ 761 "tftp $loadaddr $bootfile;" \ 762 "tftp $fdtaddr $fdtfile;" \ 763 "bootm $loadaddr $ramdiskaddr $fdtaddr" 764 765 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 766 767 #include <asm/fsl_secure_boot.h> 768 769 #endif /* __T2080RDB_H */ 770