1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_USB_EHCI 16 #define CONFIG_FSL_SATA_V2 17 18 /* High Level Configuration Options */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 30 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 31 #define CONFIG_ENV_OVERWRITE 32 33 #ifdef CONFIG_RAMBOOT_PBL 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 35 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SYS_TEXT_BASE 0x00201000 39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 40 #define CONFIG_SPL_PAD_TO 0x40000 41 #define CONFIG_SPL_MAX_SIZE 0x28000 42 #define RESET_VECTOR_OFFSET 0x27FFC 43 #define BOOT_PAGE_OFFSET 0x27000 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #endif 49 50 #ifdef CONFIG_NAND 51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 54 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 57 #define CONFIG_SPL_NAND_BOOT 58 #endif 59 60 #ifdef CONFIG_SPIFLASH 61 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 62 #define CONFIG_SPL_SPI_FLASH_MINIMAL 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 68 #ifndef CONFIG_SPL_BUILD 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #endif 71 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 72 #define CONFIG_SPL_SPI_BOOT 73 #endif 74 75 #ifdef CONFIG_SDCARD 76 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 77 #define CONFIG_SPL_MMC_MINIMAL 78 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 79 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 80 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 81 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 83 #ifndef CONFIG_SPL_BUILD 84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 85 #endif 86 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 87 #define CONFIG_SPL_MMC_BOOT 88 #endif 89 90 #endif /* CONFIG_RAMBOOT_PBL */ 91 92 #define CONFIG_SRIO_PCIE_BOOT_MASTER 93 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 94 /* Set 1M boot space */ 95 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 96 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 97 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 98 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 99 #endif 100 101 #ifndef CONFIG_SYS_TEXT_BASE 102 #define CONFIG_SYS_TEXT_BASE 0xeff40000 103 #endif 104 105 #ifndef CONFIG_RESET_VECTOR_ADDRESS 106 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 107 #endif 108 109 /* 110 * These can be toggled for performance analysis, otherwise use default. 111 */ 112 #define CONFIG_SYS_CACHE_STASHING 113 #define CONFIG_BTB /* toggle branch predition */ 114 #define CONFIG_DDR_ECC 115 #ifdef CONFIG_DDR_ECC 116 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 117 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 118 #endif 119 120 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 121 #define CONFIG_SYS_MEMTEST_END 0x00400000 122 #define CONFIG_SYS_ALT_MEMTEST 123 124 #ifdef CONFIG_MTD_NOR_FLASH 125 #define CONFIG_FLASH_CFI_DRIVER 126 #define CONFIG_SYS_FLASH_CFI 127 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 128 #endif 129 130 #if defined(CONFIG_SPIFLASH) 131 #define CONFIG_SYS_EXTRA_ENV_RELOC 132 #define CONFIG_ENV_IS_IN_SPI_FLASH 133 #define CONFIG_ENV_SPI_BUS 0 134 #define CONFIG_ENV_SPI_CS 0 135 #define CONFIG_ENV_SPI_MAX_HZ 10000000 136 #define CONFIG_ENV_SPI_MODE 0 137 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 138 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 139 #define CONFIG_ENV_SECT_SIZE 0x10000 140 #elif defined(CONFIG_SDCARD) 141 #define CONFIG_SYS_EXTRA_ENV_RELOC 142 #define CONFIG_ENV_IS_IN_MMC 143 #define CONFIG_SYS_MMC_ENV_DEV 0 144 #define CONFIG_ENV_SIZE 0x2000 145 #define CONFIG_ENV_OFFSET (512 * 0x800) 146 #elif defined(CONFIG_NAND) 147 #define CONFIG_SYS_EXTRA_ENV_RELOC 148 #define CONFIG_ENV_IS_IN_NAND 149 #define CONFIG_ENV_SIZE 0x2000 150 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 151 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 152 #define CONFIG_ENV_IS_IN_REMOTE 153 #define CONFIG_ENV_ADDR 0xffe20000 154 #define CONFIG_ENV_SIZE 0x2000 155 #elif defined(CONFIG_ENV_IS_NOWHERE) 156 #define CONFIG_ENV_SIZE 0x2000 157 #else 158 #define CONFIG_ENV_IS_IN_FLASH 159 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 160 #define CONFIG_ENV_SIZE 0x2000 161 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 162 #endif 163 164 #ifndef __ASSEMBLY__ 165 unsigned long get_board_sys_clk(void); 166 unsigned long get_board_ddr_clk(void); 167 #endif 168 169 #define CONFIG_SYS_CLK_FREQ 66660000 170 #define CONFIG_DDR_CLK_FREQ 133330000 171 172 /* 173 * Config the L3 Cache as L3 SRAM 174 */ 175 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 176 #define CONFIG_SYS_L3_SIZE (512 << 10) 177 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 178 #ifdef CONFIG_RAMBOOT_PBL 179 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 180 #endif 181 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 182 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 183 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 184 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 185 186 #define CONFIG_SYS_DCSRBAR 0xf0000000 187 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 188 189 /* EEPROM */ 190 #define CONFIG_ID_EEPROM 191 #define CONFIG_SYS_I2C_EEPROM_NXID 192 #define CONFIG_SYS_EEPROM_BUS_NUM 0 193 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 194 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 195 196 /* 197 * DDR Setup 198 */ 199 #define CONFIG_VERY_BIG_RAM 200 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 201 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 202 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 203 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 204 #define CONFIG_DDR_SPD 205 #undef CONFIG_FSL_DDR_INTERACTIVE 206 #define CONFIG_SYS_SPD_BUS_NUM 0 207 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 208 #define SPD_EEPROM_ADDRESS1 0x51 209 #define SPD_EEPROM_ADDRESS2 0x52 210 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 211 #define CTRL_INTLV_PREFERED cacheline 212 213 /* 214 * IFC Definitions 215 */ 216 #define CONFIG_SYS_FLASH_BASE 0xe8000000 217 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 218 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 219 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 220 CSPR_PORT_SIZE_16 | \ 221 CSPR_MSEL_NOR | \ 222 CSPR_V) 223 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 224 225 /* NOR Flash Timing Params */ 226 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 227 228 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 229 FTIM0_NOR_TEADC(0x5) | \ 230 FTIM0_NOR_TEAHC(0x5)) 231 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 232 FTIM1_NOR_TRAD_NOR(0x1A) |\ 233 FTIM1_NOR_TSEQRAD_NOR(0x13)) 234 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 235 FTIM2_NOR_TCH(0x4) | \ 236 FTIM2_NOR_TWPH(0x0E) | \ 237 FTIM2_NOR_TWP(0x1c)) 238 #define CONFIG_SYS_NOR_FTIM3 0x0 239 240 #define CONFIG_SYS_FLASH_QUIET_TEST 241 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 242 243 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 244 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 245 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 247 #define CONFIG_SYS_FLASH_EMPTY_INFO 248 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 249 250 /* CPLD on IFC */ 251 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 252 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 253 #define CONFIG_SYS_CSPR2_EXT (0xf) 254 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 255 | CSPR_PORT_SIZE_8 \ 256 | CSPR_MSEL_GPCM \ 257 | CSPR_V) 258 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 259 #define CONFIG_SYS_CSOR2 0x0 260 261 /* CPLD Timing parameters for IFC CS2 */ 262 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 263 FTIM0_GPCM_TEADC(0x0e) | \ 264 FTIM0_GPCM_TEAHC(0x0e)) 265 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 266 FTIM1_GPCM_TRAD(0x1f)) 267 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 268 FTIM2_GPCM_TCH(0x8) | \ 269 FTIM2_GPCM_TWP(0x1f)) 270 #define CONFIG_SYS_CS2_FTIM3 0x0 271 272 /* NAND Flash on IFC */ 273 #define CONFIG_NAND_FSL_IFC 274 #define CONFIG_SYS_NAND_BASE 0xff800000 275 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 276 277 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 278 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 279 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 280 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 281 | CSPR_V) 282 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 283 284 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 285 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 286 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 287 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 288 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 289 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 290 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 291 292 #define CONFIG_SYS_NAND_ONFI_DETECTION 293 294 /* ONFI NAND Flash mode0 Timing Params */ 295 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 296 FTIM0_NAND_TWP(0x18) | \ 297 FTIM0_NAND_TWCHT(0x07) | \ 298 FTIM0_NAND_TWH(0x0a)) 299 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 300 FTIM1_NAND_TWBE(0x39) | \ 301 FTIM1_NAND_TRR(0x0e) | \ 302 FTIM1_NAND_TRP(0x18)) 303 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 304 FTIM2_NAND_TREH(0x0a) | \ 305 FTIM2_NAND_TWHRE(0x1e)) 306 #define CONFIG_SYS_NAND_FTIM3 0x0 307 308 #define CONFIG_SYS_NAND_DDR_LAW 11 309 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 310 #define CONFIG_SYS_MAX_NAND_DEVICE 1 311 #define CONFIG_CMD_NAND 312 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 313 314 #if defined(CONFIG_NAND) 315 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 316 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 317 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 318 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 319 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 320 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 321 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 322 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 323 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 324 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 325 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 326 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 327 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 328 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 329 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 330 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 331 #else 332 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 333 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 334 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 335 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 336 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 337 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 338 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 339 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 340 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 341 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 342 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 343 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 344 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 345 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 346 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 347 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 348 #endif 349 350 #if defined(CONFIG_RAMBOOT_PBL) 351 #define CONFIG_SYS_RAMBOOT 352 #endif 353 354 #ifdef CONFIG_SPL_BUILD 355 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 356 #else 357 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 358 #endif 359 360 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 361 #define CONFIG_MISC_INIT_R 362 #define CONFIG_HWCONFIG 363 364 /* define to use L1 as initial stack */ 365 #define CONFIG_L1_INIT_RAM 366 #define CONFIG_SYS_INIT_RAM_LOCK 367 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 369 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 370 /* The assembler doesn't like typecast */ 371 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 372 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 373 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 374 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 375 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 376 GENERATED_GBL_DATA_SIZE) 377 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 378 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 379 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 380 381 /* 382 * Serial Port 383 */ 384 #define CONFIG_CONS_INDEX 1 385 #define CONFIG_SYS_NS16550_SERIAL 386 #define CONFIG_SYS_NS16550_REG_SIZE 1 387 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 388 #define CONFIG_SYS_BAUDRATE_TABLE \ 389 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 390 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 391 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 392 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 393 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 394 395 /* 396 * I2C 397 */ 398 #define CONFIG_SYS_I2C 399 #define CONFIG_SYS_I2C_FSL 400 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 401 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 402 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 403 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 404 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 405 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 406 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 407 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 408 #define CONFIG_SYS_FSL_I2C_SPEED 100000 409 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 410 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 411 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 412 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 413 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 414 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 415 #define I2C_MUX_CH_DEFAULT 0x8 416 417 #define I2C_MUX_CH_VOL_MONITOR 0xa 418 419 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 420 #ifndef CONFIG_SPL_BUILD 421 #define CONFIG_VID 422 #endif 423 #define CONFIG_VOL_MONITOR_IR36021_SET 424 #define CONFIG_VOL_MONITOR_IR36021_READ 425 /* The lowest and highest voltage allowed for T208xRDB */ 426 #define VDD_MV_MIN 819 427 #define VDD_MV_MAX 1212 428 429 /* 430 * RapidIO 431 */ 432 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 433 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 434 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 435 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 436 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 437 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 438 /* 439 * for slave u-boot IMAGE instored in master memory space, 440 * PHYS must be aligned based on the SIZE 441 */ 442 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 443 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 444 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 445 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 446 /* 447 * for slave UCODE and ENV instored in master memory space, 448 * PHYS must be aligned based on the SIZE 449 */ 450 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 451 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 452 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 453 454 /* slave core release by master*/ 455 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 456 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 457 458 /* 459 * SRIO_PCIE_BOOT - SLAVE 460 */ 461 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 462 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 463 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 464 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 465 #endif 466 467 /* 468 * eSPI - Enhanced SPI 469 */ 470 #ifdef CONFIG_SPI_FLASH 471 #define CONFIG_SPI_FLASH_BAR 472 #define CONFIG_SF_DEFAULT_SPEED 10000000 473 #define CONFIG_SF_DEFAULT_MODE 0 474 #endif 475 476 /* 477 * General PCI 478 * Memory space is mapped 1-1, but I/O space must start from 0. 479 */ 480 #define CONFIG_PCIE1 /* PCIE controller 1 */ 481 #define CONFIG_PCIE2 /* PCIE controller 2 */ 482 #define CONFIG_PCIE3 /* PCIE controller 3 */ 483 #define CONFIG_PCIE4 /* PCIE controller 4 */ 484 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 485 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 486 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 487 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 488 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 489 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 490 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 491 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 492 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 493 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 494 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 495 496 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 497 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 498 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 499 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 500 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 501 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 502 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 503 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 504 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 505 506 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 507 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 508 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 509 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 510 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 511 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 512 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 513 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 514 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 515 516 /* controller 4, Base address 203000 */ 517 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 518 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 519 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 520 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 521 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 522 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 523 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 524 525 #ifdef CONFIG_PCI 526 #define CONFIG_PCI_INDIRECT_BRIDGE 527 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 528 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 529 #endif 530 531 /* Qman/Bman */ 532 #ifndef CONFIG_NOBQFMAN 533 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 534 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 535 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 536 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 537 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 538 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 539 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 540 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 541 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 542 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 543 CONFIG_SYS_BMAN_CENA_SIZE) 544 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 545 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 546 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 547 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 548 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 549 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 550 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 551 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 552 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 553 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 554 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 555 CONFIG_SYS_QMAN_CENA_SIZE) 556 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 557 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 558 559 #define CONFIG_SYS_DPAA_FMAN 560 #define CONFIG_SYS_DPAA_PME 561 #define CONFIG_SYS_PMAN 562 #define CONFIG_SYS_DPAA_DCE 563 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 564 #define CONFIG_SYS_INTERLAKEN 565 566 /* Default address of microcode for the Linux Fman driver */ 567 #if defined(CONFIG_SPIFLASH) 568 /* 569 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 570 * env, so we got 0x110000. 571 */ 572 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 573 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 574 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 575 #define CONFIG_CORTINA_FW_ADDR 0x120000 576 577 #elif defined(CONFIG_SDCARD) 578 /* 579 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 580 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 581 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 582 */ 583 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 584 #define CONFIG_SYS_CORTINA_FW_IN_MMC 585 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 586 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 587 588 #elif defined(CONFIG_NAND) 589 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 590 #define CONFIG_SYS_CORTINA_FW_IN_NAND 591 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 592 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 593 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 594 /* 595 * Slave has no ucode locally, it can fetch this from remote. When implementing 596 * in two corenet boards, slave's ucode could be stored in master's memory 597 * space, the address can be mapped from slave TLB->slave LAW-> 598 * slave SRIO or PCIE outbound window->master inbound window-> 599 * master LAW->the ucode address in master's memory space. 600 */ 601 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 602 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 603 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 604 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 605 #else 606 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 607 #define CONFIG_SYS_CORTINA_FW_IN_NOR 608 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 609 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 610 #endif 611 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 612 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 613 #endif /* CONFIG_NOBQFMAN */ 614 615 #ifdef CONFIG_SYS_DPAA_FMAN 616 #define CONFIG_FMAN_ENET 617 #define CONFIG_PHYLIB_10G 618 #define CONFIG_PHY_AQUANTIA 619 #define CONFIG_PHY_CORTINA 620 #define CONFIG_PHY_REALTEK 621 #define CONFIG_CORTINA_FW_LENGTH 0x40000 622 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 623 #define RGMII_PHY2_ADDR 0x02 624 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 625 #define CORTINA_PHY_ADDR2 0x0d 626 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 627 #define FM1_10GEC4_PHY_ADDR 0x01 628 #endif 629 630 #ifdef CONFIG_FMAN_ENET 631 #define CONFIG_MII /* MII PHY management */ 632 #define CONFIG_ETHPRIME "FM1@DTSEC3" 633 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 634 #endif 635 636 /* 637 * SATA 638 */ 639 #ifdef CONFIG_FSL_SATA_V2 640 #define CONFIG_LIBATA 641 #define CONFIG_FSL_SATA 642 #define CONFIG_SYS_SATA_MAX_DEVICE 2 643 #define CONFIG_SATA1 644 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 645 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 646 #define CONFIG_SATA2 647 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 648 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 649 #define CONFIG_LBA48 650 #define CONFIG_CMD_SATA 651 #endif 652 653 /* 654 * USB 655 */ 656 #ifdef CONFIG_USB_EHCI 657 #define CONFIG_USB_EHCI_FSL 658 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 659 #define CONFIG_HAS_FSL_DR_USB 660 #endif 661 662 /* 663 * SDHC 664 */ 665 #ifdef CONFIG_MMC 666 #define CONFIG_FSL_ESDHC 667 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 668 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 669 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 670 #endif 671 672 /* 673 * Dynamic MTD Partition support with mtdparts 674 */ 675 #ifdef CONFIG_MTD_NOR_FLASH 676 #define CONFIG_MTD_DEVICE 677 #define CONFIG_MTD_PARTITIONS 678 #define CONFIG_CMD_MTDPARTS 679 #define CONFIG_FLASH_CFI_MTD 680 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 681 "spi0=spife110000.1" 682 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 683 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 684 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 685 "1m(uboot),5m(kernel),128k(dtb),-(user)" 686 #endif 687 688 /* 689 * Environment 690 */ 691 692 /* 693 * Command line configuration. 694 */ 695 #define CONFIG_CMD_ERRATA 696 #define CONFIG_CMD_REGINFO 697 698 #ifdef CONFIG_PCI 699 #define CONFIG_CMD_PCI 700 #endif 701 702 /* Hash command with SHA acceleration supported in hardware */ 703 #ifdef CONFIG_FSL_CAAM 704 #define CONFIG_CMD_HASH 705 #define CONFIG_SHA_HW_ACCEL 706 #endif 707 708 /* 709 * Miscellaneous configurable options 710 */ 711 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 712 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 713 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 714 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 715 #ifdef CONFIG_CMD_KGDB 716 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 717 #else 718 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 719 #endif 720 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 721 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 722 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 723 724 /* 725 * For booting Linux, the board info and command line data 726 * have to be in the first 64 MB of memory, since this is 727 * the maximum mapped by the Linux kernel during initialization. 728 */ 729 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 730 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 731 732 #ifdef CONFIG_CMD_KGDB 733 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 734 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 735 #endif 736 737 /* 738 * Environment Configuration 739 */ 740 #define CONFIG_ROOTPATH "/opt/nfsroot" 741 #define CONFIG_BOOTFILE "uImage" 742 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 743 744 /* default location for tftp and bootm */ 745 #define CONFIG_LOADADDR 1000000 746 #define CONFIG_BAUDRATE 115200 747 #define __USB_PHY_TYPE utmi 748 749 #define CONFIG_EXTRA_ENV_SETTINGS \ 750 "hwconfig=fsl_ddr:" \ 751 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 752 "bank_intlv=auto;" \ 753 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 754 "netdev=eth0\0" \ 755 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 756 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 757 "tftpflash=tftpboot $loadaddr $uboot && " \ 758 "protect off $ubootaddr +$filesize && " \ 759 "erase $ubootaddr +$filesize && " \ 760 "cp.b $loadaddr $ubootaddr $filesize && " \ 761 "protect on $ubootaddr +$filesize && " \ 762 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 763 "consoledev=ttyS0\0" \ 764 "ramdiskaddr=2000000\0" \ 765 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 766 "fdtaddr=1e00000\0" \ 767 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 768 "bdev=sda3\0" 769 770 /* 771 * For emulation this causes u-boot to jump to the start of the 772 * proof point app code automatically 773 */ 774 #define CONFIG_PROOF_POINTS \ 775 "setenv bootargs root=/dev/$bdev rw " \ 776 "console=$consoledev,$baudrate $othbootargs;" \ 777 "cpu 1 release 0x29000000 - - -;" \ 778 "cpu 2 release 0x29000000 - - -;" \ 779 "cpu 3 release 0x29000000 - - -;" \ 780 "cpu 4 release 0x29000000 - - -;" \ 781 "cpu 5 release 0x29000000 - - -;" \ 782 "cpu 6 release 0x29000000 - - -;" \ 783 "cpu 7 release 0x29000000 - - -;" \ 784 "go 0x29000000" 785 786 #define CONFIG_HVBOOT \ 787 "setenv bootargs config-addr=0x60000000; " \ 788 "bootm 0x01000000 - 0x00f00000" 789 790 #define CONFIG_ALU \ 791 "setenv bootargs root=/dev/$bdev rw " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "cpu 1 release 0x01000000 - - -;" \ 794 "cpu 2 release 0x01000000 - - -;" \ 795 "cpu 3 release 0x01000000 - - -;" \ 796 "cpu 4 release 0x01000000 - - -;" \ 797 "cpu 5 release 0x01000000 - - -;" \ 798 "cpu 6 release 0x01000000 - - -;" \ 799 "cpu 7 release 0x01000000 - - -;" \ 800 "go 0x01000000" 801 802 #define CONFIG_LINUX \ 803 "setenv bootargs root=/dev/ram rw " \ 804 "console=$consoledev,$baudrate $othbootargs;" \ 805 "setenv ramdiskaddr 0x02000000;" \ 806 "setenv fdtaddr 0x00c00000;" \ 807 "setenv loadaddr 0x1000000;" \ 808 "bootm $loadaddr $ramdiskaddr $fdtaddr" 809 810 #define CONFIG_HDBOOT \ 811 "setenv bootargs root=/dev/$bdev rw " \ 812 "console=$consoledev,$baudrate $othbootargs;" \ 813 "tftp $loadaddr $bootfile;" \ 814 "tftp $fdtaddr $fdtfile;" \ 815 "bootm $loadaddr - $fdtaddr" 816 817 #define CONFIG_NFSBOOTCOMMAND \ 818 "setenv bootargs root=/dev/nfs rw " \ 819 "nfsroot=$serverip:$rootpath " \ 820 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 821 "console=$consoledev,$baudrate $othbootargs;" \ 822 "tftp $loadaddr $bootfile;" \ 823 "tftp $fdtaddr $fdtfile;" \ 824 "bootm $loadaddr - $fdtaddr" 825 826 #define CONFIG_RAMBOOTCOMMAND \ 827 "setenv bootargs root=/dev/ram rw " \ 828 "console=$consoledev,$baudrate $othbootargs;" \ 829 "tftp $ramdiskaddr $ramdiskfile;" \ 830 "tftp $loadaddr $bootfile;" \ 831 "tftp $fdtaddr $fdtfile;" \ 832 "bootm $loadaddr $ramdiskaddr $fdtaddr" 833 834 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 835 836 #include <asm/fsl_secure_boot.h> 837 838 #endif /* __T2080RDB_H */ 839