1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_T2080RDB 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_MMC 18 #define CONFIG_USB_EHCI 19 #define CONFIG_FSL_SATA_V2 20 21 /* High Level Configuration Options */ 22 #define CONFIG_BOOKE 23 #define CONFIG_E500 /* BOOKE e500 family */ 24 #define CONFIG_E500MC /* BOOKE e500mc family */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 36 #define CONFIG_FSL_IFC /* Enable IFC Support */ 37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_ENV_OVERWRITE 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 44 45 #define CONFIG_SPL_FLUSH_IMAGE 46 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 47 #define CONFIG_FSL_LAW /* Use common FSL init code */ 48 #define CONFIG_SYS_TEXT_BASE 0x00201000 49 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 50 #define CONFIG_SPL_PAD_TO 0x40000 51 #define CONFIG_SPL_MAX_SIZE 0x28000 52 #define RESET_VECTOR_OFFSET 0x27FFC 53 #define BOOT_PAGE_OFFSET 0x27000 54 #ifdef CONFIG_SPL_BUILD 55 #define CONFIG_SPL_SKIP_RELOCATE 56 #define CONFIG_SPL_COMMON_INIT_DDR 57 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 58 #define CONFIG_SYS_NO_FLASH 59 #endif 60 61 #ifdef CONFIG_NAND 62 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 63 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 64 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 65 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 66 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 67 #define CONFIG_SPL_NAND_BOOT 68 #endif 69 70 #ifdef CONFIG_SPIFLASH 71 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 72 #define CONFIG_SPL_SPI_FLASH_MINIMAL 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 78 #ifndef CONFIG_SPL_BUILD 79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 80 #endif 81 #define CONFIG_SPL_SPI_BOOT 82 #endif 83 84 #ifdef CONFIG_SDCARD 85 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 86 #define CONFIG_SPL_MMC_MINIMAL 87 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 88 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 89 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 90 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 91 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 92 #ifndef CONFIG_SPL_BUILD 93 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 94 #endif 95 #define CONFIG_SPL_MMC_BOOT 96 #endif 97 98 #endif /* CONFIG_RAMBOOT_PBL */ 99 100 #define CONFIG_SRIO_PCIE_BOOT_MASTER 101 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 102 /* Set 1M boot space */ 103 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 104 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 105 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 106 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 107 #define CONFIG_SYS_NO_FLASH 108 #endif 109 110 #ifndef CONFIG_SYS_TEXT_BASE 111 #define CONFIG_SYS_TEXT_BASE 0xeff40000 112 #endif 113 114 #ifndef CONFIG_RESET_VECTOR_ADDRESS 115 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 116 #endif 117 118 /* 119 * These can be toggled for performance analysis, otherwise use default. 120 */ 121 #define CONFIG_SYS_CACHE_STASHING 122 #define CONFIG_BTB /* toggle branch predition */ 123 #define CONFIG_DDR_ECC 124 #ifdef CONFIG_DDR_ECC 125 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 126 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 127 #endif 128 129 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 130 #define CONFIG_SYS_MEMTEST_END 0x00400000 131 #define CONFIG_SYS_ALT_MEMTEST 132 133 #ifndef CONFIG_SYS_NO_FLASH 134 #define CONFIG_FLASH_CFI_DRIVER 135 #define CONFIG_SYS_FLASH_CFI 136 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 137 #endif 138 139 #if defined(CONFIG_SPIFLASH) 140 #define CONFIG_SYS_EXTRA_ENV_RELOC 141 #define CONFIG_ENV_IS_IN_SPI_FLASH 142 #define CONFIG_ENV_SPI_BUS 0 143 #define CONFIG_ENV_SPI_CS 0 144 #define CONFIG_ENV_SPI_MAX_HZ 10000000 145 #define CONFIG_ENV_SPI_MODE 0 146 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 147 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 148 #define CONFIG_ENV_SECT_SIZE 0x10000 149 #elif defined(CONFIG_SDCARD) 150 #define CONFIG_SYS_EXTRA_ENV_RELOC 151 #define CONFIG_ENV_IS_IN_MMC 152 #define CONFIG_SYS_MMC_ENV_DEV 0 153 #define CONFIG_ENV_SIZE 0x2000 154 #define CONFIG_ENV_OFFSET (512 * 0x800) 155 #elif defined(CONFIG_NAND) 156 #define CONFIG_SYS_EXTRA_ENV_RELOC 157 #define CONFIG_ENV_IS_IN_NAND 158 #define CONFIG_ENV_SIZE 0x2000 159 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 160 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 161 #define CONFIG_ENV_IS_IN_REMOTE 162 #define CONFIG_ENV_ADDR 0xffe20000 163 #define CONFIG_ENV_SIZE 0x2000 164 #elif defined(CONFIG_ENV_IS_NOWHERE) 165 #define CONFIG_ENV_SIZE 0x2000 166 #else 167 #define CONFIG_ENV_IS_IN_FLASH 168 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 169 #define CONFIG_ENV_SIZE 0x2000 170 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 171 #endif 172 173 #ifndef __ASSEMBLY__ 174 unsigned long get_board_sys_clk(void); 175 unsigned long get_board_ddr_clk(void); 176 #endif 177 178 #define CONFIG_SYS_CLK_FREQ 66660000 179 #define CONFIG_DDR_CLK_FREQ 133330000 180 181 /* 182 * Config the L3 Cache as L3 SRAM 183 */ 184 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 185 #define CONFIG_SYS_L3_SIZE (512 << 10) 186 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 187 #ifdef CONFIG_RAMBOOT_PBL 188 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 189 #endif 190 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 191 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 192 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 193 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 194 195 #define CONFIG_SYS_DCSRBAR 0xf0000000 196 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 197 198 /* EEPROM */ 199 #define CONFIG_ID_EEPROM 200 #define CONFIG_SYS_I2C_EEPROM_NXID 201 #define CONFIG_SYS_EEPROM_BUS_NUM 0 202 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 203 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 204 205 /* 206 * DDR Setup 207 */ 208 #define CONFIG_VERY_BIG_RAM 209 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 210 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 211 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 212 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 213 #define CONFIG_DDR_SPD 214 #define CONFIG_SYS_FSL_DDR3 215 #undef CONFIG_FSL_DDR_INTERACTIVE 216 #define CONFIG_SYS_SPD_BUS_NUM 0 217 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 218 #define SPD_EEPROM_ADDRESS1 0x51 219 #define SPD_EEPROM_ADDRESS2 0x52 220 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 221 #define CTRL_INTLV_PREFERED cacheline 222 223 /* 224 * IFC Definitions 225 */ 226 #define CONFIG_SYS_FLASH_BASE 0xe8000000 227 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 228 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 229 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 230 CSPR_PORT_SIZE_16 | \ 231 CSPR_MSEL_NOR | \ 232 CSPR_V) 233 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 234 235 /* NOR Flash Timing Params */ 236 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 237 238 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 239 FTIM0_NOR_TEADC(0x5) | \ 240 FTIM0_NOR_TEAHC(0x5)) 241 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 242 FTIM1_NOR_TRAD_NOR(0x1A) |\ 243 FTIM1_NOR_TSEQRAD_NOR(0x13)) 244 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 245 FTIM2_NOR_TCH(0x4) | \ 246 FTIM2_NOR_TWPH(0x0E) | \ 247 FTIM2_NOR_TWP(0x1c)) 248 #define CONFIG_SYS_NOR_FTIM3 0x0 249 250 #define CONFIG_SYS_FLASH_QUIET_TEST 251 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 252 253 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 254 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 255 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 256 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 257 #define CONFIG_SYS_FLASH_EMPTY_INFO 258 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 259 260 /* CPLD on IFC */ 261 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 262 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 263 #define CONFIG_SYS_CSPR2_EXT (0xf) 264 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 265 | CSPR_PORT_SIZE_8 \ 266 | CSPR_MSEL_GPCM \ 267 | CSPR_V) 268 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 269 #define CONFIG_SYS_CSOR2 0x0 270 271 /* CPLD Timing parameters for IFC CS2 */ 272 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 273 FTIM0_GPCM_TEADC(0x0e) | \ 274 FTIM0_GPCM_TEAHC(0x0e)) 275 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 276 FTIM1_GPCM_TRAD(0x1f)) 277 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 278 FTIM2_GPCM_TCH(0x8) | \ 279 FTIM2_GPCM_TWP(0x1f)) 280 #define CONFIG_SYS_CS2_FTIM3 0x0 281 282 /* NAND Flash on IFC */ 283 #define CONFIG_NAND_FSL_IFC 284 #define CONFIG_SYS_NAND_BASE 0xff800000 285 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 286 287 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 288 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 289 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 290 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 291 | CSPR_V) 292 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 293 294 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 295 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 296 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 297 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 298 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 299 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 300 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 301 302 #define CONFIG_SYS_NAND_ONFI_DETECTION 303 304 /* ONFI NAND Flash mode0 Timing Params */ 305 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 306 FTIM0_NAND_TWP(0x18) | \ 307 FTIM0_NAND_TWCHT(0x07) | \ 308 FTIM0_NAND_TWH(0x0a)) 309 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 310 FTIM1_NAND_TWBE(0x39) | \ 311 FTIM1_NAND_TRR(0x0e) | \ 312 FTIM1_NAND_TRP(0x18)) 313 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 314 FTIM2_NAND_TREH(0x0a) | \ 315 FTIM2_NAND_TWHRE(0x1e)) 316 #define CONFIG_SYS_NAND_FTIM3 0x0 317 318 #define CONFIG_SYS_NAND_DDR_LAW 11 319 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 320 #define CONFIG_SYS_MAX_NAND_DEVICE 1 321 #define CONFIG_CMD_NAND 322 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 323 324 #if defined(CONFIG_NAND) 325 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 326 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 327 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 328 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 329 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 330 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 331 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 332 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 333 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 334 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 335 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 336 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 337 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 338 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 339 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 340 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 341 #else 342 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 343 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 344 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 345 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 346 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 347 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 348 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 349 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 350 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 351 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 352 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 353 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 354 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 355 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 356 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 357 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 358 #endif 359 360 #if defined(CONFIG_RAMBOOT_PBL) 361 #define CONFIG_SYS_RAMBOOT 362 #endif 363 364 #ifdef CONFIG_SPL_BUILD 365 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 366 #else 367 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 368 #endif 369 370 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 371 #define CONFIG_MISC_INIT_R 372 #define CONFIG_HWCONFIG 373 374 /* define to use L1 as initial stack */ 375 #define CONFIG_L1_INIT_RAM 376 #define CONFIG_SYS_INIT_RAM_LOCK 377 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 378 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 380 /* The assembler doesn't like typecast */ 381 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 382 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 383 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 384 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 385 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 386 GENERATED_GBL_DATA_SIZE) 387 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 388 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 389 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 390 391 /* 392 * Serial Port 393 */ 394 #define CONFIG_CONS_INDEX 1 395 #define CONFIG_SYS_NS16550_SERIAL 396 #define CONFIG_SYS_NS16550_REG_SIZE 1 397 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 398 #define CONFIG_SYS_BAUDRATE_TABLE \ 399 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 400 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 401 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 402 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 403 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 404 405 /* 406 * I2C 407 */ 408 #define CONFIG_SYS_I2C 409 #define CONFIG_SYS_I2C_FSL 410 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 411 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 412 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 413 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 414 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 415 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 416 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 417 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 418 #define CONFIG_SYS_FSL_I2C_SPEED 100000 419 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 420 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 421 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 422 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 423 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 424 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 425 #define I2C_MUX_CH_DEFAULT 0x8 426 427 #define I2C_MUX_CH_VOL_MONITOR 0xa 428 429 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 430 #ifndef CONFIG_SPL_BUILD 431 #define CONFIG_VID 432 #endif 433 #define CONFIG_VOL_MONITOR_IR36021_SET 434 #define CONFIG_VOL_MONITOR_IR36021_READ 435 /* The lowest and highest voltage allowed for T208xRDB */ 436 #define VDD_MV_MIN 819 437 #define VDD_MV_MAX 1212 438 439 /* 440 * RapidIO 441 */ 442 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 443 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 444 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 445 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 446 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 447 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 448 /* 449 * for slave u-boot IMAGE instored in master memory space, 450 * PHYS must be aligned based on the SIZE 451 */ 452 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 453 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 454 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 455 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 456 /* 457 * for slave UCODE and ENV instored in master memory space, 458 * PHYS must be aligned based on the SIZE 459 */ 460 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 461 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 462 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 463 464 /* slave core release by master*/ 465 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 466 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 467 468 /* 469 * SRIO_PCIE_BOOT - SLAVE 470 */ 471 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 472 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 473 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 474 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 475 #endif 476 477 /* 478 * eSPI - Enhanced SPI 479 */ 480 #ifdef CONFIG_SPI_FLASH 481 #define CONFIG_SPI_FLASH_BAR 482 #define CONFIG_SF_DEFAULT_SPEED 10000000 483 #define CONFIG_SF_DEFAULT_MODE 0 484 #endif 485 486 /* 487 * General PCI 488 * Memory space is mapped 1-1, but I/O space must start from 0. 489 */ 490 #define CONFIG_PCI /* Enable PCI/PCIE */ 491 #define CONFIG_PCIE1 /* PCIE controller 1 */ 492 #define CONFIG_PCIE2 /* PCIE controller 2 */ 493 #define CONFIG_PCIE3 /* PCIE controller 3 */ 494 #define CONFIG_PCIE4 /* PCIE controller 4 */ 495 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 496 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 497 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 498 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 499 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 500 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 501 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 502 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 503 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 504 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 505 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 506 507 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 508 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 509 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 510 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 511 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 512 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 513 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 514 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 515 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 516 517 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 518 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 519 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 520 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 521 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 522 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 523 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 524 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 525 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 526 527 /* controller 4, Base address 203000 */ 528 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 529 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 530 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 531 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 532 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 533 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 534 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 535 536 #ifdef CONFIG_PCI 537 #define CONFIG_PCI_INDIRECT_BRIDGE 538 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 539 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 540 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 541 #define CONFIG_DOS_PARTITION 542 #endif 543 544 /* Qman/Bman */ 545 #ifndef CONFIG_NOBQFMAN 546 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 547 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 548 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 549 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 550 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 551 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 552 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 553 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 554 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 555 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 556 CONFIG_SYS_BMAN_CENA_SIZE) 557 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 558 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 559 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 560 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 561 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 562 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 563 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 564 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 565 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 566 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 567 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 568 CONFIG_SYS_QMAN_CENA_SIZE) 569 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 570 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 571 572 #define CONFIG_SYS_DPAA_FMAN 573 #define CONFIG_SYS_DPAA_PME 574 #define CONFIG_SYS_PMAN 575 #define CONFIG_SYS_DPAA_DCE 576 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 577 #define CONFIG_SYS_INTERLAKEN 578 579 /* Default address of microcode for the Linux Fman driver */ 580 #if defined(CONFIG_SPIFLASH) 581 /* 582 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 583 * env, so we got 0x110000. 584 */ 585 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 586 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 587 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 588 #define CONFIG_CORTINA_FW_ADDR 0x120000 589 590 #elif defined(CONFIG_SDCARD) 591 /* 592 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 593 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 594 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 595 */ 596 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 597 #define CONFIG_SYS_CORTINA_FW_IN_MMC 598 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 599 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 600 601 #elif defined(CONFIG_NAND) 602 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 603 #define CONFIG_SYS_CORTINA_FW_IN_NAND 604 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 605 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 606 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 607 /* 608 * Slave has no ucode locally, it can fetch this from remote. When implementing 609 * in two corenet boards, slave's ucode could be stored in master's memory 610 * space, the address can be mapped from slave TLB->slave LAW-> 611 * slave SRIO or PCIE outbound window->master inbound window-> 612 * master LAW->the ucode address in master's memory space. 613 */ 614 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 615 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 616 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 617 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 618 #else 619 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 620 #define CONFIG_SYS_CORTINA_FW_IN_NOR 621 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 622 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 623 #endif 624 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 625 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 626 #endif /* CONFIG_NOBQFMAN */ 627 628 #ifdef CONFIG_SYS_DPAA_FMAN 629 #define CONFIG_FMAN_ENET 630 #define CONFIG_PHYLIB_10G 631 #define CONFIG_PHY_AQUANTIA 632 #define CONFIG_PHY_CORTINA 633 #define CONFIG_PHY_REALTEK 634 #define CONFIG_CORTINA_FW_LENGTH 0x40000 635 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 636 #define RGMII_PHY2_ADDR 0x02 637 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 638 #define CORTINA_PHY_ADDR2 0x0d 639 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 640 #define FM1_10GEC4_PHY_ADDR 0x01 641 #endif 642 643 #ifdef CONFIG_FMAN_ENET 644 #define CONFIG_MII /* MII PHY management */ 645 #define CONFIG_ETHPRIME "FM1@DTSEC3" 646 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 647 #endif 648 649 /* 650 * SATA 651 */ 652 #ifdef CONFIG_FSL_SATA_V2 653 #define CONFIG_LIBATA 654 #define CONFIG_FSL_SATA 655 #define CONFIG_SYS_SATA_MAX_DEVICE 2 656 #define CONFIG_SATA1 657 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 658 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 659 #define CONFIG_SATA2 660 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 661 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 662 #define CONFIG_LBA48 663 #define CONFIG_CMD_SATA 664 #define CONFIG_DOS_PARTITION 665 #endif 666 667 /* 668 * USB 669 */ 670 #ifdef CONFIG_USB_EHCI 671 #define CONFIG_USB_EHCI_FSL 672 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 673 #define CONFIG_HAS_FSL_DR_USB 674 #endif 675 676 /* 677 * SDHC 678 */ 679 #ifdef CONFIG_MMC 680 #define CONFIG_FSL_ESDHC 681 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 682 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 683 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 684 #define CONFIG_GENERIC_MMC 685 #define CONFIG_DOS_PARTITION 686 #endif 687 688 /* 689 * Dynamic MTD Partition support with mtdparts 690 */ 691 #ifndef CONFIG_SYS_NO_FLASH 692 #define CONFIG_MTD_DEVICE 693 #define CONFIG_MTD_PARTITIONS 694 #define CONFIG_CMD_MTDPARTS 695 #define CONFIG_FLASH_CFI_MTD 696 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 697 "spi0=spife110000.1" 698 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 699 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 700 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 701 "1m(uboot),5m(kernel),128k(dtb),-(user)" 702 #endif 703 704 /* 705 * Environment 706 */ 707 708 /* 709 * Command line configuration. 710 */ 711 #define CONFIG_CMD_ERRATA 712 #define CONFIG_CMD_REGINFO 713 714 #ifdef CONFIG_PCI 715 #define CONFIG_CMD_PCI 716 #endif 717 718 /* Hash command with SHA acceleration supported in hardware */ 719 #ifdef CONFIG_FSL_CAAM 720 #define CONFIG_CMD_HASH 721 #define CONFIG_SHA_HW_ACCEL 722 #endif 723 724 /* 725 * Miscellaneous configurable options 726 */ 727 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 728 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 729 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 730 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 731 #ifdef CONFIG_CMD_KGDB 732 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 733 #else 734 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 735 #endif 736 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 737 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 738 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 739 740 /* 741 * For booting Linux, the board info and command line data 742 * have to be in the first 64 MB of memory, since this is 743 * the maximum mapped by the Linux kernel during initialization. 744 */ 745 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 746 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 747 748 #ifdef CONFIG_CMD_KGDB 749 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 750 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 751 #endif 752 753 /* 754 * Environment Configuration 755 */ 756 #define CONFIG_ROOTPATH "/opt/nfsroot" 757 #define CONFIG_BOOTFILE "uImage" 758 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 759 760 /* default location for tftp and bootm */ 761 #define CONFIG_LOADADDR 1000000 762 #define CONFIG_BAUDRATE 115200 763 #define __USB_PHY_TYPE utmi 764 765 #define CONFIG_EXTRA_ENV_SETTINGS \ 766 "hwconfig=fsl_ddr:" \ 767 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 768 "bank_intlv=auto;" \ 769 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 770 "netdev=eth0\0" \ 771 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 772 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 773 "tftpflash=tftpboot $loadaddr $uboot && " \ 774 "protect off $ubootaddr +$filesize && " \ 775 "erase $ubootaddr +$filesize && " \ 776 "cp.b $loadaddr $ubootaddr $filesize && " \ 777 "protect on $ubootaddr +$filesize && " \ 778 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 779 "consoledev=ttyS0\0" \ 780 "ramdiskaddr=2000000\0" \ 781 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 782 "fdtaddr=1e00000\0" \ 783 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 784 "bdev=sda3\0" 785 786 /* 787 * For emulation this causes u-boot to jump to the start of the 788 * proof point app code automatically 789 */ 790 #define CONFIG_PROOF_POINTS \ 791 "setenv bootargs root=/dev/$bdev rw " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "cpu 1 release 0x29000000 - - -;" \ 794 "cpu 2 release 0x29000000 - - -;" \ 795 "cpu 3 release 0x29000000 - - -;" \ 796 "cpu 4 release 0x29000000 - - -;" \ 797 "cpu 5 release 0x29000000 - - -;" \ 798 "cpu 6 release 0x29000000 - - -;" \ 799 "cpu 7 release 0x29000000 - - -;" \ 800 "go 0x29000000" 801 802 #define CONFIG_HVBOOT \ 803 "setenv bootargs config-addr=0x60000000; " \ 804 "bootm 0x01000000 - 0x00f00000" 805 806 #define CONFIG_ALU \ 807 "setenv bootargs root=/dev/$bdev rw " \ 808 "console=$consoledev,$baudrate $othbootargs;" \ 809 "cpu 1 release 0x01000000 - - -;" \ 810 "cpu 2 release 0x01000000 - - -;" \ 811 "cpu 3 release 0x01000000 - - -;" \ 812 "cpu 4 release 0x01000000 - - -;" \ 813 "cpu 5 release 0x01000000 - - -;" \ 814 "cpu 6 release 0x01000000 - - -;" \ 815 "cpu 7 release 0x01000000 - - -;" \ 816 "go 0x01000000" 817 818 #define CONFIG_LINUX \ 819 "setenv bootargs root=/dev/ram rw " \ 820 "console=$consoledev,$baudrate $othbootargs;" \ 821 "setenv ramdiskaddr 0x02000000;" \ 822 "setenv fdtaddr 0x00c00000;" \ 823 "setenv loadaddr 0x1000000;" \ 824 "bootm $loadaddr $ramdiskaddr $fdtaddr" 825 826 #define CONFIG_HDBOOT \ 827 "setenv bootargs root=/dev/$bdev rw " \ 828 "console=$consoledev,$baudrate $othbootargs;" \ 829 "tftp $loadaddr $bootfile;" \ 830 "tftp $fdtaddr $fdtfile;" \ 831 "bootm $loadaddr - $fdtaddr" 832 833 #define CONFIG_NFSBOOTCOMMAND \ 834 "setenv bootargs root=/dev/nfs rw " \ 835 "nfsroot=$serverip:$rootpath " \ 836 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 837 "console=$consoledev,$baudrate $othbootargs;" \ 838 "tftp $loadaddr $bootfile;" \ 839 "tftp $fdtaddr $fdtfile;" \ 840 "bootm $loadaddr - $fdtaddr" 841 842 #define CONFIG_RAMBOOTCOMMAND \ 843 "setenv bootargs root=/dev/ram rw " \ 844 "console=$consoledev,$baudrate $othbootargs;" \ 845 "tftp $ramdiskaddr $ramdiskfile;" \ 846 "tftp $loadaddr $bootfile;" \ 847 "tftp $fdtaddr $fdtfile;" \ 848 "bootm $loadaddr $ramdiskaddr $fdtaddr" 849 850 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 851 852 #include <asm/fsl_secure_boot.h> 853 854 #endif /* __T2080RDB_H */ 855