1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_USB_EHCI 16 #define CONFIG_FSL_SATA_V2 17 18 /* High Level Configuration Options */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 30 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 31 #define CONFIG_ENV_OVERWRITE 32 33 #ifdef CONFIG_RAMBOOT_PBL 34 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 35 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SYS_TEXT_BASE 0x00201000 39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 40 #define CONFIG_SPL_PAD_TO 0x40000 41 #define CONFIG_SPL_MAX_SIZE 0x28000 42 #define RESET_VECTOR_OFFSET 0x27FFC 43 #define BOOT_PAGE_OFFSET 0x27000 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #define CONFIG_SYS_NO_FLASH 49 #endif 50 51 #ifdef CONFIG_NAND 52 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 53 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 54 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 55 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 56 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 58 #define CONFIG_SPL_NAND_BOOT 59 #endif 60 61 #ifdef CONFIG_SPIFLASH 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 63 #define CONFIG_SPL_SPI_FLASH_MINIMAL 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 68 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 69 #ifndef CONFIG_SPL_BUILD 70 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 71 #endif 72 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 73 #define CONFIG_SPL_SPI_BOOT 74 #endif 75 76 #ifdef CONFIG_SDCARD 77 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 78 #define CONFIG_SPL_MMC_MINIMAL 79 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 80 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 81 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 82 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 84 #ifndef CONFIG_SPL_BUILD 85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 86 #endif 87 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 88 #define CONFIG_SPL_MMC_BOOT 89 #endif 90 91 #endif /* CONFIG_RAMBOOT_PBL */ 92 93 #define CONFIG_SRIO_PCIE_BOOT_MASTER 94 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 95 /* Set 1M boot space */ 96 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 97 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 98 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 99 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 100 #define CONFIG_SYS_NO_FLASH 101 #endif 102 103 #ifndef CONFIG_SYS_TEXT_BASE 104 #define CONFIG_SYS_TEXT_BASE 0xeff40000 105 #endif 106 107 #ifndef CONFIG_RESET_VECTOR_ADDRESS 108 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 109 #endif 110 111 /* 112 * These can be toggled for performance analysis, otherwise use default. 113 */ 114 #define CONFIG_SYS_CACHE_STASHING 115 #define CONFIG_BTB /* toggle branch predition */ 116 #define CONFIG_DDR_ECC 117 #ifdef CONFIG_DDR_ECC 118 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 119 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 120 #endif 121 122 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 123 #define CONFIG_SYS_MEMTEST_END 0x00400000 124 #define CONFIG_SYS_ALT_MEMTEST 125 126 #ifndef CONFIG_SYS_NO_FLASH 127 #define CONFIG_FLASH_CFI_DRIVER 128 #define CONFIG_SYS_FLASH_CFI 129 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 130 #endif 131 132 #if defined(CONFIG_SPIFLASH) 133 #define CONFIG_SYS_EXTRA_ENV_RELOC 134 #define CONFIG_ENV_IS_IN_SPI_FLASH 135 #define CONFIG_ENV_SPI_BUS 0 136 #define CONFIG_ENV_SPI_CS 0 137 #define CONFIG_ENV_SPI_MAX_HZ 10000000 138 #define CONFIG_ENV_SPI_MODE 0 139 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 140 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 141 #define CONFIG_ENV_SECT_SIZE 0x10000 142 #elif defined(CONFIG_SDCARD) 143 #define CONFIG_SYS_EXTRA_ENV_RELOC 144 #define CONFIG_ENV_IS_IN_MMC 145 #define CONFIG_SYS_MMC_ENV_DEV 0 146 #define CONFIG_ENV_SIZE 0x2000 147 #define CONFIG_ENV_OFFSET (512 * 0x800) 148 #elif defined(CONFIG_NAND) 149 #define CONFIG_SYS_EXTRA_ENV_RELOC 150 #define CONFIG_ENV_IS_IN_NAND 151 #define CONFIG_ENV_SIZE 0x2000 152 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 153 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 154 #define CONFIG_ENV_IS_IN_REMOTE 155 #define CONFIG_ENV_ADDR 0xffe20000 156 #define CONFIG_ENV_SIZE 0x2000 157 #elif defined(CONFIG_ENV_IS_NOWHERE) 158 #define CONFIG_ENV_SIZE 0x2000 159 #else 160 #define CONFIG_ENV_IS_IN_FLASH 161 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 164 #endif 165 166 #ifndef __ASSEMBLY__ 167 unsigned long get_board_sys_clk(void); 168 unsigned long get_board_ddr_clk(void); 169 #endif 170 171 #define CONFIG_SYS_CLK_FREQ 66660000 172 #define CONFIG_DDR_CLK_FREQ 133330000 173 174 /* 175 * Config the L3 Cache as L3 SRAM 176 */ 177 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 178 #define CONFIG_SYS_L3_SIZE (512 << 10) 179 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 180 #ifdef CONFIG_RAMBOOT_PBL 181 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 182 #endif 183 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 184 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 185 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 186 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 187 188 #define CONFIG_SYS_DCSRBAR 0xf0000000 189 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 190 191 /* EEPROM */ 192 #define CONFIG_ID_EEPROM 193 #define CONFIG_SYS_I2C_EEPROM_NXID 194 #define CONFIG_SYS_EEPROM_BUS_NUM 0 195 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 196 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 197 198 /* 199 * DDR Setup 200 */ 201 #define CONFIG_VERY_BIG_RAM 202 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 203 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 204 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 205 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 206 #define CONFIG_DDR_SPD 207 #undef CONFIG_FSL_DDR_INTERACTIVE 208 #define CONFIG_SYS_SPD_BUS_NUM 0 209 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 210 #define SPD_EEPROM_ADDRESS1 0x51 211 #define SPD_EEPROM_ADDRESS2 0x52 212 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 213 #define CTRL_INTLV_PREFERED cacheline 214 215 /* 216 * IFC Definitions 217 */ 218 #define CONFIG_SYS_FLASH_BASE 0xe8000000 219 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 220 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 221 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 222 CSPR_PORT_SIZE_16 | \ 223 CSPR_MSEL_NOR | \ 224 CSPR_V) 225 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 226 227 /* NOR Flash Timing Params */ 228 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 229 230 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 231 FTIM0_NOR_TEADC(0x5) | \ 232 FTIM0_NOR_TEAHC(0x5)) 233 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 234 FTIM1_NOR_TRAD_NOR(0x1A) |\ 235 FTIM1_NOR_TSEQRAD_NOR(0x13)) 236 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 237 FTIM2_NOR_TCH(0x4) | \ 238 FTIM2_NOR_TWPH(0x0E) | \ 239 FTIM2_NOR_TWP(0x1c)) 240 #define CONFIG_SYS_NOR_FTIM3 0x0 241 242 #define CONFIG_SYS_FLASH_QUIET_TEST 243 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 244 245 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 246 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 247 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 248 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 249 #define CONFIG_SYS_FLASH_EMPTY_INFO 250 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 251 252 /* CPLD on IFC */ 253 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 254 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 255 #define CONFIG_SYS_CSPR2_EXT (0xf) 256 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 257 | CSPR_PORT_SIZE_8 \ 258 | CSPR_MSEL_GPCM \ 259 | CSPR_V) 260 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 261 #define CONFIG_SYS_CSOR2 0x0 262 263 /* CPLD Timing parameters for IFC CS2 */ 264 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 265 FTIM0_GPCM_TEADC(0x0e) | \ 266 FTIM0_GPCM_TEAHC(0x0e)) 267 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 268 FTIM1_GPCM_TRAD(0x1f)) 269 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 270 FTIM2_GPCM_TCH(0x8) | \ 271 FTIM2_GPCM_TWP(0x1f)) 272 #define CONFIG_SYS_CS2_FTIM3 0x0 273 274 /* NAND Flash on IFC */ 275 #define CONFIG_NAND_FSL_IFC 276 #define CONFIG_SYS_NAND_BASE 0xff800000 277 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 278 279 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 280 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 281 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 282 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 283 | CSPR_V) 284 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 285 286 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 287 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 288 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 289 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 290 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 291 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 292 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 293 294 #define CONFIG_SYS_NAND_ONFI_DETECTION 295 296 /* ONFI NAND Flash mode0 Timing Params */ 297 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 298 FTIM0_NAND_TWP(0x18) | \ 299 FTIM0_NAND_TWCHT(0x07) | \ 300 FTIM0_NAND_TWH(0x0a)) 301 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 302 FTIM1_NAND_TWBE(0x39) | \ 303 FTIM1_NAND_TRR(0x0e) | \ 304 FTIM1_NAND_TRP(0x18)) 305 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 306 FTIM2_NAND_TREH(0x0a) | \ 307 FTIM2_NAND_TWHRE(0x1e)) 308 #define CONFIG_SYS_NAND_FTIM3 0x0 309 310 #define CONFIG_SYS_NAND_DDR_LAW 11 311 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 312 #define CONFIG_SYS_MAX_NAND_DEVICE 1 313 #define CONFIG_CMD_NAND 314 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 315 316 #if defined(CONFIG_NAND) 317 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 318 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 319 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 320 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 321 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 322 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 323 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 324 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 325 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 326 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 327 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 328 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 329 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 330 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 331 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 332 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 333 #else 334 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 335 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 336 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 337 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 338 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 339 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 340 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 341 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 342 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 343 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 344 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 345 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 346 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 347 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 348 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 349 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 350 #endif 351 352 #if defined(CONFIG_RAMBOOT_PBL) 353 #define CONFIG_SYS_RAMBOOT 354 #endif 355 356 #ifdef CONFIG_SPL_BUILD 357 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 358 #else 359 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 360 #endif 361 362 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 363 #define CONFIG_MISC_INIT_R 364 #define CONFIG_HWCONFIG 365 366 /* define to use L1 as initial stack */ 367 #define CONFIG_L1_INIT_RAM 368 #define CONFIG_SYS_INIT_RAM_LOCK 369 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 370 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 371 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 372 /* The assembler doesn't like typecast */ 373 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 374 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 375 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 376 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 377 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 378 GENERATED_GBL_DATA_SIZE) 379 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 380 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 381 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 382 383 /* 384 * Serial Port 385 */ 386 #define CONFIG_CONS_INDEX 1 387 #define CONFIG_SYS_NS16550_SERIAL 388 #define CONFIG_SYS_NS16550_REG_SIZE 1 389 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 390 #define CONFIG_SYS_BAUDRATE_TABLE \ 391 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 392 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 393 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 394 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 395 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 396 397 /* 398 * I2C 399 */ 400 #define CONFIG_SYS_I2C 401 #define CONFIG_SYS_I2C_FSL 402 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 403 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 404 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 405 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 406 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 407 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 408 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 409 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 410 #define CONFIG_SYS_FSL_I2C_SPEED 100000 411 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 412 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 413 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 414 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 415 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 416 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 417 #define I2C_MUX_CH_DEFAULT 0x8 418 419 #define I2C_MUX_CH_VOL_MONITOR 0xa 420 421 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 422 #ifndef CONFIG_SPL_BUILD 423 #define CONFIG_VID 424 #endif 425 #define CONFIG_VOL_MONITOR_IR36021_SET 426 #define CONFIG_VOL_MONITOR_IR36021_READ 427 /* The lowest and highest voltage allowed for T208xRDB */ 428 #define VDD_MV_MIN 819 429 #define VDD_MV_MAX 1212 430 431 /* 432 * RapidIO 433 */ 434 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 435 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 436 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 437 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 438 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 439 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 440 /* 441 * for slave u-boot IMAGE instored in master memory space, 442 * PHYS must be aligned based on the SIZE 443 */ 444 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 445 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 446 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 447 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 448 /* 449 * for slave UCODE and ENV instored in master memory space, 450 * PHYS must be aligned based on the SIZE 451 */ 452 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 453 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 454 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 455 456 /* slave core release by master*/ 457 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 458 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 459 460 /* 461 * SRIO_PCIE_BOOT - SLAVE 462 */ 463 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 464 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 465 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 466 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 467 #endif 468 469 /* 470 * eSPI - Enhanced SPI 471 */ 472 #ifdef CONFIG_SPI_FLASH 473 #define CONFIG_SPI_FLASH_BAR 474 #define CONFIG_SF_DEFAULT_SPEED 10000000 475 #define CONFIG_SF_DEFAULT_MODE 0 476 #endif 477 478 /* 479 * General PCI 480 * Memory space is mapped 1-1, but I/O space must start from 0. 481 */ 482 #define CONFIG_PCIE1 /* PCIE controller 1 */ 483 #define CONFIG_PCIE2 /* PCIE controller 2 */ 484 #define CONFIG_PCIE3 /* PCIE controller 3 */ 485 #define CONFIG_PCIE4 /* PCIE controller 4 */ 486 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 487 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 488 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 489 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 490 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 491 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 492 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 493 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 494 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 495 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 496 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 497 498 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 499 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 500 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 501 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 502 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 503 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 504 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 505 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 506 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 507 508 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 509 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 510 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 511 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 512 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 513 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 514 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 515 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 516 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 517 518 /* controller 4, Base address 203000 */ 519 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 520 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 521 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 522 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 523 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 524 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 525 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 526 527 #ifdef CONFIG_PCI 528 #define CONFIG_PCI_INDIRECT_BRIDGE 529 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 530 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 531 #endif 532 533 /* Qman/Bman */ 534 #ifndef CONFIG_NOBQFMAN 535 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 536 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 537 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 538 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 539 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 540 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 541 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 542 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 543 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 544 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 545 CONFIG_SYS_BMAN_CENA_SIZE) 546 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 547 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 548 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 549 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 550 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 551 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 552 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 553 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 554 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 555 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 556 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 557 CONFIG_SYS_QMAN_CENA_SIZE) 558 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 559 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 560 561 #define CONFIG_SYS_DPAA_FMAN 562 #define CONFIG_SYS_DPAA_PME 563 #define CONFIG_SYS_PMAN 564 #define CONFIG_SYS_DPAA_DCE 565 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 566 #define CONFIG_SYS_INTERLAKEN 567 568 /* Default address of microcode for the Linux Fman driver */ 569 #if defined(CONFIG_SPIFLASH) 570 /* 571 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 572 * env, so we got 0x110000. 573 */ 574 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 575 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 576 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 577 #define CONFIG_CORTINA_FW_ADDR 0x120000 578 579 #elif defined(CONFIG_SDCARD) 580 /* 581 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 582 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 583 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 584 */ 585 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 586 #define CONFIG_SYS_CORTINA_FW_IN_MMC 587 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 588 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 589 590 #elif defined(CONFIG_NAND) 591 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 592 #define CONFIG_SYS_CORTINA_FW_IN_NAND 593 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 594 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 595 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 596 /* 597 * Slave has no ucode locally, it can fetch this from remote. When implementing 598 * in two corenet boards, slave's ucode could be stored in master's memory 599 * space, the address can be mapped from slave TLB->slave LAW-> 600 * slave SRIO or PCIE outbound window->master inbound window-> 601 * master LAW->the ucode address in master's memory space. 602 */ 603 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 604 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 605 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 606 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 607 #else 608 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 609 #define CONFIG_SYS_CORTINA_FW_IN_NOR 610 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 611 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 612 #endif 613 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 614 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 615 #endif /* CONFIG_NOBQFMAN */ 616 617 #ifdef CONFIG_SYS_DPAA_FMAN 618 #define CONFIG_FMAN_ENET 619 #define CONFIG_PHYLIB_10G 620 #define CONFIG_PHY_AQUANTIA 621 #define CONFIG_PHY_CORTINA 622 #define CONFIG_PHY_REALTEK 623 #define CONFIG_CORTINA_FW_LENGTH 0x40000 624 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 625 #define RGMII_PHY2_ADDR 0x02 626 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 627 #define CORTINA_PHY_ADDR2 0x0d 628 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 629 #define FM1_10GEC4_PHY_ADDR 0x01 630 #endif 631 632 #ifdef CONFIG_FMAN_ENET 633 #define CONFIG_MII /* MII PHY management */ 634 #define CONFIG_ETHPRIME "FM1@DTSEC3" 635 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 636 #endif 637 638 /* 639 * SATA 640 */ 641 #ifdef CONFIG_FSL_SATA_V2 642 #define CONFIG_LIBATA 643 #define CONFIG_FSL_SATA 644 #define CONFIG_SYS_SATA_MAX_DEVICE 2 645 #define CONFIG_SATA1 646 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 647 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 648 #define CONFIG_SATA2 649 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 650 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 651 #define CONFIG_LBA48 652 #define CONFIG_CMD_SATA 653 #endif 654 655 /* 656 * USB 657 */ 658 #ifdef CONFIG_USB_EHCI 659 #define CONFIG_USB_EHCI_FSL 660 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 661 #define CONFIG_HAS_FSL_DR_USB 662 #endif 663 664 /* 665 * SDHC 666 */ 667 #ifdef CONFIG_MMC 668 #define CONFIG_FSL_ESDHC 669 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 670 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 671 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 672 #endif 673 674 /* 675 * Dynamic MTD Partition support with mtdparts 676 */ 677 #ifndef CONFIG_SYS_NO_FLASH 678 #define CONFIG_MTD_DEVICE 679 #define CONFIG_MTD_PARTITIONS 680 #define CONFIG_CMD_MTDPARTS 681 #define CONFIG_FLASH_CFI_MTD 682 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 683 "spi0=spife110000.1" 684 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 685 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 686 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 687 "1m(uboot),5m(kernel),128k(dtb),-(user)" 688 #endif 689 690 /* 691 * Environment 692 */ 693 694 /* 695 * Command line configuration. 696 */ 697 #define CONFIG_CMD_ERRATA 698 #define CONFIG_CMD_REGINFO 699 700 #ifdef CONFIG_PCI 701 #define CONFIG_CMD_PCI 702 #endif 703 704 /* Hash command with SHA acceleration supported in hardware */ 705 #ifdef CONFIG_FSL_CAAM 706 #define CONFIG_CMD_HASH 707 #define CONFIG_SHA_HW_ACCEL 708 #endif 709 710 /* 711 * Miscellaneous configurable options 712 */ 713 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 714 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 715 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 716 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 717 #ifdef CONFIG_CMD_KGDB 718 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 719 #else 720 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 721 #endif 722 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 723 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 724 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 725 726 /* 727 * For booting Linux, the board info and command line data 728 * have to be in the first 64 MB of memory, since this is 729 * the maximum mapped by the Linux kernel during initialization. 730 */ 731 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 732 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 733 734 #ifdef CONFIG_CMD_KGDB 735 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 736 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 737 #endif 738 739 /* 740 * Environment Configuration 741 */ 742 #define CONFIG_ROOTPATH "/opt/nfsroot" 743 #define CONFIG_BOOTFILE "uImage" 744 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 745 746 /* default location for tftp and bootm */ 747 #define CONFIG_LOADADDR 1000000 748 #define CONFIG_BAUDRATE 115200 749 #define __USB_PHY_TYPE utmi 750 751 #define CONFIG_EXTRA_ENV_SETTINGS \ 752 "hwconfig=fsl_ddr:" \ 753 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 754 "bank_intlv=auto;" \ 755 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 756 "netdev=eth0\0" \ 757 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 758 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 759 "tftpflash=tftpboot $loadaddr $uboot && " \ 760 "protect off $ubootaddr +$filesize && " \ 761 "erase $ubootaddr +$filesize && " \ 762 "cp.b $loadaddr $ubootaddr $filesize && " \ 763 "protect on $ubootaddr +$filesize && " \ 764 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 765 "consoledev=ttyS0\0" \ 766 "ramdiskaddr=2000000\0" \ 767 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 768 "fdtaddr=1e00000\0" \ 769 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 770 "bdev=sda3\0" 771 772 /* 773 * For emulation this causes u-boot to jump to the start of the 774 * proof point app code automatically 775 */ 776 #define CONFIG_PROOF_POINTS \ 777 "setenv bootargs root=/dev/$bdev rw " \ 778 "console=$consoledev,$baudrate $othbootargs;" \ 779 "cpu 1 release 0x29000000 - - -;" \ 780 "cpu 2 release 0x29000000 - - -;" \ 781 "cpu 3 release 0x29000000 - - -;" \ 782 "cpu 4 release 0x29000000 - - -;" \ 783 "cpu 5 release 0x29000000 - - -;" \ 784 "cpu 6 release 0x29000000 - - -;" \ 785 "cpu 7 release 0x29000000 - - -;" \ 786 "go 0x29000000" 787 788 #define CONFIG_HVBOOT \ 789 "setenv bootargs config-addr=0x60000000; " \ 790 "bootm 0x01000000 - 0x00f00000" 791 792 #define CONFIG_ALU \ 793 "setenv bootargs root=/dev/$bdev rw " \ 794 "console=$consoledev,$baudrate $othbootargs;" \ 795 "cpu 1 release 0x01000000 - - -;" \ 796 "cpu 2 release 0x01000000 - - -;" \ 797 "cpu 3 release 0x01000000 - - -;" \ 798 "cpu 4 release 0x01000000 - - -;" \ 799 "cpu 5 release 0x01000000 - - -;" \ 800 "cpu 6 release 0x01000000 - - -;" \ 801 "cpu 7 release 0x01000000 - - -;" \ 802 "go 0x01000000" 803 804 #define CONFIG_LINUX \ 805 "setenv bootargs root=/dev/ram rw " \ 806 "console=$consoledev,$baudrate $othbootargs;" \ 807 "setenv ramdiskaddr 0x02000000;" \ 808 "setenv fdtaddr 0x00c00000;" \ 809 "setenv loadaddr 0x1000000;" \ 810 "bootm $loadaddr $ramdiskaddr $fdtaddr" 811 812 #define CONFIG_HDBOOT \ 813 "setenv bootargs root=/dev/$bdev rw " \ 814 "console=$consoledev,$baudrate $othbootargs;" \ 815 "tftp $loadaddr $bootfile;" \ 816 "tftp $fdtaddr $fdtfile;" \ 817 "bootm $loadaddr - $fdtaddr" 818 819 #define CONFIG_NFSBOOTCOMMAND \ 820 "setenv bootargs root=/dev/nfs rw " \ 821 "nfsroot=$serverip:$rootpath " \ 822 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 823 "console=$consoledev,$baudrate $othbootargs;" \ 824 "tftp $loadaddr $bootfile;" \ 825 "tftp $fdtaddr $fdtfile;" \ 826 "bootm $loadaddr - $fdtaddr" 827 828 #define CONFIG_RAMBOOTCOMMAND \ 829 "setenv bootargs root=/dev/ram rw " \ 830 "console=$consoledev,$baudrate $othbootargs;" \ 831 "tftp $ramdiskaddr $ramdiskfile;" \ 832 "tftp $loadaddr $bootfile;" \ 833 "tftp $fdtaddr $fdtfile;" \ 834 "bootm $loadaddr $ramdiskaddr $fdtaddr" 835 836 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 837 838 #include <asm/fsl_secure_boot.h> 839 840 #endif /* __T2080RDB_H */ 841