1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_T2080RDB 17 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 18 #define CONFIG_MMC 19 #define CONFIG_SPI_FLASH 20 #define CONFIG_USB_EHCI 21 #define CONFIG_FSL_SATA_V2 22 23 /* High Level Configuration Options */ 24 #define CONFIG_PHYS_64BIT 25 #define CONFIG_BOOKE 26 #define CONFIG_E500 /* BOOKE e500 family */ 27 #define CONFIG_E500MC /* BOOKE e500mc family */ 28 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 29 #define CONFIG_MP /* support multiple processors */ 30 #define CONFIG_ENABLE_36BIT_PHYS 31 32 #ifdef CONFIG_PHYS_64BIT 33 #define CONFIG_ADDR_MAP 1 34 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 35 #endif 36 37 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 38 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 39 #define CONFIG_FSL_IFC /* Enable IFC Support */ 40 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 41 #define CONFIG_FSL_LAW /* Use common FSL init code */ 42 #define CONFIG_ENV_OVERWRITE 43 44 #ifdef CONFIG_RAMBOOT_PBL 45 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 46 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 47 48 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 49 #define CONFIG_SPL_ENV_SUPPORT 50 #define CONFIG_SPL_SERIAL_SUPPORT 51 #define CONFIG_SPL_FLUSH_IMAGE 52 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 53 #define CONFIG_SPL_LIBGENERIC_SUPPORT 54 #define CONFIG_SPL_LIBCOMMON_SUPPORT 55 #define CONFIG_SPL_I2C_SUPPORT 56 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 57 #define CONFIG_FSL_LAW /* Use common FSL init code */ 58 #define CONFIG_SYS_TEXT_BASE 0x00201000 59 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 60 #define CONFIG_SPL_PAD_TO 0x40000 61 #define CONFIG_SPL_MAX_SIZE 0x28000 62 #define RESET_VECTOR_OFFSET 0x27FFC 63 #define BOOT_PAGE_OFFSET 0x27000 64 #ifdef CONFIG_SPL_BUILD 65 #define CONFIG_SPL_SKIP_RELOCATE 66 #define CONFIG_SPL_COMMON_INIT_DDR 67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 68 #define CONFIG_SYS_NO_FLASH 69 #endif 70 71 #ifdef CONFIG_NAND 72 #define CONFIG_SPL_NAND_SUPPORT 73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 74 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 75 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 78 #define CONFIG_SPL_NAND_BOOT 79 #endif 80 81 #ifdef CONFIG_SPIFLASH 82 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 83 #define CONFIG_SPL_SPI_SUPPORT 84 #define CONFIG_SPL_SPI_FLASH_SUPPORT 85 #define CONFIG_SPL_SPI_FLASH_MINIMAL 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 91 #ifndef CONFIG_SPL_BUILD 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #endif 94 #define CONFIG_SPL_SPI_BOOT 95 #endif 96 97 #ifdef CONFIG_SDCARD 98 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 99 #define CONFIG_SPL_MMC_SUPPORT 100 #define CONFIG_SPL_MMC_MINIMAL 101 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 102 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 103 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 104 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 105 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 106 #ifndef CONFIG_SPL_BUILD 107 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 108 #endif 109 #define CONFIG_SPL_MMC_BOOT 110 #endif 111 112 #endif /* CONFIG_RAMBOOT_PBL */ 113 114 #define CONFIG_SRIO_PCIE_BOOT_MASTER 115 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 116 /* Set 1M boot space */ 117 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 118 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 119 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 120 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 121 #define CONFIG_SYS_NO_FLASH 122 #endif 123 124 #ifndef CONFIG_SYS_TEXT_BASE 125 #define CONFIG_SYS_TEXT_BASE 0xeff40000 126 #endif 127 128 #ifndef CONFIG_RESET_VECTOR_ADDRESS 129 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 130 #endif 131 132 /* 133 * These can be toggled for performance analysis, otherwise use default. 134 */ 135 #define CONFIG_SYS_CACHE_STASHING 136 #define CONFIG_BTB /* toggle branch predition */ 137 #define CONFIG_DDR_ECC 138 #ifdef CONFIG_DDR_ECC 139 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 140 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 141 #endif 142 143 #define CONFIG_CMD_MEMTEST 144 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 145 #define CONFIG_SYS_MEMTEST_END 0x00400000 146 #define CONFIG_SYS_ALT_MEMTEST 147 148 #ifndef CONFIG_SYS_NO_FLASH 149 #define CONFIG_FLASH_CFI_DRIVER 150 #define CONFIG_SYS_FLASH_CFI 151 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 152 #endif 153 154 #if defined(CONFIG_SPIFLASH) 155 #define CONFIG_SYS_EXTRA_ENV_RELOC 156 #define CONFIG_ENV_IS_IN_SPI_FLASH 157 #define CONFIG_ENV_SPI_BUS 0 158 #define CONFIG_ENV_SPI_CS 0 159 #define CONFIG_ENV_SPI_MAX_HZ 10000000 160 #define CONFIG_ENV_SPI_MODE 0 161 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 162 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 163 #define CONFIG_ENV_SECT_SIZE 0x10000 164 #elif defined(CONFIG_SDCARD) 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_ENV_IS_IN_MMC 167 #define CONFIG_SYS_MMC_ENV_DEV 0 168 #define CONFIG_ENV_SIZE 0x2000 169 #define CONFIG_ENV_OFFSET (512 * 0x800) 170 #elif defined(CONFIG_NAND) 171 #define CONFIG_SYS_EXTRA_ENV_RELOC 172 #define CONFIG_ENV_IS_IN_NAND 173 #define CONFIG_ENV_SIZE 0x2000 174 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 175 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 176 #define CONFIG_ENV_IS_IN_REMOTE 177 #define CONFIG_ENV_ADDR 0xffe20000 178 #define CONFIG_ENV_SIZE 0x2000 179 #elif defined(CONFIG_ENV_IS_NOWHERE) 180 #define CONFIG_ENV_SIZE 0x2000 181 #else 182 #define CONFIG_ENV_IS_IN_FLASH 183 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 184 #define CONFIG_ENV_SIZE 0x2000 185 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 186 #endif 187 188 #ifndef __ASSEMBLY__ 189 unsigned long get_board_sys_clk(void); 190 unsigned long get_board_ddr_clk(void); 191 #endif 192 193 #define CONFIG_SYS_CLK_FREQ 66660000 194 #define CONFIG_DDR_CLK_FREQ 133330000 195 196 /* 197 * Config the L3 Cache as L3 SRAM 198 */ 199 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 200 #define CONFIG_SYS_L3_SIZE (512 << 10) 201 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 202 #ifdef CONFIG_RAMBOOT_PBL 203 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 204 #endif 205 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 206 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 207 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 208 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 209 210 #define CONFIG_SYS_DCSRBAR 0xf0000000 211 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 212 213 /* EEPROM */ 214 #define CONFIG_ID_EEPROM 215 #define CONFIG_SYS_I2C_EEPROM_NXID 216 #define CONFIG_SYS_EEPROM_BUS_NUM 0 217 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 218 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 219 220 /* 221 * DDR Setup 222 */ 223 #define CONFIG_VERY_BIG_RAM 224 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 225 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 226 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 227 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 228 #define CONFIG_DDR_SPD 229 #define CONFIG_SYS_FSL_DDR3 230 #undef CONFIG_FSL_DDR_INTERACTIVE 231 #define CONFIG_SYS_SPD_BUS_NUM 0 232 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 233 #define SPD_EEPROM_ADDRESS1 0x51 234 #define SPD_EEPROM_ADDRESS2 0x52 235 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 236 #define CTRL_INTLV_PREFERED cacheline 237 238 /* 239 * IFC Definitions 240 */ 241 #define CONFIG_SYS_FLASH_BASE 0xe8000000 242 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 243 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 244 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 245 CSPR_PORT_SIZE_16 | \ 246 CSPR_MSEL_NOR | \ 247 CSPR_V) 248 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 249 250 /* NOR Flash Timing Params */ 251 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 252 253 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 254 FTIM0_NOR_TEADC(0x5) | \ 255 FTIM0_NOR_TEAHC(0x5)) 256 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 257 FTIM1_NOR_TRAD_NOR(0x1A) |\ 258 FTIM1_NOR_TSEQRAD_NOR(0x13)) 259 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 260 FTIM2_NOR_TCH(0x4) | \ 261 FTIM2_NOR_TWPH(0x0E) | \ 262 FTIM2_NOR_TWP(0x1c)) 263 #define CONFIG_SYS_NOR_FTIM3 0x0 264 265 #define CONFIG_SYS_FLASH_QUIET_TEST 266 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 267 268 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 269 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 270 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 271 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 272 #define CONFIG_SYS_FLASH_EMPTY_INFO 273 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 274 275 /* CPLD on IFC */ 276 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 277 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 278 #define CONFIG_SYS_CSPR2_EXT (0xf) 279 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 280 | CSPR_PORT_SIZE_8 \ 281 | CSPR_MSEL_GPCM \ 282 | CSPR_V) 283 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 284 #define CONFIG_SYS_CSOR2 0x0 285 286 /* CPLD Timing parameters for IFC CS2 */ 287 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 288 FTIM0_GPCM_TEADC(0x0e) | \ 289 FTIM0_GPCM_TEAHC(0x0e)) 290 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 291 FTIM1_GPCM_TRAD(0x1f)) 292 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 293 FTIM2_GPCM_TCH(0x8) | \ 294 FTIM2_GPCM_TWP(0x1f)) 295 #define CONFIG_SYS_CS2_FTIM3 0x0 296 297 /* NAND Flash on IFC */ 298 #define CONFIG_NAND_FSL_IFC 299 #define CONFIG_SYS_NAND_BASE 0xff800000 300 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 301 302 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 303 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 304 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 305 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 306 | CSPR_V) 307 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 308 309 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 310 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 311 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 312 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 313 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 314 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 315 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 316 317 #define CONFIG_SYS_NAND_ONFI_DETECTION 318 319 /* ONFI NAND Flash mode0 Timing Params */ 320 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 321 FTIM0_NAND_TWP(0x18) | \ 322 FTIM0_NAND_TWCHT(0x07) | \ 323 FTIM0_NAND_TWH(0x0a)) 324 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 325 FTIM1_NAND_TWBE(0x39) | \ 326 FTIM1_NAND_TRR(0x0e) | \ 327 FTIM1_NAND_TRP(0x18)) 328 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 329 FTIM2_NAND_TREH(0x0a) | \ 330 FTIM2_NAND_TWHRE(0x1e)) 331 #define CONFIG_SYS_NAND_FTIM3 0x0 332 333 #define CONFIG_SYS_NAND_DDR_LAW 11 334 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 335 #define CONFIG_SYS_MAX_NAND_DEVICE 1 336 #define CONFIG_CMD_NAND 337 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 338 339 #if defined(CONFIG_NAND) 340 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 341 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 342 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 343 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 344 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 345 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 346 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 347 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 348 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 349 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 350 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 351 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 352 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 353 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 354 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 355 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 356 #else 357 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 358 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 359 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 360 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 361 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 362 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 363 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 364 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 365 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 366 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 367 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 368 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 369 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 370 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 371 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 372 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 373 #endif 374 375 #if defined(CONFIG_RAMBOOT_PBL) 376 #define CONFIG_SYS_RAMBOOT 377 #endif 378 379 #ifdef CONFIG_SPL_BUILD 380 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 381 #else 382 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 383 #endif 384 385 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 386 #define CONFIG_MISC_INIT_R 387 #define CONFIG_HWCONFIG 388 389 /* define to use L1 as initial stack */ 390 #define CONFIG_L1_INIT_RAM 391 #define CONFIG_SYS_INIT_RAM_LOCK 392 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 395 /* The assembler doesn't like typecast */ 396 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 397 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 398 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 399 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 400 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 401 GENERATED_GBL_DATA_SIZE) 402 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 403 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 404 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 405 406 /* 407 * Serial Port 408 */ 409 #define CONFIG_CONS_INDEX 1 410 #define CONFIG_SYS_NS16550 411 #define CONFIG_SYS_NS16550_SERIAL 412 #define CONFIG_SYS_NS16550_REG_SIZE 1 413 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 414 #define CONFIG_SYS_BAUDRATE_TABLE \ 415 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 416 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 417 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 418 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 419 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 420 421 /* Use the HUSH parser */ 422 #define CONFIG_SYS_HUSH_PARSER 423 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 424 425 /* pass open firmware flat tree */ 426 #define CONFIG_OF_LIBFDT 427 #define CONFIG_OF_BOARD_SETUP 428 #define CONFIG_OF_STDOUT_VIA_ALIAS 429 430 /* new uImage format support */ 431 #define CONFIG_FIT 432 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 433 434 /* 435 * I2C 436 */ 437 #define CONFIG_SYS_I2C 438 #define CONFIG_SYS_I2C_FSL 439 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 440 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 441 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 442 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 443 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 444 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 445 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 446 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 447 #define CONFIG_SYS_FSL_I2C_SPEED 100000 448 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 449 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 450 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 451 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 452 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 453 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 454 #define I2C_MUX_CH_DEFAULT 0x8 455 456 #define I2C_MUX_CH_VOL_MONITOR 0xa 457 458 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 459 #ifndef CONFIG_SPL_BUILD 460 #define CONFIG_VID 461 #endif 462 #define CONFIG_VOL_MONITOR_IR36021_SET 463 #define CONFIG_VOL_MONITOR_IR36021_READ 464 /* The lowest and highest voltage allowed for T208xRDB */ 465 #define VDD_MV_MIN 819 466 #define VDD_MV_MAX 1212 467 468 /* 469 * RapidIO 470 */ 471 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 472 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 473 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 474 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 475 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 476 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 477 /* 478 * for slave u-boot IMAGE instored in master memory space, 479 * PHYS must be aligned based on the SIZE 480 */ 481 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 482 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 483 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 484 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 485 /* 486 * for slave UCODE and ENV instored in master memory space, 487 * PHYS must be aligned based on the SIZE 488 */ 489 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 490 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 491 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 492 493 /* slave core release by master*/ 494 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 495 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 496 497 /* 498 * SRIO_PCIE_BOOT - SLAVE 499 */ 500 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 501 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 502 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 503 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 504 #endif 505 506 /* 507 * eSPI - Enhanced SPI 508 */ 509 #ifdef CONFIG_SPI_FLASH 510 #define CONFIG_FSL_ESPI 511 #define CONFIG_SPI_FLASH_STMICRO 512 #define CONFIG_SPI_FLASH_BAR 513 #define CONFIG_CMD_SF 514 #define CONFIG_SF_DEFAULT_SPEED 10000000 515 #define CONFIG_SF_DEFAULT_MODE 0 516 #endif 517 518 /* 519 * General PCI 520 * Memory space is mapped 1-1, but I/O space must start from 0. 521 */ 522 #define CONFIG_PCI /* Enable PCI/PCIE */ 523 #define CONFIG_PCIE1 /* PCIE controler 1 */ 524 #define CONFIG_PCIE2 /* PCIE controler 2 */ 525 #define CONFIG_PCIE3 /* PCIE controler 3 */ 526 #define CONFIG_PCIE4 /* PCIE controler 4 */ 527 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 528 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 529 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 530 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 531 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 532 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 533 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 534 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 535 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 536 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 537 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 538 539 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 540 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 541 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 542 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 543 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 544 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 545 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 546 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 547 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 548 549 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 550 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 551 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 552 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 553 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 554 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 555 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 556 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 557 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 558 559 /* controller 4, Base address 203000 */ 560 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 561 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 562 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 563 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 564 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 565 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 566 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 567 568 #ifdef CONFIG_PCI 569 #define CONFIG_PCI_INDIRECT_BRIDGE 570 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 571 #define CONFIG_E1000 572 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 573 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 574 #define CONFIG_DOS_PARTITION 575 #endif 576 577 /* Qman/Bman */ 578 #ifndef CONFIG_NOBQFMAN 579 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 580 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 581 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 582 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 583 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 584 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 585 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 586 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 587 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 588 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 589 CONFIG_SYS_BMAN_CENA_SIZE) 590 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 591 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 592 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 593 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 594 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 595 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 596 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 597 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 598 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 599 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 600 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 601 CONFIG_SYS_QMAN_CENA_SIZE) 602 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 603 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 604 605 #define CONFIG_SYS_DPAA_FMAN 606 #define CONFIG_SYS_DPAA_PME 607 #define CONFIG_SYS_PMAN 608 #define CONFIG_SYS_DPAA_DCE 609 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 610 #define CONFIG_SYS_INTERLAKEN 611 612 /* Default address of microcode for the Linux Fman driver */ 613 #if defined(CONFIG_SPIFLASH) 614 /* 615 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 616 * env, so we got 0x110000. 617 */ 618 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 619 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 620 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 621 #define CONFIG_CORTINA_FW_ADDR 0x120000 622 623 #elif defined(CONFIG_SDCARD) 624 /* 625 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 626 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 627 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 628 */ 629 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 630 #define CONFIG_SYS_CORTINA_FW_IN_MMC 631 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 632 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 633 634 #elif defined(CONFIG_NAND) 635 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 636 #define CONFIG_SYS_CORTINA_FW_IN_NAND 637 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 638 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 639 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 640 /* 641 * Slave has no ucode locally, it can fetch this from remote. When implementing 642 * in two corenet boards, slave's ucode could be stored in master's memory 643 * space, the address can be mapped from slave TLB->slave LAW-> 644 * slave SRIO or PCIE outbound window->master inbound window-> 645 * master LAW->the ucode address in master's memory space. 646 */ 647 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 648 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 649 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 650 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 651 #else 652 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 653 #define CONFIG_SYS_CORTINA_FW_IN_NOR 654 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 655 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 656 #endif 657 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 658 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 659 #endif /* CONFIG_NOBQFMAN */ 660 661 #ifdef CONFIG_SYS_DPAA_FMAN 662 #define CONFIG_FMAN_ENET 663 #define CONFIG_PHYLIB_10G 664 #define CONFIG_PHY_AQUANTIA 665 #define CONFIG_PHY_CORTINA 666 #define CONFIG_PHY_REALTEK 667 #define CONFIG_CORTINA_FW_LENGTH 0x40000 668 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 669 #define RGMII_PHY2_ADDR 0x02 670 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 671 #define CORTINA_PHY_ADDR2 0x0d 672 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 673 #define FM1_10GEC4_PHY_ADDR 0x01 674 #endif 675 676 677 #ifdef CONFIG_FMAN_ENET 678 #define CONFIG_MII /* MII PHY management */ 679 #define CONFIG_ETHPRIME "FM1@DTSEC3" 680 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 681 #endif 682 683 /* 684 * SATA 685 */ 686 #ifdef CONFIG_FSL_SATA_V2 687 #define CONFIG_LIBATA 688 #define CONFIG_FSL_SATA 689 #define CONFIG_SYS_SATA_MAX_DEVICE 2 690 #define CONFIG_SATA1 691 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 692 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 693 #define CONFIG_SATA2 694 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 695 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 696 #define CONFIG_LBA48 697 #define CONFIG_CMD_SATA 698 #define CONFIG_DOS_PARTITION 699 #define CONFIG_CMD_EXT2 700 #endif 701 702 /* 703 * USB 704 */ 705 #ifdef CONFIG_USB_EHCI 706 #define CONFIG_CMD_USB 707 #define CONFIG_USB_STORAGE 708 #define CONFIG_USB_EHCI_FSL 709 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 710 #define CONFIG_CMD_EXT2 711 #define CONFIG_HAS_FSL_DR_USB 712 #endif 713 714 /* 715 * SDHC 716 */ 717 #ifdef CONFIG_MMC 718 #define CONFIG_CMD_MMC 719 #define CONFIG_FSL_ESDHC 720 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 721 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 722 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 723 #define CONFIG_GENERIC_MMC 724 #define CONFIG_CMD_EXT2 725 #define CONFIG_CMD_FAT 726 #define CONFIG_DOS_PARTITION 727 #endif 728 729 /* 730 * Dynamic MTD Partition support with mtdparts 731 */ 732 #ifndef CONFIG_SYS_NO_FLASH 733 #define CONFIG_MTD_DEVICE 734 #define CONFIG_MTD_PARTITIONS 735 #define CONFIG_CMD_MTDPARTS 736 #define CONFIG_FLASH_CFI_MTD 737 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 738 "spi0=spife110000.1" 739 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 740 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 741 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 742 "1m(uboot),5m(kernel),128k(dtb),-(user)" 743 #endif 744 745 /* 746 * Environment 747 */ 748 749 /* 750 * Command line configuration. 751 */ 752 #include <config_cmd_default.h> 753 754 #define CONFIG_CMD_DHCP 755 #define CONFIG_CMD_ELF 756 #define CONFIG_CMD_ERRATA 757 #define CONFIG_CMD_MII 758 #define CONFIG_CMD_I2C 759 #define CONFIG_CMD_PING 760 #define CONFIG_CMD_ECHO 761 #define CONFIG_CMD_REGINFO 762 #define CONFIG_CMD_BDI 763 764 #ifdef CONFIG_PCI 765 #define CONFIG_CMD_PCI 766 #endif 767 768 /* Hash command with SHA acceleration supported in hardware */ 769 #ifdef CONFIG_FSL_CAAM 770 #define CONFIG_CMD_HASH 771 #define CONFIG_SHA_HW_ACCEL 772 #endif 773 774 /* 775 * Miscellaneous configurable options 776 */ 777 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 778 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 779 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 780 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 781 #ifdef CONFIG_CMD_KGDB 782 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 783 #else 784 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 785 #endif 786 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 787 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 788 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 789 790 /* 791 * For booting Linux, the board info and command line data 792 * have to be in the first 64 MB of memory, since this is 793 * the maximum mapped by the Linux kernel during initialization. 794 */ 795 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 796 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 797 798 #ifdef CONFIG_CMD_KGDB 799 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 800 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 801 #endif 802 803 /* 804 * Environment Configuration 805 */ 806 #define CONFIG_ROOTPATH "/opt/nfsroot" 807 #define CONFIG_BOOTFILE "uImage" 808 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 809 810 /* default location for tftp and bootm */ 811 #define CONFIG_LOADADDR 1000000 812 #define CONFIG_BAUDRATE 115200 813 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 814 #define __USB_PHY_TYPE utmi 815 816 #define CONFIG_EXTRA_ENV_SETTINGS \ 817 "hwconfig=fsl_ddr:" \ 818 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 819 "bank_intlv=auto;" \ 820 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 821 "netdev=eth0\0" \ 822 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 823 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 824 "tftpflash=tftpboot $loadaddr $uboot && " \ 825 "protect off $ubootaddr +$filesize && " \ 826 "erase $ubootaddr +$filesize && " \ 827 "cp.b $loadaddr $ubootaddr $filesize && " \ 828 "protect on $ubootaddr +$filesize && " \ 829 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 830 "consoledev=ttyS0\0" \ 831 "ramdiskaddr=2000000\0" \ 832 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 833 "fdtaddr=c00000\0" \ 834 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 835 "bdev=sda3\0" 836 837 /* 838 * For emulation this causes u-boot to jump to the start of the 839 * proof point app code automatically 840 */ 841 #define CONFIG_PROOF_POINTS \ 842 "setenv bootargs root=/dev/$bdev rw " \ 843 "console=$consoledev,$baudrate $othbootargs;" \ 844 "cpu 1 release 0x29000000 - - -;" \ 845 "cpu 2 release 0x29000000 - - -;" \ 846 "cpu 3 release 0x29000000 - - -;" \ 847 "cpu 4 release 0x29000000 - - -;" \ 848 "cpu 5 release 0x29000000 - - -;" \ 849 "cpu 6 release 0x29000000 - - -;" \ 850 "cpu 7 release 0x29000000 - - -;" \ 851 "go 0x29000000" 852 853 #define CONFIG_HVBOOT \ 854 "setenv bootargs config-addr=0x60000000; " \ 855 "bootm 0x01000000 - 0x00f00000" 856 857 #define CONFIG_ALU \ 858 "setenv bootargs root=/dev/$bdev rw " \ 859 "console=$consoledev,$baudrate $othbootargs;" \ 860 "cpu 1 release 0x01000000 - - -;" \ 861 "cpu 2 release 0x01000000 - - -;" \ 862 "cpu 3 release 0x01000000 - - -;" \ 863 "cpu 4 release 0x01000000 - - -;" \ 864 "cpu 5 release 0x01000000 - - -;" \ 865 "cpu 6 release 0x01000000 - - -;" \ 866 "cpu 7 release 0x01000000 - - -;" \ 867 "go 0x01000000" 868 869 #define CONFIG_LINUX \ 870 "setenv bootargs root=/dev/ram rw " \ 871 "console=$consoledev,$baudrate $othbootargs;" \ 872 "setenv ramdiskaddr 0x02000000;" \ 873 "setenv fdtaddr 0x00c00000;" \ 874 "setenv loadaddr 0x1000000;" \ 875 "bootm $loadaddr $ramdiskaddr $fdtaddr" 876 877 #define CONFIG_HDBOOT \ 878 "setenv bootargs root=/dev/$bdev rw " \ 879 "console=$consoledev,$baudrate $othbootargs;" \ 880 "tftp $loadaddr $bootfile;" \ 881 "tftp $fdtaddr $fdtfile;" \ 882 "bootm $loadaddr - $fdtaddr" 883 884 #define CONFIG_NFSBOOTCOMMAND \ 885 "setenv bootargs root=/dev/nfs rw " \ 886 "nfsroot=$serverip:$rootpath " \ 887 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 888 "console=$consoledev,$baudrate $othbootargs;" \ 889 "tftp $loadaddr $bootfile;" \ 890 "tftp $fdtaddr $fdtfile;" \ 891 "bootm $loadaddr - $fdtaddr" 892 893 #define CONFIG_RAMBOOTCOMMAND \ 894 "setenv bootargs root=/dev/ram rw " \ 895 "console=$consoledev,$baudrate $othbootargs;" \ 896 "tftp $ramdiskaddr $ramdiskfile;" \ 897 "tftp $loadaddr $bootfile;" \ 898 "tftp $fdtaddr $fdtfile;" \ 899 "bootm $loadaddr $ramdiskaddr $fdtaddr" 900 901 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 902 903 #ifdef CONFIG_SECURE_BOOT 904 #include <asm/fsl_secure_boot.h> 905 #define CONFIG_CMD_BLOB 906 #undef CONFIG_CMD_USB 907 #endif 908 909 #endif /* __T2080RDB_H */ 910