1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_T2080RDB 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 #define CONFIG_MMC 17 #define CONFIG_USB_EHCI 18 #define CONFIG_FSL_SATA_V2 19 20 /* High Level Configuration Options */ 21 #define CONFIG_BOOKE 22 #define CONFIG_E500 /* BOOKE e500 family */ 23 #define CONFIG_E500MC /* BOOKE e500mc family */ 24 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 25 #define CONFIG_MP /* support multiple processors */ 26 #define CONFIG_ENABLE_36BIT_PHYS 27 28 #ifdef CONFIG_PHYS_64BIT 29 #define CONFIG_ADDR_MAP 1 30 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 31 #endif 32 33 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 34 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 35 #define CONFIG_FSL_IFC /* Enable IFC Support */ 36 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 37 #define CONFIG_FSL_LAW /* Use common FSL init code */ 38 #define CONFIG_ENV_OVERWRITE 39 40 #ifdef CONFIG_RAMBOOT_PBL 41 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 42 43 #define CONFIG_SPL_FLUSH_IMAGE 44 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 #define CONFIG_SYS_TEXT_BASE 0x00201000 47 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 48 #define CONFIG_SPL_PAD_TO 0x40000 49 #define CONFIG_SPL_MAX_SIZE 0x28000 50 #define RESET_VECTOR_OFFSET 0x27FFC 51 #define BOOT_PAGE_OFFSET 0x27000 52 #ifdef CONFIG_SPL_BUILD 53 #define CONFIG_SPL_SKIP_RELOCATE 54 #define CONFIG_SPL_COMMON_INIT_DDR 55 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 56 #define CONFIG_SYS_NO_FLASH 57 #endif 58 59 #ifdef CONFIG_NAND 60 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 61 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 62 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 63 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 64 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 65 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 66 #define CONFIG_SPL_NAND_BOOT 67 #endif 68 69 #ifdef CONFIG_SPIFLASH 70 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 71 #define CONFIG_SPL_SPI_FLASH_MINIMAL 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 76 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 77 #ifndef CONFIG_SPL_BUILD 78 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 79 #endif 80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 81 #define CONFIG_SPL_SPI_BOOT 82 #endif 83 84 #ifdef CONFIG_SDCARD 85 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 86 #define CONFIG_SPL_MMC_MINIMAL 87 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 88 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 89 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 90 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 91 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 92 #ifndef CONFIG_SPL_BUILD 93 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 94 #endif 95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 96 #define CONFIG_SPL_MMC_BOOT 97 #endif 98 99 #endif /* CONFIG_RAMBOOT_PBL */ 100 101 #define CONFIG_SRIO_PCIE_BOOT_MASTER 102 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 103 /* Set 1M boot space */ 104 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 105 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 106 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 107 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 108 #define CONFIG_SYS_NO_FLASH 109 #endif 110 111 #ifndef CONFIG_SYS_TEXT_BASE 112 #define CONFIG_SYS_TEXT_BASE 0xeff40000 113 #endif 114 115 #ifndef CONFIG_RESET_VECTOR_ADDRESS 116 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 117 #endif 118 119 /* 120 * These can be toggled for performance analysis, otherwise use default. 121 */ 122 #define CONFIG_SYS_CACHE_STASHING 123 #define CONFIG_BTB /* toggle branch predition */ 124 #define CONFIG_DDR_ECC 125 #ifdef CONFIG_DDR_ECC 126 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 127 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 128 #endif 129 130 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 131 #define CONFIG_SYS_MEMTEST_END 0x00400000 132 #define CONFIG_SYS_ALT_MEMTEST 133 134 #ifndef CONFIG_SYS_NO_FLASH 135 #define CONFIG_FLASH_CFI_DRIVER 136 #define CONFIG_SYS_FLASH_CFI 137 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 138 #endif 139 140 #if defined(CONFIG_SPIFLASH) 141 #define CONFIG_SYS_EXTRA_ENV_RELOC 142 #define CONFIG_ENV_IS_IN_SPI_FLASH 143 #define CONFIG_ENV_SPI_BUS 0 144 #define CONFIG_ENV_SPI_CS 0 145 #define CONFIG_ENV_SPI_MAX_HZ 10000000 146 #define CONFIG_ENV_SPI_MODE 0 147 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 148 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 149 #define CONFIG_ENV_SECT_SIZE 0x10000 150 #elif defined(CONFIG_SDCARD) 151 #define CONFIG_SYS_EXTRA_ENV_RELOC 152 #define CONFIG_ENV_IS_IN_MMC 153 #define CONFIG_SYS_MMC_ENV_DEV 0 154 #define CONFIG_ENV_SIZE 0x2000 155 #define CONFIG_ENV_OFFSET (512 * 0x800) 156 #elif defined(CONFIG_NAND) 157 #define CONFIG_SYS_EXTRA_ENV_RELOC 158 #define CONFIG_ENV_IS_IN_NAND 159 #define CONFIG_ENV_SIZE 0x2000 160 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 161 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 162 #define CONFIG_ENV_IS_IN_REMOTE 163 #define CONFIG_ENV_ADDR 0xffe20000 164 #define CONFIG_ENV_SIZE 0x2000 165 #elif defined(CONFIG_ENV_IS_NOWHERE) 166 #define CONFIG_ENV_SIZE 0x2000 167 #else 168 #define CONFIG_ENV_IS_IN_FLASH 169 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 170 #define CONFIG_ENV_SIZE 0x2000 171 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 172 #endif 173 174 #ifndef __ASSEMBLY__ 175 unsigned long get_board_sys_clk(void); 176 unsigned long get_board_ddr_clk(void); 177 #endif 178 179 #define CONFIG_SYS_CLK_FREQ 66660000 180 #define CONFIG_DDR_CLK_FREQ 133330000 181 182 /* 183 * Config the L3 Cache as L3 SRAM 184 */ 185 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 186 #define CONFIG_SYS_L3_SIZE (512 << 10) 187 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 188 #ifdef CONFIG_RAMBOOT_PBL 189 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 190 #endif 191 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 192 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 193 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 194 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 195 196 #define CONFIG_SYS_DCSRBAR 0xf0000000 197 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 198 199 /* EEPROM */ 200 #define CONFIG_ID_EEPROM 201 #define CONFIG_SYS_I2C_EEPROM_NXID 202 #define CONFIG_SYS_EEPROM_BUS_NUM 0 203 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 204 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 205 206 /* 207 * DDR Setup 208 */ 209 #define CONFIG_VERY_BIG_RAM 210 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 211 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 212 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 213 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 214 #define CONFIG_DDR_SPD 215 #define CONFIG_SYS_FSL_DDR3 216 #undef CONFIG_FSL_DDR_INTERACTIVE 217 #define CONFIG_SYS_SPD_BUS_NUM 0 218 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 219 #define SPD_EEPROM_ADDRESS1 0x51 220 #define SPD_EEPROM_ADDRESS2 0x52 221 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 222 #define CTRL_INTLV_PREFERED cacheline 223 224 /* 225 * IFC Definitions 226 */ 227 #define CONFIG_SYS_FLASH_BASE 0xe8000000 228 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 229 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 230 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 231 CSPR_PORT_SIZE_16 | \ 232 CSPR_MSEL_NOR | \ 233 CSPR_V) 234 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 235 236 /* NOR Flash Timing Params */ 237 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 238 239 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 240 FTIM0_NOR_TEADC(0x5) | \ 241 FTIM0_NOR_TEAHC(0x5)) 242 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 243 FTIM1_NOR_TRAD_NOR(0x1A) |\ 244 FTIM1_NOR_TSEQRAD_NOR(0x13)) 245 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 246 FTIM2_NOR_TCH(0x4) | \ 247 FTIM2_NOR_TWPH(0x0E) | \ 248 FTIM2_NOR_TWP(0x1c)) 249 #define CONFIG_SYS_NOR_FTIM3 0x0 250 251 #define CONFIG_SYS_FLASH_QUIET_TEST 252 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 253 254 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 255 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 256 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 257 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 258 #define CONFIG_SYS_FLASH_EMPTY_INFO 259 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 260 261 /* CPLD on IFC */ 262 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 263 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 264 #define CONFIG_SYS_CSPR2_EXT (0xf) 265 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 266 | CSPR_PORT_SIZE_8 \ 267 | CSPR_MSEL_GPCM \ 268 | CSPR_V) 269 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 270 #define CONFIG_SYS_CSOR2 0x0 271 272 /* CPLD Timing parameters for IFC CS2 */ 273 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 274 FTIM0_GPCM_TEADC(0x0e) | \ 275 FTIM0_GPCM_TEAHC(0x0e)) 276 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 277 FTIM1_GPCM_TRAD(0x1f)) 278 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 279 FTIM2_GPCM_TCH(0x8) | \ 280 FTIM2_GPCM_TWP(0x1f)) 281 #define CONFIG_SYS_CS2_FTIM3 0x0 282 283 /* NAND Flash on IFC */ 284 #define CONFIG_NAND_FSL_IFC 285 #define CONFIG_SYS_NAND_BASE 0xff800000 286 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 287 288 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 289 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 290 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 291 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 292 | CSPR_V) 293 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 294 295 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 296 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 297 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 298 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 299 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 300 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 301 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 302 303 #define CONFIG_SYS_NAND_ONFI_DETECTION 304 305 /* ONFI NAND Flash mode0 Timing Params */ 306 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 307 FTIM0_NAND_TWP(0x18) | \ 308 FTIM0_NAND_TWCHT(0x07) | \ 309 FTIM0_NAND_TWH(0x0a)) 310 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 311 FTIM1_NAND_TWBE(0x39) | \ 312 FTIM1_NAND_TRR(0x0e) | \ 313 FTIM1_NAND_TRP(0x18)) 314 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 315 FTIM2_NAND_TREH(0x0a) | \ 316 FTIM2_NAND_TWHRE(0x1e)) 317 #define CONFIG_SYS_NAND_FTIM3 0x0 318 319 #define CONFIG_SYS_NAND_DDR_LAW 11 320 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 321 #define CONFIG_SYS_MAX_NAND_DEVICE 1 322 #define CONFIG_CMD_NAND 323 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 324 325 #if defined(CONFIG_NAND) 326 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 327 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 328 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 329 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 330 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 331 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 332 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 333 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 334 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 335 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 336 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 337 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 338 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 339 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 340 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 341 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 342 #else 343 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 344 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 345 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 352 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 353 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 354 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 355 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 356 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 357 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 358 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 359 #endif 360 361 #if defined(CONFIG_RAMBOOT_PBL) 362 #define CONFIG_SYS_RAMBOOT 363 #endif 364 365 #ifdef CONFIG_SPL_BUILD 366 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 367 #else 368 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 369 #endif 370 371 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 372 #define CONFIG_MISC_INIT_R 373 #define CONFIG_HWCONFIG 374 375 /* define to use L1 as initial stack */ 376 #define CONFIG_L1_INIT_RAM 377 #define CONFIG_SYS_INIT_RAM_LOCK 378 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 380 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 381 /* The assembler doesn't like typecast */ 382 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 383 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 384 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 385 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 386 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 387 GENERATED_GBL_DATA_SIZE) 388 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 389 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 390 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 391 392 /* 393 * Serial Port 394 */ 395 #define CONFIG_CONS_INDEX 1 396 #define CONFIG_SYS_NS16550_SERIAL 397 #define CONFIG_SYS_NS16550_REG_SIZE 1 398 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 399 #define CONFIG_SYS_BAUDRATE_TABLE \ 400 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 401 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 402 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 403 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 404 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 405 406 /* 407 * I2C 408 */ 409 #define CONFIG_SYS_I2C 410 #define CONFIG_SYS_I2C_FSL 411 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 412 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 413 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 414 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 415 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 416 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 417 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 418 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 419 #define CONFIG_SYS_FSL_I2C_SPEED 100000 420 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 421 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 422 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 423 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 424 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 425 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 426 #define I2C_MUX_CH_DEFAULT 0x8 427 428 #define I2C_MUX_CH_VOL_MONITOR 0xa 429 430 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 431 #ifndef CONFIG_SPL_BUILD 432 #define CONFIG_VID 433 #endif 434 #define CONFIG_VOL_MONITOR_IR36021_SET 435 #define CONFIG_VOL_MONITOR_IR36021_READ 436 /* The lowest and highest voltage allowed for T208xRDB */ 437 #define VDD_MV_MIN 819 438 #define VDD_MV_MAX 1212 439 440 /* 441 * RapidIO 442 */ 443 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 444 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 445 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 446 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 447 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 448 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 449 /* 450 * for slave u-boot IMAGE instored in master memory space, 451 * PHYS must be aligned based on the SIZE 452 */ 453 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 454 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 455 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 456 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 457 /* 458 * for slave UCODE and ENV instored in master memory space, 459 * PHYS must be aligned based on the SIZE 460 */ 461 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 462 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 463 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 464 465 /* slave core release by master*/ 466 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 467 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 468 469 /* 470 * SRIO_PCIE_BOOT - SLAVE 471 */ 472 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 473 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 474 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 475 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 476 #endif 477 478 /* 479 * eSPI - Enhanced SPI 480 */ 481 #ifdef CONFIG_SPI_FLASH 482 #define CONFIG_SPI_FLASH_BAR 483 #define CONFIG_SF_DEFAULT_SPEED 10000000 484 #define CONFIG_SF_DEFAULT_MODE 0 485 #endif 486 487 /* 488 * General PCI 489 * Memory space is mapped 1-1, but I/O space must start from 0. 490 */ 491 #define CONFIG_PCIE1 /* PCIE controller 1 */ 492 #define CONFIG_PCIE2 /* PCIE controller 2 */ 493 #define CONFIG_PCIE3 /* PCIE controller 3 */ 494 #define CONFIG_PCIE4 /* PCIE controller 4 */ 495 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 496 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 497 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 498 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 499 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 500 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 501 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 502 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 503 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 504 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 505 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 506 507 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 508 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 509 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 510 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 511 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 512 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 513 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 514 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 515 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 516 517 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 518 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 519 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 520 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 521 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 522 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 523 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 524 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 525 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 526 527 /* controller 4, Base address 203000 */ 528 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 529 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 530 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 531 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 532 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 533 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 534 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 535 536 #ifdef CONFIG_PCI 537 #define CONFIG_PCI_INDIRECT_BRIDGE 538 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 539 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 540 #define CONFIG_DOS_PARTITION 541 #endif 542 543 /* Qman/Bman */ 544 #ifndef CONFIG_NOBQFMAN 545 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 546 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 547 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 548 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 549 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 550 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 551 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 552 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 553 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 554 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 555 CONFIG_SYS_BMAN_CENA_SIZE) 556 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 557 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 558 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 559 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 560 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 561 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 562 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 563 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 564 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 565 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 566 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 567 CONFIG_SYS_QMAN_CENA_SIZE) 568 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 569 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 570 571 #define CONFIG_SYS_DPAA_FMAN 572 #define CONFIG_SYS_DPAA_PME 573 #define CONFIG_SYS_PMAN 574 #define CONFIG_SYS_DPAA_DCE 575 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 576 #define CONFIG_SYS_INTERLAKEN 577 578 /* Default address of microcode for the Linux Fman driver */ 579 #if defined(CONFIG_SPIFLASH) 580 /* 581 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 582 * env, so we got 0x110000. 583 */ 584 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 585 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 586 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 587 #define CONFIG_CORTINA_FW_ADDR 0x120000 588 589 #elif defined(CONFIG_SDCARD) 590 /* 591 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 592 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 593 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 594 */ 595 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 596 #define CONFIG_SYS_CORTINA_FW_IN_MMC 597 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 598 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 599 600 #elif defined(CONFIG_NAND) 601 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 602 #define CONFIG_SYS_CORTINA_FW_IN_NAND 603 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 604 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 605 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 606 /* 607 * Slave has no ucode locally, it can fetch this from remote. When implementing 608 * in two corenet boards, slave's ucode could be stored in master's memory 609 * space, the address can be mapped from slave TLB->slave LAW-> 610 * slave SRIO or PCIE outbound window->master inbound window-> 611 * master LAW->the ucode address in master's memory space. 612 */ 613 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 614 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 615 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 616 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 617 #else 618 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 619 #define CONFIG_SYS_CORTINA_FW_IN_NOR 620 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 621 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 622 #endif 623 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 624 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 625 #endif /* CONFIG_NOBQFMAN */ 626 627 #ifdef CONFIG_SYS_DPAA_FMAN 628 #define CONFIG_FMAN_ENET 629 #define CONFIG_PHYLIB_10G 630 #define CONFIG_PHY_AQUANTIA 631 #define CONFIG_PHY_CORTINA 632 #define CONFIG_PHY_REALTEK 633 #define CONFIG_CORTINA_FW_LENGTH 0x40000 634 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 635 #define RGMII_PHY2_ADDR 0x02 636 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 637 #define CORTINA_PHY_ADDR2 0x0d 638 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 639 #define FM1_10GEC4_PHY_ADDR 0x01 640 #endif 641 642 #ifdef CONFIG_FMAN_ENET 643 #define CONFIG_MII /* MII PHY management */ 644 #define CONFIG_ETHPRIME "FM1@DTSEC3" 645 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 646 #endif 647 648 /* 649 * SATA 650 */ 651 #ifdef CONFIG_FSL_SATA_V2 652 #define CONFIG_LIBATA 653 #define CONFIG_FSL_SATA 654 #define CONFIG_SYS_SATA_MAX_DEVICE 2 655 #define CONFIG_SATA1 656 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 657 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 658 #define CONFIG_SATA2 659 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 660 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 661 #define CONFIG_LBA48 662 #define CONFIG_CMD_SATA 663 #define CONFIG_DOS_PARTITION 664 #endif 665 666 /* 667 * USB 668 */ 669 #ifdef CONFIG_USB_EHCI 670 #define CONFIG_USB_EHCI_FSL 671 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 672 #define CONFIG_HAS_FSL_DR_USB 673 #endif 674 675 /* 676 * SDHC 677 */ 678 #ifdef CONFIG_MMC 679 #define CONFIG_FSL_ESDHC 680 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 681 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 682 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 683 #define CONFIG_GENERIC_MMC 684 #define CONFIG_DOS_PARTITION 685 #endif 686 687 /* 688 * Dynamic MTD Partition support with mtdparts 689 */ 690 #ifndef CONFIG_SYS_NO_FLASH 691 #define CONFIG_MTD_DEVICE 692 #define CONFIG_MTD_PARTITIONS 693 #define CONFIG_CMD_MTDPARTS 694 #define CONFIG_FLASH_CFI_MTD 695 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 696 "spi0=spife110000.1" 697 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 698 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 699 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 700 "1m(uboot),5m(kernel),128k(dtb),-(user)" 701 #endif 702 703 /* 704 * Environment 705 */ 706 707 /* 708 * Command line configuration. 709 */ 710 #define CONFIG_CMD_ERRATA 711 #define CONFIG_CMD_REGINFO 712 713 #ifdef CONFIG_PCI 714 #define CONFIG_CMD_PCI 715 #endif 716 717 /* Hash command with SHA acceleration supported in hardware */ 718 #ifdef CONFIG_FSL_CAAM 719 #define CONFIG_CMD_HASH 720 #define CONFIG_SHA_HW_ACCEL 721 #endif 722 723 /* 724 * Miscellaneous configurable options 725 */ 726 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 727 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 728 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 729 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 730 #ifdef CONFIG_CMD_KGDB 731 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 732 #else 733 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 734 #endif 735 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 736 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 737 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 738 739 /* 740 * For booting Linux, the board info and command line data 741 * have to be in the first 64 MB of memory, since this is 742 * the maximum mapped by the Linux kernel during initialization. 743 */ 744 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 745 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 746 747 #ifdef CONFIG_CMD_KGDB 748 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 749 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 750 #endif 751 752 /* 753 * Environment Configuration 754 */ 755 #define CONFIG_ROOTPATH "/opt/nfsroot" 756 #define CONFIG_BOOTFILE "uImage" 757 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 758 759 /* default location for tftp and bootm */ 760 #define CONFIG_LOADADDR 1000000 761 #define CONFIG_BAUDRATE 115200 762 #define __USB_PHY_TYPE utmi 763 764 #define CONFIG_EXTRA_ENV_SETTINGS \ 765 "hwconfig=fsl_ddr:" \ 766 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 767 "bank_intlv=auto;" \ 768 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 769 "netdev=eth0\0" \ 770 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 771 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 772 "tftpflash=tftpboot $loadaddr $uboot && " \ 773 "protect off $ubootaddr +$filesize && " \ 774 "erase $ubootaddr +$filesize && " \ 775 "cp.b $loadaddr $ubootaddr $filesize && " \ 776 "protect on $ubootaddr +$filesize && " \ 777 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 778 "consoledev=ttyS0\0" \ 779 "ramdiskaddr=2000000\0" \ 780 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 781 "fdtaddr=1e00000\0" \ 782 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 783 "bdev=sda3\0" 784 785 /* 786 * For emulation this causes u-boot to jump to the start of the 787 * proof point app code automatically 788 */ 789 #define CONFIG_PROOF_POINTS \ 790 "setenv bootargs root=/dev/$bdev rw " \ 791 "console=$consoledev,$baudrate $othbootargs;" \ 792 "cpu 1 release 0x29000000 - - -;" \ 793 "cpu 2 release 0x29000000 - - -;" \ 794 "cpu 3 release 0x29000000 - - -;" \ 795 "cpu 4 release 0x29000000 - - -;" \ 796 "cpu 5 release 0x29000000 - - -;" \ 797 "cpu 6 release 0x29000000 - - -;" \ 798 "cpu 7 release 0x29000000 - - -;" \ 799 "go 0x29000000" 800 801 #define CONFIG_HVBOOT \ 802 "setenv bootargs config-addr=0x60000000; " \ 803 "bootm 0x01000000 - 0x00f00000" 804 805 #define CONFIG_ALU \ 806 "setenv bootargs root=/dev/$bdev rw " \ 807 "console=$consoledev,$baudrate $othbootargs;" \ 808 "cpu 1 release 0x01000000 - - -;" \ 809 "cpu 2 release 0x01000000 - - -;" \ 810 "cpu 3 release 0x01000000 - - -;" \ 811 "cpu 4 release 0x01000000 - - -;" \ 812 "cpu 5 release 0x01000000 - - -;" \ 813 "cpu 6 release 0x01000000 - - -;" \ 814 "cpu 7 release 0x01000000 - - -;" \ 815 "go 0x01000000" 816 817 #define CONFIG_LINUX \ 818 "setenv bootargs root=/dev/ram rw " \ 819 "console=$consoledev,$baudrate $othbootargs;" \ 820 "setenv ramdiskaddr 0x02000000;" \ 821 "setenv fdtaddr 0x00c00000;" \ 822 "setenv loadaddr 0x1000000;" \ 823 "bootm $loadaddr $ramdiskaddr $fdtaddr" 824 825 #define CONFIG_HDBOOT \ 826 "setenv bootargs root=/dev/$bdev rw " \ 827 "console=$consoledev,$baudrate $othbootargs;" \ 828 "tftp $loadaddr $bootfile;" \ 829 "tftp $fdtaddr $fdtfile;" \ 830 "bootm $loadaddr - $fdtaddr" 831 832 #define CONFIG_NFSBOOTCOMMAND \ 833 "setenv bootargs root=/dev/nfs rw " \ 834 "nfsroot=$serverip:$rootpath " \ 835 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 836 "console=$consoledev,$baudrate $othbootargs;" \ 837 "tftp $loadaddr $bootfile;" \ 838 "tftp $fdtaddr $fdtfile;" \ 839 "bootm $loadaddr - $fdtaddr" 840 841 #define CONFIG_RAMBOOTCOMMAND \ 842 "setenv bootargs root=/dev/ram rw " \ 843 "console=$consoledev,$baudrate $othbootargs;" \ 844 "tftp $ramdiskaddr $ramdiskfile;" \ 845 "tftp $loadaddr $bootfile;" \ 846 "tftp $fdtaddr $fdtfile;" \ 847 "bootm $loadaddr $ramdiskaddr $fdtaddr" 848 849 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 850 851 #include <asm/fsl_secure_boot.h> 852 853 #endif /* __T2080RDB_H */ 854