1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T2080 RDB/PCIe board configuration file 8 */ 9 10 #ifndef __T2080RDB_H 11 #define __T2080RDB_H 12 13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 14 #define CONFIG_FSL_SATA_V2 15 16 /* High Level Configuration Options */ 17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 18 #define CONFIG_ENABLE_36BIT_PHYS 19 20 #ifdef CONFIG_PHYS_64BIT 21 #define CONFIG_ADDR_MAP 1 22 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 23 #endif 24 25 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 26 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 27 #define CONFIG_ENV_OVERWRITE 28 29 #ifdef CONFIG_RAMBOOT_PBL 30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 31 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 34 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 35 #define CONFIG_SPL_PAD_TO 0x40000 36 #define CONFIG_SPL_MAX_SIZE 0x28000 37 #define RESET_VECTOR_OFFSET 0x27FFC 38 #define BOOT_PAGE_OFFSET 0x27000 39 #ifdef CONFIG_SPL_BUILD 40 #define CONFIG_SPL_SKIP_RELOCATE 41 #define CONFIG_SPL_COMMON_INIT_DDR 42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 43 #endif 44 45 #ifdef CONFIG_NAND 46 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 47 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 48 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 49 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 50 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 52 #define CONFIG_SPL_NAND_BOOT 53 #endif 54 55 #ifdef CONFIG_SPIFLASH 56 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 57 #define CONFIG_SPL_SPI_FLASH_MINIMAL 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 62 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 63 #ifndef CONFIG_SPL_BUILD 64 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 65 #endif 66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 67 #define CONFIG_SPL_SPI_BOOT 68 #endif 69 70 #ifdef CONFIG_SDCARD 71 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 72 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 73 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 74 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 75 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 76 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 77 #ifndef CONFIG_SPL_BUILD 78 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 79 #endif 80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 81 #define CONFIG_SPL_MMC_BOOT 82 #endif 83 84 #endif /* CONFIG_RAMBOOT_PBL */ 85 86 #define CONFIG_SRIO_PCIE_BOOT_MASTER 87 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 88 /* Set 1M boot space */ 89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 90 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 91 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 92 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 93 #endif 94 95 #ifndef CONFIG_RESET_VECTOR_ADDRESS 96 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 97 #endif 98 99 /* 100 * These can be toggled for performance analysis, otherwise use default. 101 */ 102 #define CONFIG_SYS_CACHE_STASHING 103 #define CONFIG_BTB /* toggle branch predition */ 104 #define CONFIG_DDR_ECC 105 #ifdef CONFIG_DDR_ECC 106 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 107 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 108 #endif 109 110 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 111 #define CONFIG_SYS_MEMTEST_END 0x00400000 112 113 #ifdef CONFIG_MTD_NOR_FLASH 114 #define CONFIG_FLASH_CFI_DRIVER 115 #define CONFIG_SYS_FLASH_CFI 116 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 117 #endif 118 119 #if defined(CONFIG_SPIFLASH) 120 #define CONFIG_SYS_EXTRA_ENV_RELOC 121 #define CONFIG_ENV_SPI_BUS 0 122 #define CONFIG_ENV_SPI_CS 0 123 #define CONFIG_ENV_SPI_MAX_HZ 10000000 124 #define CONFIG_ENV_SPI_MODE 0 125 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 126 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 127 #define CONFIG_ENV_SECT_SIZE 0x10000 128 #elif defined(CONFIG_SDCARD) 129 #define CONFIG_SYS_EXTRA_ENV_RELOC 130 #define CONFIG_SYS_MMC_ENV_DEV 0 131 #define CONFIG_ENV_SIZE 0x2000 132 #define CONFIG_ENV_OFFSET (512 * 0x800) 133 #elif defined(CONFIG_NAND) 134 #define CONFIG_SYS_EXTRA_ENV_RELOC 135 #define CONFIG_ENV_SIZE 0x2000 136 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 137 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 138 #define CONFIG_ENV_ADDR 0xffe20000 139 #define CONFIG_ENV_SIZE 0x2000 140 #elif defined(CONFIG_ENV_IS_NOWHERE) 141 #define CONFIG_ENV_SIZE 0x2000 142 #else 143 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 144 #define CONFIG_ENV_SIZE 0x2000 145 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 146 #endif 147 148 #ifndef __ASSEMBLY__ 149 unsigned long get_board_sys_clk(void); 150 unsigned long get_board_ddr_clk(void); 151 #endif 152 153 #define CONFIG_SYS_CLK_FREQ 66660000 154 #define CONFIG_DDR_CLK_FREQ 133330000 155 156 /* 157 * Config the L3 Cache as L3 SRAM 158 */ 159 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 160 #define CONFIG_SYS_L3_SIZE (512 << 10) 161 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 162 #ifdef CONFIG_RAMBOOT_PBL 163 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 164 #endif 165 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 166 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 167 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 168 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 169 170 #define CONFIG_SYS_DCSRBAR 0xf0000000 171 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 172 173 /* EEPROM */ 174 #define CONFIG_ID_EEPROM 175 #define CONFIG_SYS_I2C_EEPROM_NXID 176 #define CONFIG_SYS_EEPROM_BUS_NUM 0 177 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 178 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 179 180 /* 181 * DDR Setup 182 */ 183 #define CONFIG_VERY_BIG_RAM 184 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 185 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 186 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 187 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 188 #define CONFIG_DDR_SPD 189 #undef CONFIG_FSL_DDR_INTERACTIVE 190 #define CONFIG_SYS_SPD_BUS_NUM 0 191 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 192 #define SPD_EEPROM_ADDRESS1 0x51 193 #define SPD_EEPROM_ADDRESS2 0x52 194 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 195 #define CTRL_INTLV_PREFERED cacheline 196 197 /* 198 * IFC Definitions 199 */ 200 #define CONFIG_SYS_FLASH_BASE 0xe8000000 201 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 202 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 203 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 204 CSPR_PORT_SIZE_16 | \ 205 CSPR_MSEL_NOR | \ 206 CSPR_V) 207 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 208 209 /* NOR Flash Timing Params */ 210 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 211 212 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 213 FTIM0_NOR_TEADC(0x5) | \ 214 FTIM0_NOR_TEAHC(0x5)) 215 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 216 FTIM1_NOR_TRAD_NOR(0x1A) |\ 217 FTIM1_NOR_TSEQRAD_NOR(0x13)) 218 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 219 FTIM2_NOR_TCH(0x4) | \ 220 FTIM2_NOR_TWPH(0x0E) | \ 221 FTIM2_NOR_TWP(0x1c)) 222 #define CONFIG_SYS_NOR_FTIM3 0x0 223 224 #define CONFIG_SYS_FLASH_QUIET_TEST 225 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 226 227 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 228 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 229 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 230 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 231 #define CONFIG_SYS_FLASH_EMPTY_INFO 232 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 233 234 /* CPLD on IFC */ 235 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 236 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 237 #define CONFIG_SYS_CSPR2_EXT (0xf) 238 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 239 | CSPR_PORT_SIZE_8 \ 240 | CSPR_MSEL_GPCM \ 241 | CSPR_V) 242 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 243 #define CONFIG_SYS_CSOR2 0x0 244 245 /* CPLD Timing parameters for IFC CS2 */ 246 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 247 FTIM0_GPCM_TEADC(0x0e) | \ 248 FTIM0_GPCM_TEAHC(0x0e)) 249 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 250 FTIM1_GPCM_TRAD(0x1f)) 251 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 252 FTIM2_GPCM_TCH(0x8) | \ 253 FTIM2_GPCM_TWP(0x1f)) 254 #define CONFIG_SYS_CS2_FTIM3 0x0 255 256 /* NAND Flash on IFC */ 257 #define CONFIG_NAND_FSL_IFC 258 #define CONFIG_SYS_NAND_BASE 0xff800000 259 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 260 261 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 262 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 263 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 264 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 265 | CSPR_V) 266 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 267 268 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 269 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 270 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 271 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 272 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 273 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 274 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 275 276 #define CONFIG_SYS_NAND_ONFI_DETECTION 277 278 /* ONFI NAND Flash mode0 Timing Params */ 279 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 280 FTIM0_NAND_TWP(0x18) | \ 281 FTIM0_NAND_TWCHT(0x07) | \ 282 FTIM0_NAND_TWH(0x0a)) 283 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 284 FTIM1_NAND_TWBE(0x39) | \ 285 FTIM1_NAND_TRR(0x0e) | \ 286 FTIM1_NAND_TRP(0x18)) 287 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 288 FTIM2_NAND_TREH(0x0a) | \ 289 FTIM2_NAND_TWHRE(0x1e)) 290 #define CONFIG_SYS_NAND_FTIM3 0x0 291 292 #define CONFIG_SYS_NAND_DDR_LAW 11 293 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 294 #define CONFIG_SYS_MAX_NAND_DEVICE 1 295 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 296 297 #if defined(CONFIG_NAND) 298 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 299 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 300 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 301 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 302 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 303 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 304 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 305 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 306 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 307 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 308 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 309 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 310 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 311 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 312 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 313 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 314 #else 315 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 316 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 317 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 318 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 319 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 320 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 321 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 322 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 323 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 324 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 325 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 326 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 327 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 328 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 329 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 330 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 331 #endif 332 333 #if defined(CONFIG_RAMBOOT_PBL) 334 #define CONFIG_SYS_RAMBOOT 335 #endif 336 337 #ifdef CONFIG_SPL_BUILD 338 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 339 #else 340 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 341 #endif 342 343 #define CONFIG_MISC_INIT_R 344 #define CONFIG_HWCONFIG 345 346 /* define to use L1 as initial stack */ 347 #define CONFIG_L1_INIT_RAM 348 #define CONFIG_SYS_INIT_RAM_LOCK 349 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 350 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 351 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 352 /* The assembler doesn't like typecast */ 353 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 354 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 355 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 356 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 357 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 358 GENERATED_GBL_DATA_SIZE) 359 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 360 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 361 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 362 363 /* 364 * Serial Port 365 */ 366 #define CONFIG_SYS_NS16550_SERIAL 367 #define CONFIG_SYS_NS16550_REG_SIZE 1 368 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 369 #define CONFIG_SYS_BAUDRATE_TABLE \ 370 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 371 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 372 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 373 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 374 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 375 376 /* 377 * I2C 378 */ 379 #define CONFIG_SYS_I2C 380 #define CONFIG_SYS_I2C_FSL 381 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 382 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 383 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 384 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 385 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 386 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 387 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 388 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 389 #define CONFIG_SYS_FSL_I2C_SPEED 100000 390 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 391 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 392 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 393 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 394 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 395 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 396 #define I2C_MUX_CH_DEFAULT 0x8 397 398 #define I2C_MUX_CH_VOL_MONITOR 0xa 399 400 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 401 #ifndef CONFIG_SPL_BUILD 402 #define CONFIG_VID 403 #endif 404 #define CONFIG_VOL_MONITOR_IR36021_SET 405 #define CONFIG_VOL_MONITOR_IR36021_READ 406 /* The lowest and highest voltage allowed for T208xRDB */ 407 #define VDD_MV_MIN 819 408 #define VDD_MV_MAX 1212 409 410 /* 411 * RapidIO 412 */ 413 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 414 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 415 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 416 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 417 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 418 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 419 /* 420 * for slave u-boot IMAGE instored in master memory space, 421 * PHYS must be aligned based on the SIZE 422 */ 423 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 424 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 425 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 426 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 427 /* 428 * for slave UCODE and ENV instored in master memory space, 429 * PHYS must be aligned based on the SIZE 430 */ 431 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 432 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 433 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 434 435 /* slave core release by master*/ 436 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 437 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 438 439 /* 440 * SRIO_PCIE_BOOT - SLAVE 441 */ 442 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 443 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 444 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 445 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 446 #endif 447 448 /* 449 * eSPI - Enhanced SPI 450 */ 451 #ifdef CONFIG_SPI_FLASH 452 #define CONFIG_SPI_FLASH_BAR 453 #define CONFIG_SF_DEFAULT_SPEED 10000000 454 #define CONFIG_SF_DEFAULT_MODE 0 455 #endif 456 457 /* 458 * General PCI 459 * Memory space is mapped 1-1, but I/O space must start from 0. 460 */ 461 #define CONFIG_PCIE1 /* PCIE controller 1 */ 462 #define CONFIG_PCIE2 /* PCIE controller 2 */ 463 #define CONFIG_PCIE3 /* PCIE controller 3 */ 464 #define CONFIG_PCIE4 /* PCIE controller 4 */ 465 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 466 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 467 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 468 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 469 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 470 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 471 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 472 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 473 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 474 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 475 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 476 477 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 478 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 479 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 480 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 481 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 482 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 483 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 484 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 485 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 486 487 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 488 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 489 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 490 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 491 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 492 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 493 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 494 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 495 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 496 497 /* controller 4, Base address 203000 */ 498 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 499 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 500 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 501 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 502 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 503 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 504 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 505 506 #ifdef CONFIG_PCI 507 #define CONFIG_PCI_INDIRECT_BRIDGE 508 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 509 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 510 #endif 511 512 /* Qman/Bman */ 513 #ifndef CONFIG_NOBQFMAN 514 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 515 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 516 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 517 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 518 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 519 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 520 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 521 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 522 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 523 CONFIG_SYS_BMAN_CENA_SIZE) 524 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 525 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 526 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 527 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 528 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 529 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 530 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 531 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 532 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 533 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 534 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 535 CONFIG_SYS_QMAN_CENA_SIZE) 536 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 537 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 538 539 #define CONFIG_SYS_DPAA_FMAN 540 #define CONFIG_SYS_DPAA_PME 541 #define CONFIG_SYS_PMAN 542 #define CONFIG_SYS_DPAA_DCE 543 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 544 #define CONFIG_SYS_INTERLAKEN 545 546 /* Default address of microcode for the Linux Fman driver */ 547 #if defined(CONFIG_SPIFLASH) 548 /* 549 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 550 * env, so we got 0x110000. 551 */ 552 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 553 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 554 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 555 #define CONFIG_CORTINA_FW_ADDR 0x120000 556 557 #elif defined(CONFIG_SDCARD) 558 /* 559 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 560 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 561 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 562 */ 563 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 564 #define CONFIG_SYS_CORTINA_FW_IN_MMC 565 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 566 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 567 568 #elif defined(CONFIG_NAND) 569 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 570 #define CONFIG_SYS_CORTINA_FW_IN_NAND 571 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 572 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 573 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 574 /* 575 * Slave has no ucode locally, it can fetch this from remote. When implementing 576 * in two corenet boards, slave's ucode could be stored in master's memory 577 * space, the address can be mapped from slave TLB->slave LAW-> 578 * slave SRIO or PCIE outbound window->master inbound window-> 579 * master LAW->the ucode address in master's memory space. 580 */ 581 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 582 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 583 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 584 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 585 #else 586 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 587 #define CONFIG_SYS_CORTINA_FW_IN_NOR 588 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 589 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 590 #endif 591 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 592 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 593 #endif /* CONFIG_NOBQFMAN */ 594 595 #ifdef CONFIG_SYS_DPAA_FMAN 596 #define CONFIG_FMAN_ENET 597 #define CONFIG_PHYLIB_10G 598 #define CONFIG_PHY_AQUANTIA 599 #define CONFIG_PHY_CORTINA 600 #define CONFIG_PHY_REALTEK 601 #define CONFIG_CORTINA_FW_LENGTH 0x40000 602 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 603 #define RGMII_PHY2_ADDR 0x02 604 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 605 #define CORTINA_PHY_ADDR2 0x0d 606 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 607 #define FM1_10GEC4_PHY_ADDR 0x01 608 #endif 609 610 #ifdef CONFIG_FMAN_ENET 611 #define CONFIG_MII /* MII PHY management */ 612 #define CONFIG_ETHPRIME "FM1@DTSEC3" 613 #endif 614 615 /* 616 * SATA 617 */ 618 #ifdef CONFIG_FSL_SATA_V2 619 #define CONFIG_SYS_SATA_MAX_DEVICE 2 620 #define CONFIG_SATA1 621 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 622 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 623 #define CONFIG_SATA2 624 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 625 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 626 #define CONFIG_LBA48 627 #endif 628 629 /* 630 * USB 631 */ 632 #ifdef CONFIG_USB_EHCI_HCD 633 #define CONFIG_USB_EHCI_FSL 634 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 635 #define CONFIG_HAS_FSL_DR_USB 636 #endif 637 638 /* 639 * SDHC 640 */ 641 #ifdef CONFIG_MMC 642 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 643 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 644 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 645 #endif 646 647 /* 648 * Dynamic MTD Partition support with mtdparts 649 */ 650 #ifdef CONFIG_MTD_NOR_FLASH 651 #define CONFIG_MTD_DEVICE 652 #define CONFIG_MTD_PARTITIONS 653 #define CONFIG_FLASH_CFI_MTD 654 #endif 655 656 /* 657 * Environment 658 */ 659 660 /* 661 * Miscellaneous configurable options 662 */ 663 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 664 665 /* 666 * For booting Linux, the board info and command line data 667 * have to be in the first 64 MB of memory, since this is 668 * the maximum mapped by the Linux kernel during initialization. 669 */ 670 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 671 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 672 673 #ifdef CONFIG_CMD_KGDB 674 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 675 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 676 #endif 677 678 /* 679 * Environment Configuration 680 */ 681 #define CONFIG_ROOTPATH "/opt/nfsroot" 682 #define CONFIG_BOOTFILE "uImage" 683 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 684 685 /* default location for tftp and bootm */ 686 #define CONFIG_LOADADDR 1000000 687 #define __USB_PHY_TYPE utmi 688 689 #define CONFIG_EXTRA_ENV_SETTINGS \ 690 "hwconfig=fsl_ddr:" \ 691 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 692 "bank_intlv=auto;" \ 693 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 694 "netdev=eth0\0" \ 695 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 696 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 697 "tftpflash=tftpboot $loadaddr $uboot && " \ 698 "protect off $ubootaddr +$filesize && " \ 699 "erase $ubootaddr +$filesize && " \ 700 "cp.b $loadaddr $ubootaddr $filesize && " \ 701 "protect on $ubootaddr +$filesize && " \ 702 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 703 "consoledev=ttyS0\0" \ 704 "ramdiskaddr=2000000\0" \ 705 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 706 "fdtaddr=1e00000\0" \ 707 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 708 "bdev=sda3\0" 709 710 /* 711 * For emulation this causes u-boot to jump to the start of the 712 * proof point app code automatically 713 */ 714 #define CONFIG_PROOF_POINTS \ 715 "setenv bootargs root=/dev/$bdev rw " \ 716 "console=$consoledev,$baudrate $othbootargs;" \ 717 "cpu 1 release 0x29000000 - - -;" \ 718 "cpu 2 release 0x29000000 - - -;" \ 719 "cpu 3 release 0x29000000 - - -;" \ 720 "cpu 4 release 0x29000000 - - -;" \ 721 "cpu 5 release 0x29000000 - - -;" \ 722 "cpu 6 release 0x29000000 - - -;" \ 723 "cpu 7 release 0x29000000 - - -;" \ 724 "go 0x29000000" 725 726 #define CONFIG_HVBOOT \ 727 "setenv bootargs config-addr=0x60000000; " \ 728 "bootm 0x01000000 - 0x00f00000" 729 730 #define CONFIG_ALU \ 731 "setenv bootargs root=/dev/$bdev rw " \ 732 "console=$consoledev,$baudrate $othbootargs;" \ 733 "cpu 1 release 0x01000000 - - -;" \ 734 "cpu 2 release 0x01000000 - - -;" \ 735 "cpu 3 release 0x01000000 - - -;" \ 736 "cpu 4 release 0x01000000 - - -;" \ 737 "cpu 5 release 0x01000000 - - -;" \ 738 "cpu 6 release 0x01000000 - - -;" \ 739 "cpu 7 release 0x01000000 - - -;" \ 740 "go 0x01000000" 741 742 #define CONFIG_LINUX \ 743 "setenv bootargs root=/dev/ram rw " \ 744 "console=$consoledev,$baudrate $othbootargs;" \ 745 "setenv ramdiskaddr 0x02000000;" \ 746 "setenv fdtaddr 0x00c00000;" \ 747 "setenv loadaddr 0x1000000;" \ 748 "bootm $loadaddr $ramdiskaddr $fdtaddr" 749 750 #define CONFIG_HDBOOT \ 751 "setenv bootargs root=/dev/$bdev rw " \ 752 "console=$consoledev,$baudrate $othbootargs;" \ 753 "tftp $loadaddr $bootfile;" \ 754 "tftp $fdtaddr $fdtfile;" \ 755 "bootm $loadaddr - $fdtaddr" 756 757 #define CONFIG_NFSBOOTCOMMAND \ 758 "setenv bootargs root=/dev/nfs rw " \ 759 "nfsroot=$serverip:$rootpath " \ 760 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 761 "console=$consoledev,$baudrate $othbootargs;" \ 762 "tftp $loadaddr $bootfile;" \ 763 "tftp $fdtaddr $fdtfile;" \ 764 "bootm $loadaddr - $fdtaddr" 765 766 #define CONFIG_RAMBOOTCOMMAND \ 767 "setenv bootargs root=/dev/ram rw " \ 768 "console=$consoledev,$baudrate $othbootargs;" \ 769 "tftp $ramdiskaddr $ramdiskfile;" \ 770 "tftp $loadaddr $bootfile;" \ 771 "tftp $fdtaddr $fdtfile;" \ 772 "bootm $loadaddr $ramdiskaddr $fdtaddr" 773 774 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 775 776 #include <asm/fsl_secure_boot.h> 777 778 #endif /* __T2080RDB_H */ 779