1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_T2080RDB 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 #define CONFIG_USB_EHCI 17 #define CONFIG_FSL_SATA_V2 18 19 /* High Level Configuration Options */ 20 #define CONFIG_BOOKE 21 #define CONFIG_E500 /* BOOKE e500 family */ 22 #define CONFIG_E500MC /* BOOKE e500mc family */ 23 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 24 #define CONFIG_MP /* support multiple processors */ 25 #define CONFIG_ENABLE_36BIT_PHYS 26 27 #ifdef CONFIG_PHYS_64BIT 28 #define CONFIG_ADDR_MAP 1 29 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 30 #endif 31 32 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 33 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 34 #define CONFIG_FSL_IFC /* Enable IFC Support */ 35 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 36 #define CONFIG_ENV_OVERWRITE 37 38 #ifdef CONFIG_RAMBOOT_PBL 39 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 40 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 #define CONFIG_SYS_TEXT_BASE 0x00201000 44 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 45 #define CONFIG_SPL_PAD_TO 0x40000 46 #define CONFIG_SPL_MAX_SIZE 0x28000 47 #define RESET_VECTOR_OFFSET 0x27FFC 48 #define BOOT_PAGE_OFFSET 0x27000 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SPL_SKIP_RELOCATE 51 #define CONFIG_SPL_COMMON_INIT_DDR 52 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 53 #define CONFIG_SYS_NO_FLASH 54 #endif 55 56 #ifdef CONFIG_NAND 57 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 58 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 59 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 60 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 62 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 63 #define CONFIG_SPL_NAND_BOOT 64 #endif 65 66 #ifdef CONFIG_SPIFLASH 67 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 68 #define CONFIG_SPL_SPI_FLASH_MINIMAL 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 73 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 74 #ifndef CONFIG_SPL_BUILD 75 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 76 #endif 77 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 78 #define CONFIG_SPL_SPI_BOOT 79 #endif 80 81 #ifdef CONFIG_SDCARD 82 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 83 #define CONFIG_SPL_MMC_MINIMAL 84 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 85 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 86 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 87 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 88 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 89 #ifndef CONFIG_SPL_BUILD 90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 91 #endif 92 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 93 #define CONFIG_SPL_MMC_BOOT 94 #endif 95 96 #endif /* CONFIG_RAMBOOT_PBL */ 97 98 #define CONFIG_SRIO_PCIE_BOOT_MASTER 99 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 100 /* Set 1M boot space */ 101 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 102 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 103 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 104 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 105 #define CONFIG_SYS_NO_FLASH 106 #endif 107 108 #ifndef CONFIG_SYS_TEXT_BASE 109 #define CONFIG_SYS_TEXT_BASE 0xeff40000 110 #endif 111 112 #ifndef CONFIG_RESET_VECTOR_ADDRESS 113 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 114 #endif 115 116 /* 117 * These can be toggled for performance analysis, otherwise use default. 118 */ 119 #define CONFIG_SYS_CACHE_STASHING 120 #define CONFIG_BTB /* toggle branch predition */ 121 #define CONFIG_DDR_ECC 122 #ifdef CONFIG_DDR_ECC 123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 124 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 125 #endif 126 127 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 128 #define CONFIG_SYS_MEMTEST_END 0x00400000 129 #define CONFIG_SYS_ALT_MEMTEST 130 131 #ifndef CONFIG_SYS_NO_FLASH 132 #define CONFIG_FLASH_CFI_DRIVER 133 #define CONFIG_SYS_FLASH_CFI 134 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 135 #endif 136 137 #if defined(CONFIG_SPIFLASH) 138 #define CONFIG_SYS_EXTRA_ENV_RELOC 139 #define CONFIG_ENV_IS_IN_SPI_FLASH 140 #define CONFIG_ENV_SPI_BUS 0 141 #define CONFIG_ENV_SPI_CS 0 142 #define CONFIG_ENV_SPI_MAX_HZ 10000000 143 #define CONFIG_ENV_SPI_MODE 0 144 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 145 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 146 #define CONFIG_ENV_SECT_SIZE 0x10000 147 #elif defined(CONFIG_SDCARD) 148 #define CONFIG_SYS_EXTRA_ENV_RELOC 149 #define CONFIG_ENV_IS_IN_MMC 150 #define CONFIG_SYS_MMC_ENV_DEV 0 151 #define CONFIG_ENV_SIZE 0x2000 152 #define CONFIG_ENV_OFFSET (512 * 0x800) 153 #elif defined(CONFIG_NAND) 154 #define CONFIG_SYS_EXTRA_ENV_RELOC 155 #define CONFIG_ENV_IS_IN_NAND 156 #define CONFIG_ENV_SIZE 0x2000 157 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 158 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 159 #define CONFIG_ENV_IS_IN_REMOTE 160 #define CONFIG_ENV_ADDR 0xffe20000 161 #define CONFIG_ENV_SIZE 0x2000 162 #elif defined(CONFIG_ENV_IS_NOWHERE) 163 #define CONFIG_ENV_SIZE 0x2000 164 #else 165 #define CONFIG_ENV_IS_IN_FLASH 166 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 167 #define CONFIG_ENV_SIZE 0x2000 168 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 169 #endif 170 171 #ifndef __ASSEMBLY__ 172 unsigned long get_board_sys_clk(void); 173 unsigned long get_board_ddr_clk(void); 174 #endif 175 176 #define CONFIG_SYS_CLK_FREQ 66660000 177 #define CONFIG_DDR_CLK_FREQ 133330000 178 179 /* 180 * Config the L3 Cache as L3 SRAM 181 */ 182 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 183 #define CONFIG_SYS_L3_SIZE (512 << 10) 184 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 185 #ifdef CONFIG_RAMBOOT_PBL 186 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 187 #endif 188 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 189 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 190 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 191 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 192 193 #define CONFIG_SYS_DCSRBAR 0xf0000000 194 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 195 196 /* EEPROM */ 197 #define CONFIG_ID_EEPROM 198 #define CONFIG_SYS_I2C_EEPROM_NXID 199 #define CONFIG_SYS_EEPROM_BUS_NUM 0 200 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 201 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 202 203 /* 204 * DDR Setup 205 */ 206 #define CONFIG_VERY_BIG_RAM 207 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 208 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 209 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 210 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 211 #define CONFIG_DDR_SPD 212 #define CONFIG_SYS_FSL_DDR3 213 #undef CONFIG_FSL_DDR_INTERACTIVE 214 #define CONFIG_SYS_SPD_BUS_NUM 0 215 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 216 #define SPD_EEPROM_ADDRESS1 0x51 217 #define SPD_EEPROM_ADDRESS2 0x52 218 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 219 #define CTRL_INTLV_PREFERED cacheline 220 221 /* 222 * IFC Definitions 223 */ 224 #define CONFIG_SYS_FLASH_BASE 0xe8000000 225 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 226 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 227 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 228 CSPR_PORT_SIZE_16 | \ 229 CSPR_MSEL_NOR | \ 230 CSPR_V) 231 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 232 233 /* NOR Flash Timing Params */ 234 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 235 236 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 237 FTIM0_NOR_TEADC(0x5) | \ 238 FTIM0_NOR_TEAHC(0x5)) 239 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 240 FTIM1_NOR_TRAD_NOR(0x1A) |\ 241 FTIM1_NOR_TSEQRAD_NOR(0x13)) 242 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 243 FTIM2_NOR_TCH(0x4) | \ 244 FTIM2_NOR_TWPH(0x0E) | \ 245 FTIM2_NOR_TWP(0x1c)) 246 #define CONFIG_SYS_NOR_FTIM3 0x0 247 248 #define CONFIG_SYS_FLASH_QUIET_TEST 249 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 250 251 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 252 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 253 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 254 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 255 #define CONFIG_SYS_FLASH_EMPTY_INFO 256 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 257 258 /* CPLD on IFC */ 259 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 260 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 261 #define CONFIG_SYS_CSPR2_EXT (0xf) 262 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 263 | CSPR_PORT_SIZE_8 \ 264 | CSPR_MSEL_GPCM \ 265 | CSPR_V) 266 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 267 #define CONFIG_SYS_CSOR2 0x0 268 269 /* CPLD Timing parameters for IFC CS2 */ 270 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 271 FTIM0_GPCM_TEADC(0x0e) | \ 272 FTIM0_GPCM_TEAHC(0x0e)) 273 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 274 FTIM1_GPCM_TRAD(0x1f)) 275 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 276 FTIM2_GPCM_TCH(0x8) | \ 277 FTIM2_GPCM_TWP(0x1f)) 278 #define CONFIG_SYS_CS2_FTIM3 0x0 279 280 /* NAND Flash on IFC */ 281 #define CONFIG_NAND_FSL_IFC 282 #define CONFIG_SYS_NAND_BASE 0xff800000 283 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 284 285 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 286 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 287 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 288 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 289 | CSPR_V) 290 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 291 292 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 293 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 294 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 295 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 296 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 297 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 298 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 299 300 #define CONFIG_SYS_NAND_ONFI_DETECTION 301 302 /* ONFI NAND Flash mode0 Timing Params */ 303 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 304 FTIM0_NAND_TWP(0x18) | \ 305 FTIM0_NAND_TWCHT(0x07) | \ 306 FTIM0_NAND_TWH(0x0a)) 307 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 308 FTIM1_NAND_TWBE(0x39) | \ 309 FTIM1_NAND_TRR(0x0e) | \ 310 FTIM1_NAND_TRP(0x18)) 311 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 312 FTIM2_NAND_TREH(0x0a) | \ 313 FTIM2_NAND_TWHRE(0x1e)) 314 #define CONFIG_SYS_NAND_FTIM3 0x0 315 316 #define CONFIG_SYS_NAND_DDR_LAW 11 317 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 318 #define CONFIG_SYS_MAX_NAND_DEVICE 1 319 #define CONFIG_CMD_NAND 320 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 321 322 #if defined(CONFIG_NAND) 323 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 324 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 325 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 326 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 327 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 328 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 329 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 330 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 331 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 332 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 333 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 334 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 335 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 336 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 337 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 338 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 339 #else 340 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 341 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 342 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 343 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 344 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 345 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 346 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 347 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 348 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 349 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 350 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 351 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 352 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 353 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 354 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 355 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 356 #endif 357 358 #if defined(CONFIG_RAMBOOT_PBL) 359 #define CONFIG_SYS_RAMBOOT 360 #endif 361 362 #ifdef CONFIG_SPL_BUILD 363 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 364 #else 365 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 366 #endif 367 368 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 369 #define CONFIG_MISC_INIT_R 370 #define CONFIG_HWCONFIG 371 372 /* define to use L1 as initial stack */ 373 #define CONFIG_L1_INIT_RAM 374 #define CONFIG_SYS_INIT_RAM_LOCK 375 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 376 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 377 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 378 /* The assembler doesn't like typecast */ 379 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 380 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 381 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 382 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 383 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 384 GENERATED_GBL_DATA_SIZE) 385 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 386 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 387 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 388 389 /* 390 * Serial Port 391 */ 392 #define CONFIG_CONS_INDEX 1 393 #define CONFIG_SYS_NS16550_SERIAL 394 #define CONFIG_SYS_NS16550_REG_SIZE 1 395 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 396 #define CONFIG_SYS_BAUDRATE_TABLE \ 397 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 398 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 399 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 400 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 401 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 402 403 /* 404 * I2C 405 */ 406 #define CONFIG_SYS_I2C 407 #define CONFIG_SYS_I2C_FSL 408 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 409 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 410 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 411 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 412 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 413 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 414 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 415 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 416 #define CONFIG_SYS_FSL_I2C_SPEED 100000 417 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 418 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 419 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 420 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 421 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 422 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 423 #define I2C_MUX_CH_DEFAULT 0x8 424 425 #define I2C_MUX_CH_VOL_MONITOR 0xa 426 427 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 428 #ifndef CONFIG_SPL_BUILD 429 #define CONFIG_VID 430 #endif 431 #define CONFIG_VOL_MONITOR_IR36021_SET 432 #define CONFIG_VOL_MONITOR_IR36021_READ 433 /* The lowest and highest voltage allowed for T208xRDB */ 434 #define VDD_MV_MIN 819 435 #define VDD_MV_MAX 1212 436 437 /* 438 * RapidIO 439 */ 440 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 441 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 442 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 443 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 444 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 445 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 446 /* 447 * for slave u-boot IMAGE instored in master memory space, 448 * PHYS must be aligned based on the SIZE 449 */ 450 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 451 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 452 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 453 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 454 /* 455 * for slave UCODE and ENV instored in master memory space, 456 * PHYS must be aligned based on the SIZE 457 */ 458 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 459 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 460 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 461 462 /* slave core release by master*/ 463 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 464 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 465 466 /* 467 * SRIO_PCIE_BOOT - SLAVE 468 */ 469 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 470 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 471 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 472 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 473 #endif 474 475 /* 476 * eSPI - Enhanced SPI 477 */ 478 #ifdef CONFIG_SPI_FLASH 479 #define CONFIG_SPI_FLASH_BAR 480 #define CONFIG_SF_DEFAULT_SPEED 10000000 481 #define CONFIG_SF_DEFAULT_MODE 0 482 #endif 483 484 /* 485 * General PCI 486 * Memory space is mapped 1-1, but I/O space must start from 0. 487 */ 488 #define CONFIG_PCIE1 /* PCIE controller 1 */ 489 #define CONFIG_PCIE2 /* PCIE controller 2 */ 490 #define CONFIG_PCIE3 /* PCIE controller 3 */ 491 #define CONFIG_PCIE4 /* PCIE controller 4 */ 492 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 493 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 494 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 495 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 496 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 497 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 498 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 499 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 500 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 501 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 502 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 503 504 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 505 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 506 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 507 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 508 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 509 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 510 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 511 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 512 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 513 514 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 515 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 516 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 517 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 518 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 519 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 520 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 521 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 522 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 523 524 /* controller 4, Base address 203000 */ 525 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 526 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 527 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 528 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 529 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 530 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 531 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 532 533 #ifdef CONFIG_PCI 534 #define CONFIG_PCI_INDIRECT_BRIDGE 535 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 536 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 537 #define CONFIG_DOS_PARTITION 538 #endif 539 540 /* Qman/Bman */ 541 #ifndef CONFIG_NOBQFMAN 542 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 543 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 544 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 545 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 546 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 547 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 548 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 549 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 550 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 551 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 552 CONFIG_SYS_BMAN_CENA_SIZE) 553 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 554 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 555 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 556 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 557 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 558 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 559 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 560 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 561 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 562 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 563 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 564 CONFIG_SYS_QMAN_CENA_SIZE) 565 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 566 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 567 568 #define CONFIG_SYS_DPAA_FMAN 569 #define CONFIG_SYS_DPAA_PME 570 #define CONFIG_SYS_PMAN 571 #define CONFIG_SYS_DPAA_DCE 572 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 573 #define CONFIG_SYS_INTERLAKEN 574 575 /* Default address of microcode for the Linux Fman driver */ 576 #if defined(CONFIG_SPIFLASH) 577 /* 578 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 579 * env, so we got 0x110000. 580 */ 581 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 582 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 583 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 584 #define CONFIG_CORTINA_FW_ADDR 0x120000 585 586 #elif defined(CONFIG_SDCARD) 587 /* 588 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 589 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 590 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 591 */ 592 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 593 #define CONFIG_SYS_CORTINA_FW_IN_MMC 594 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 595 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 596 597 #elif defined(CONFIG_NAND) 598 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 599 #define CONFIG_SYS_CORTINA_FW_IN_NAND 600 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 601 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 602 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 603 /* 604 * Slave has no ucode locally, it can fetch this from remote. When implementing 605 * in two corenet boards, slave's ucode could be stored in master's memory 606 * space, the address can be mapped from slave TLB->slave LAW-> 607 * slave SRIO or PCIE outbound window->master inbound window-> 608 * master LAW->the ucode address in master's memory space. 609 */ 610 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 611 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 612 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 613 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 614 #else 615 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 616 #define CONFIG_SYS_CORTINA_FW_IN_NOR 617 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 618 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 619 #endif 620 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 621 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 622 #endif /* CONFIG_NOBQFMAN */ 623 624 #ifdef CONFIG_SYS_DPAA_FMAN 625 #define CONFIG_FMAN_ENET 626 #define CONFIG_PHYLIB_10G 627 #define CONFIG_PHY_AQUANTIA 628 #define CONFIG_PHY_CORTINA 629 #define CONFIG_PHY_REALTEK 630 #define CONFIG_CORTINA_FW_LENGTH 0x40000 631 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 632 #define RGMII_PHY2_ADDR 0x02 633 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 634 #define CORTINA_PHY_ADDR2 0x0d 635 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 636 #define FM1_10GEC4_PHY_ADDR 0x01 637 #endif 638 639 #ifdef CONFIG_FMAN_ENET 640 #define CONFIG_MII /* MII PHY management */ 641 #define CONFIG_ETHPRIME "FM1@DTSEC3" 642 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 643 #endif 644 645 /* 646 * SATA 647 */ 648 #ifdef CONFIG_FSL_SATA_V2 649 #define CONFIG_LIBATA 650 #define CONFIG_FSL_SATA 651 #define CONFIG_SYS_SATA_MAX_DEVICE 2 652 #define CONFIG_SATA1 653 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 654 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 655 #define CONFIG_SATA2 656 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 657 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 658 #define CONFIG_LBA48 659 #define CONFIG_CMD_SATA 660 #define CONFIG_DOS_PARTITION 661 #endif 662 663 /* 664 * USB 665 */ 666 #ifdef CONFIG_USB_EHCI 667 #define CONFIG_USB_EHCI_FSL 668 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 669 #define CONFIG_HAS_FSL_DR_USB 670 #endif 671 672 /* 673 * SDHC 674 */ 675 #ifdef CONFIG_MMC 676 #define CONFIG_FSL_ESDHC 677 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 678 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 679 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 680 #define CONFIG_GENERIC_MMC 681 #define CONFIG_DOS_PARTITION 682 #endif 683 684 /* 685 * Dynamic MTD Partition support with mtdparts 686 */ 687 #ifndef CONFIG_SYS_NO_FLASH 688 #define CONFIG_MTD_DEVICE 689 #define CONFIG_MTD_PARTITIONS 690 #define CONFIG_CMD_MTDPARTS 691 #define CONFIG_FLASH_CFI_MTD 692 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 693 "spi0=spife110000.1" 694 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 695 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 696 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 697 "1m(uboot),5m(kernel),128k(dtb),-(user)" 698 #endif 699 700 /* 701 * Environment 702 */ 703 704 /* 705 * Command line configuration. 706 */ 707 #define CONFIG_CMD_ERRATA 708 #define CONFIG_CMD_REGINFO 709 710 #ifdef CONFIG_PCI 711 #define CONFIG_CMD_PCI 712 #endif 713 714 /* Hash command with SHA acceleration supported in hardware */ 715 #ifdef CONFIG_FSL_CAAM 716 #define CONFIG_CMD_HASH 717 #define CONFIG_SHA_HW_ACCEL 718 #endif 719 720 /* 721 * Miscellaneous configurable options 722 */ 723 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 724 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 725 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 726 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 727 #ifdef CONFIG_CMD_KGDB 728 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 729 #else 730 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 731 #endif 732 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 733 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 734 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 735 736 /* 737 * For booting Linux, the board info and command line data 738 * have to be in the first 64 MB of memory, since this is 739 * the maximum mapped by the Linux kernel during initialization. 740 */ 741 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 742 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 743 744 #ifdef CONFIG_CMD_KGDB 745 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 746 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 747 #endif 748 749 /* 750 * Environment Configuration 751 */ 752 #define CONFIG_ROOTPATH "/opt/nfsroot" 753 #define CONFIG_BOOTFILE "uImage" 754 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 755 756 /* default location for tftp and bootm */ 757 #define CONFIG_LOADADDR 1000000 758 #define CONFIG_BAUDRATE 115200 759 #define __USB_PHY_TYPE utmi 760 761 #define CONFIG_EXTRA_ENV_SETTINGS \ 762 "hwconfig=fsl_ddr:" \ 763 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 764 "bank_intlv=auto;" \ 765 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 766 "netdev=eth0\0" \ 767 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 768 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 769 "tftpflash=tftpboot $loadaddr $uboot && " \ 770 "protect off $ubootaddr +$filesize && " \ 771 "erase $ubootaddr +$filesize && " \ 772 "cp.b $loadaddr $ubootaddr $filesize && " \ 773 "protect on $ubootaddr +$filesize && " \ 774 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 775 "consoledev=ttyS0\0" \ 776 "ramdiskaddr=2000000\0" \ 777 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 778 "fdtaddr=1e00000\0" \ 779 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 780 "bdev=sda3\0" 781 782 /* 783 * For emulation this causes u-boot to jump to the start of the 784 * proof point app code automatically 785 */ 786 #define CONFIG_PROOF_POINTS \ 787 "setenv bootargs root=/dev/$bdev rw " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "cpu 1 release 0x29000000 - - -;" \ 790 "cpu 2 release 0x29000000 - - -;" \ 791 "cpu 3 release 0x29000000 - - -;" \ 792 "cpu 4 release 0x29000000 - - -;" \ 793 "cpu 5 release 0x29000000 - - -;" \ 794 "cpu 6 release 0x29000000 - - -;" \ 795 "cpu 7 release 0x29000000 - - -;" \ 796 "go 0x29000000" 797 798 #define CONFIG_HVBOOT \ 799 "setenv bootargs config-addr=0x60000000; " \ 800 "bootm 0x01000000 - 0x00f00000" 801 802 #define CONFIG_ALU \ 803 "setenv bootargs root=/dev/$bdev rw " \ 804 "console=$consoledev,$baudrate $othbootargs;" \ 805 "cpu 1 release 0x01000000 - - -;" \ 806 "cpu 2 release 0x01000000 - - -;" \ 807 "cpu 3 release 0x01000000 - - -;" \ 808 "cpu 4 release 0x01000000 - - -;" \ 809 "cpu 5 release 0x01000000 - - -;" \ 810 "cpu 6 release 0x01000000 - - -;" \ 811 "cpu 7 release 0x01000000 - - -;" \ 812 "go 0x01000000" 813 814 #define CONFIG_LINUX \ 815 "setenv bootargs root=/dev/ram rw " \ 816 "console=$consoledev,$baudrate $othbootargs;" \ 817 "setenv ramdiskaddr 0x02000000;" \ 818 "setenv fdtaddr 0x00c00000;" \ 819 "setenv loadaddr 0x1000000;" \ 820 "bootm $loadaddr $ramdiskaddr $fdtaddr" 821 822 #define CONFIG_HDBOOT \ 823 "setenv bootargs root=/dev/$bdev rw " \ 824 "console=$consoledev,$baudrate $othbootargs;" \ 825 "tftp $loadaddr $bootfile;" \ 826 "tftp $fdtaddr $fdtfile;" \ 827 "bootm $loadaddr - $fdtaddr" 828 829 #define CONFIG_NFSBOOTCOMMAND \ 830 "setenv bootargs root=/dev/nfs rw " \ 831 "nfsroot=$serverip:$rootpath " \ 832 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 833 "console=$consoledev,$baudrate $othbootargs;" \ 834 "tftp $loadaddr $bootfile;" \ 835 "tftp $fdtaddr $fdtfile;" \ 836 "bootm $loadaddr - $fdtaddr" 837 838 #define CONFIG_RAMBOOTCOMMAND \ 839 "setenv bootargs root=/dev/ram rw " \ 840 "console=$consoledev,$baudrate $othbootargs;" \ 841 "tftp $ramdiskaddr $ramdiskfile;" \ 842 "tftp $loadaddr $bootfile;" \ 843 "tftp $fdtaddr $fdtfile;" \ 844 "bootm $loadaddr $ramdiskaddr $fdtaddr" 845 846 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 847 848 #include <asm/fsl_secure_boot.h> 849 850 #endif /* __T2080RDB_H */ 851