1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_FSL_SATA_V2 16 17 /* High Level Configuration Options */ 18 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 19 #define CONFIG_MP /* support multiple processors */ 20 #define CONFIG_ENABLE_36BIT_PHYS 21 22 #ifdef CONFIG_PHYS_64BIT 23 #define CONFIG_ADDR_MAP 1 24 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 25 #endif 26 27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 28 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 29 #define CONFIG_ENV_OVERWRITE 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 33 34 #define CONFIG_SPL_FLUSH_IMAGE 35 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 37 #define CONFIG_SPL_PAD_TO 0x40000 38 #define CONFIG_SPL_MAX_SIZE 0x28000 39 #define RESET_VECTOR_OFFSET 0x27FFC 40 #define BOOT_PAGE_OFFSET 0x27000 41 #ifdef CONFIG_SPL_BUILD 42 #define CONFIG_SPL_SKIP_RELOCATE 43 #define CONFIG_SPL_COMMON_INIT_DDR 44 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 45 #endif 46 47 #ifdef CONFIG_NAND 48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 50 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 54 #define CONFIG_SPL_NAND_BOOT 55 #endif 56 57 #ifdef CONFIG_SPIFLASH 58 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 59 #define CONFIG_SPL_SPI_FLASH_MINIMAL 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 61 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 64 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 65 #ifndef CONFIG_SPL_BUILD 66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 67 #endif 68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 69 #define CONFIG_SPL_SPI_BOOT 70 #endif 71 72 #ifdef CONFIG_SDCARD 73 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 74 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 75 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 76 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 77 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 78 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 79 #ifndef CONFIG_SPL_BUILD 80 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 81 #endif 82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 83 #define CONFIG_SPL_MMC_BOOT 84 #endif 85 86 #endif /* CONFIG_RAMBOOT_PBL */ 87 88 #define CONFIG_SRIO_PCIE_BOOT_MASTER 89 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 90 /* Set 1M boot space */ 91 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 92 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 93 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 94 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 95 #endif 96 97 #ifndef CONFIG_RESET_VECTOR_ADDRESS 98 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 99 #endif 100 101 /* 102 * These can be toggled for performance analysis, otherwise use default. 103 */ 104 #define CONFIG_SYS_CACHE_STASHING 105 #define CONFIG_BTB /* toggle branch predition */ 106 #define CONFIG_DDR_ECC 107 #ifdef CONFIG_DDR_ECC 108 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 109 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 110 #endif 111 112 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 113 #define CONFIG_SYS_MEMTEST_END 0x00400000 114 #define CONFIG_SYS_ALT_MEMTEST 115 116 #ifdef CONFIG_MTD_NOR_FLASH 117 #define CONFIG_FLASH_CFI_DRIVER 118 #define CONFIG_SYS_FLASH_CFI 119 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 120 #endif 121 122 #if defined(CONFIG_SPIFLASH) 123 #define CONFIG_SYS_EXTRA_ENV_RELOC 124 #define CONFIG_ENV_SPI_BUS 0 125 #define CONFIG_ENV_SPI_CS 0 126 #define CONFIG_ENV_SPI_MAX_HZ 10000000 127 #define CONFIG_ENV_SPI_MODE 0 128 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 129 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 130 #define CONFIG_ENV_SECT_SIZE 0x10000 131 #elif defined(CONFIG_SDCARD) 132 #define CONFIG_SYS_EXTRA_ENV_RELOC 133 #define CONFIG_SYS_MMC_ENV_DEV 0 134 #define CONFIG_ENV_SIZE 0x2000 135 #define CONFIG_ENV_OFFSET (512 * 0x800) 136 #elif defined(CONFIG_NAND) 137 #define CONFIG_SYS_EXTRA_ENV_RELOC 138 #define CONFIG_ENV_SIZE 0x2000 139 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 140 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 141 #define CONFIG_ENV_ADDR 0xffe20000 142 #define CONFIG_ENV_SIZE 0x2000 143 #elif defined(CONFIG_ENV_IS_NOWHERE) 144 #define CONFIG_ENV_SIZE 0x2000 145 #else 146 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 147 #define CONFIG_ENV_SIZE 0x2000 148 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 149 #endif 150 151 #ifndef __ASSEMBLY__ 152 unsigned long get_board_sys_clk(void); 153 unsigned long get_board_ddr_clk(void); 154 #endif 155 156 #define CONFIG_SYS_CLK_FREQ 66660000 157 #define CONFIG_DDR_CLK_FREQ 133330000 158 159 /* 160 * Config the L3 Cache as L3 SRAM 161 */ 162 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 163 #define CONFIG_SYS_L3_SIZE (512 << 10) 164 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 165 #ifdef CONFIG_RAMBOOT_PBL 166 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 167 #endif 168 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 169 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 170 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 171 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 172 173 #define CONFIG_SYS_DCSRBAR 0xf0000000 174 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 175 176 /* EEPROM */ 177 #define CONFIG_ID_EEPROM 178 #define CONFIG_SYS_I2C_EEPROM_NXID 179 #define CONFIG_SYS_EEPROM_BUS_NUM 0 180 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 181 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 182 183 /* 184 * DDR Setup 185 */ 186 #define CONFIG_VERY_BIG_RAM 187 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 188 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 189 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 190 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 191 #define CONFIG_DDR_SPD 192 #undef CONFIG_FSL_DDR_INTERACTIVE 193 #define CONFIG_SYS_SPD_BUS_NUM 0 194 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 195 #define SPD_EEPROM_ADDRESS1 0x51 196 #define SPD_EEPROM_ADDRESS2 0x52 197 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 198 #define CTRL_INTLV_PREFERED cacheline 199 200 /* 201 * IFC Definitions 202 */ 203 #define CONFIG_SYS_FLASH_BASE 0xe8000000 204 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 205 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 206 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 207 CSPR_PORT_SIZE_16 | \ 208 CSPR_MSEL_NOR | \ 209 CSPR_V) 210 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 211 212 /* NOR Flash Timing Params */ 213 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 214 215 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 216 FTIM0_NOR_TEADC(0x5) | \ 217 FTIM0_NOR_TEAHC(0x5)) 218 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 219 FTIM1_NOR_TRAD_NOR(0x1A) |\ 220 FTIM1_NOR_TSEQRAD_NOR(0x13)) 221 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 222 FTIM2_NOR_TCH(0x4) | \ 223 FTIM2_NOR_TWPH(0x0E) | \ 224 FTIM2_NOR_TWP(0x1c)) 225 #define CONFIG_SYS_NOR_FTIM3 0x0 226 227 #define CONFIG_SYS_FLASH_QUIET_TEST 228 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 229 230 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 231 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 232 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 233 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 234 #define CONFIG_SYS_FLASH_EMPTY_INFO 235 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 236 237 /* CPLD on IFC */ 238 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 239 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 240 #define CONFIG_SYS_CSPR2_EXT (0xf) 241 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 242 | CSPR_PORT_SIZE_8 \ 243 | CSPR_MSEL_GPCM \ 244 | CSPR_V) 245 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 246 #define CONFIG_SYS_CSOR2 0x0 247 248 /* CPLD Timing parameters for IFC CS2 */ 249 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 250 FTIM0_GPCM_TEADC(0x0e) | \ 251 FTIM0_GPCM_TEAHC(0x0e)) 252 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 253 FTIM1_GPCM_TRAD(0x1f)) 254 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 255 FTIM2_GPCM_TCH(0x8) | \ 256 FTIM2_GPCM_TWP(0x1f)) 257 #define CONFIG_SYS_CS2_FTIM3 0x0 258 259 /* NAND Flash on IFC */ 260 #define CONFIG_NAND_FSL_IFC 261 #define CONFIG_SYS_NAND_BASE 0xff800000 262 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 263 264 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 265 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 266 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 267 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 268 | CSPR_V) 269 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 270 271 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 272 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 273 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 274 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 275 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 276 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 277 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 278 279 #define CONFIG_SYS_NAND_ONFI_DETECTION 280 281 /* ONFI NAND Flash mode0 Timing Params */ 282 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 283 FTIM0_NAND_TWP(0x18) | \ 284 FTIM0_NAND_TWCHT(0x07) | \ 285 FTIM0_NAND_TWH(0x0a)) 286 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 287 FTIM1_NAND_TWBE(0x39) | \ 288 FTIM1_NAND_TRR(0x0e) | \ 289 FTIM1_NAND_TRP(0x18)) 290 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 291 FTIM2_NAND_TREH(0x0a) | \ 292 FTIM2_NAND_TWHRE(0x1e)) 293 #define CONFIG_SYS_NAND_FTIM3 0x0 294 295 #define CONFIG_SYS_NAND_DDR_LAW 11 296 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 297 #define CONFIG_SYS_MAX_NAND_DEVICE 1 298 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 299 300 #if defined(CONFIG_NAND) 301 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 302 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 303 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 304 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 305 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 306 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 307 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 308 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 309 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 310 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 311 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 312 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 313 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 314 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 315 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 316 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 317 #else 318 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 319 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 320 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 321 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 322 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 323 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 324 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 325 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 326 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 327 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 328 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 329 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 330 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 331 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 332 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 333 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 334 #endif 335 336 #if defined(CONFIG_RAMBOOT_PBL) 337 #define CONFIG_SYS_RAMBOOT 338 #endif 339 340 #ifdef CONFIG_SPL_BUILD 341 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 342 #else 343 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 344 #endif 345 346 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 347 #define CONFIG_MISC_INIT_R 348 #define CONFIG_HWCONFIG 349 350 /* define to use L1 as initial stack */ 351 #define CONFIG_L1_INIT_RAM 352 #define CONFIG_SYS_INIT_RAM_LOCK 353 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 354 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 355 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 356 /* The assembler doesn't like typecast */ 357 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 358 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 359 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 360 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 361 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 362 GENERATED_GBL_DATA_SIZE) 363 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 364 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 365 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 366 367 /* 368 * Serial Port 369 */ 370 #define CONFIG_CONS_INDEX 1 371 #define CONFIG_SYS_NS16550_SERIAL 372 #define CONFIG_SYS_NS16550_REG_SIZE 1 373 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 374 #define CONFIG_SYS_BAUDRATE_TABLE \ 375 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 376 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 377 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 378 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 379 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 380 381 /* 382 * I2C 383 */ 384 #define CONFIG_SYS_I2C 385 #define CONFIG_SYS_I2C_FSL 386 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 387 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 388 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 389 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 390 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 391 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 392 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 393 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 394 #define CONFIG_SYS_FSL_I2C_SPEED 100000 395 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 396 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 397 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 398 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 399 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 400 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 401 #define I2C_MUX_CH_DEFAULT 0x8 402 403 #define I2C_MUX_CH_VOL_MONITOR 0xa 404 405 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 406 #ifndef CONFIG_SPL_BUILD 407 #define CONFIG_VID 408 #endif 409 #define CONFIG_VOL_MONITOR_IR36021_SET 410 #define CONFIG_VOL_MONITOR_IR36021_READ 411 /* The lowest and highest voltage allowed for T208xRDB */ 412 #define VDD_MV_MIN 819 413 #define VDD_MV_MAX 1212 414 415 /* 416 * RapidIO 417 */ 418 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 419 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 420 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 421 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 422 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 423 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 424 /* 425 * for slave u-boot IMAGE instored in master memory space, 426 * PHYS must be aligned based on the SIZE 427 */ 428 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 429 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 430 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 431 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 432 /* 433 * for slave UCODE and ENV instored in master memory space, 434 * PHYS must be aligned based on the SIZE 435 */ 436 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 437 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 438 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 439 440 /* slave core release by master*/ 441 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 442 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 443 444 /* 445 * SRIO_PCIE_BOOT - SLAVE 446 */ 447 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 448 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 449 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 450 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 451 #endif 452 453 /* 454 * eSPI - Enhanced SPI 455 */ 456 #ifdef CONFIG_SPI_FLASH 457 #define CONFIG_SPI_FLASH_BAR 458 #define CONFIG_SF_DEFAULT_SPEED 10000000 459 #define CONFIG_SF_DEFAULT_MODE 0 460 #endif 461 462 /* 463 * General PCI 464 * Memory space is mapped 1-1, but I/O space must start from 0. 465 */ 466 #define CONFIG_PCIE1 /* PCIE controller 1 */ 467 #define CONFIG_PCIE2 /* PCIE controller 2 */ 468 #define CONFIG_PCIE3 /* PCIE controller 3 */ 469 #define CONFIG_PCIE4 /* PCIE controller 4 */ 470 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 471 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 472 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 473 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 474 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 475 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 476 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 477 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 478 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 479 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 480 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 481 482 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 483 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 484 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 485 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 486 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 487 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 488 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 489 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 490 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 491 492 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 493 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 494 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 495 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 496 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 497 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 498 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 499 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 500 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 501 502 /* controller 4, Base address 203000 */ 503 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 504 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 505 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 506 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 507 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 508 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 509 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 510 511 #ifdef CONFIG_PCI 512 #define CONFIG_PCI_INDIRECT_BRIDGE 513 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 514 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 515 #endif 516 517 /* Qman/Bman */ 518 #ifndef CONFIG_NOBQFMAN 519 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 520 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 521 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 522 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 523 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 524 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 525 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 526 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 527 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 528 CONFIG_SYS_BMAN_CENA_SIZE) 529 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 530 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 531 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 532 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 533 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 534 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 535 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 536 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 537 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 538 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 539 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 540 CONFIG_SYS_QMAN_CENA_SIZE) 541 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 542 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 543 544 #define CONFIG_SYS_DPAA_FMAN 545 #define CONFIG_SYS_DPAA_PME 546 #define CONFIG_SYS_PMAN 547 #define CONFIG_SYS_DPAA_DCE 548 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 549 #define CONFIG_SYS_INTERLAKEN 550 551 /* Default address of microcode for the Linux Fman driver */ 552 #if defined(CONFIG_SPIFLASH) 553 /* 554 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 555 * env, so we got 0x110000. 556 */ 557 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 558 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 559 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 560 #define CONFIG_CORTINA_FW_ADDR 0x120000 561 562 #elif defined(CONFIG_SDCARD) 563 /* 564 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 565 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 566 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 567 */ 568 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 569 #define CONFIG_SYS_CORTINA_FW_IN_MMC 570 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 571 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 572 573 #elif defined(CONFIG_NAND) 574 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 575 #define CONFIG_SYS_CORTINA_FW_IN_NAND 576 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 577 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 578 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 579 /* 580 * Slave has no ucode locally, it can fetch this from remote. When implementing 581 * in two corenet boards, slave's ucode could be stored in master's memory 582 * space, the address can be mapped from slave TLB->slave LAW-> 583 * slave SRIO or PCIE outbound window->master inbound window-> 584 * master LAW->the ucode address in master's memory space. 585 */ 586 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 587 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 588 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 589 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 590 #else 591 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 592 #define CONFIG_SYS_CORTINA_FW_IN_NOR 593 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 594 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 595 #endif 596 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 597 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 598 #endif /* CONFIG_NOBQFMAN */ 599 600 #ifdef CONFIG_SYS_DPAA_FMAN 601 #define CONFIG_FMAN_ENET 602 #define CONFIG_PHYLIB_10G 603 #define CONFIG_PHY_AQUANTIA 604 #define CONFIG_PHY_CORTINA 605 #define CONFIG_PHY_REALTEK 606 #define CONFIG_CORTINA_FW_LENGTH 0x40000 607 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 608 #define RGMII_PHY2_ADDR 0x02 609 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 610 #define CORTINA_PHY_ADDR2 0x0d 611 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 612 #define FM1_10GEC4_PHY_ADDR 0x01 613 #endif 614 615 #ifdef CONFIG_FMAN_ENET 616 #define CONFIG_MII /* MII PHY management */ 617 #define CONFIG_ETHPRIME "FM1@DTSEC3" 618 #endif 619 620 /* 621 * SATA 622 */ 623 #ifdef CONFIG_FSL_SATA_V2 624 #define CONFIG_SYS_SATA_MAX_DEVICE 2 625 #define CONFIG_SATA1 626 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 627 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 628 #define CONFIG_SATA2 629 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 630 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 631 #define CONFIG_LBA48 632 #endif 633 634 /* 635 * USB 636 */ 637 #ifdef CONFIG_USB_EHCI_HCD 638 #define CONFIG_USB_EHCI_FSL 639 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 640 #define CONFIG_HAS_FSL_DR_USB 641 #endif 642 643 /* 644 * SDHC 645 */ 646 #ifdef CONFIG_MMC 647 #define CONFIG_FSL_ESDHC 648 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 649 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 650 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 651 #endif 652 653 /* 654 * Dynamic MTD Partition support with mtdparts 655 */ 656 #ifdef CONFIG_MTD_NOR_FLASH 657 #define CONFIG_MTD_DEVICE 658 #define CONFIG_MTD_PARTITIONS 659 #define CONFIG_FLASH_CFI_MTD 660 #endif 661 662 /* 663 * Environment 664 */ 665 666 /* 667 * Miscellaneous configurable options 668 */ 669 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 670 671 /* 672 * For booting Linux, the board info and command line data 673 * have to be in the first 64 MB of memory, since this is 674 * the maximum mapped by the Linux kernel during initialization. 675 */ 676 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 677 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 678 679 #ifdef CONFIG_CMD_KGDB 680 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 681 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 682 #endif 683 684 /* 685 * Environment Configuration 686 */ 687 #define CONFIG_ROOTPATH "/opt/nfsroot" 688 #define CONFIG_BOOTFILE "uImage" 689 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 690 691 /* default location for tftp and bootm */ 692 #define CONFIG_LOADADDR 1000000 693 #define __USB_PHY_TYPE utmi 694 695 #define CONFIG_EXTRA_ENV_SETTINGS \ 696 "hwconfig=fsl_ddr:" \ 697 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 698 "bank_intlv=auto;" \ 699 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 700 "netdev=eth0\0" \ 701 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 702 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 703 "tftpflash=tftpboot $loadaddr $uboot && " \ 704 "protect off $ubootaddr +$filesize && " \ 705 "erase $ubootaddr +$filesize && " \ 706 "cp.b $loadaddr $ubootaddr $filesize && " \ 707 "protect on $ubootaddr +$filesize && " \ 708 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 709 "consoledev=ttyS0\0" \ 710 "ramdiskaddr=2000000\0" \ 711 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 712 "fdtaddr=1e00000\0" \ 713 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 714 "bdev=sda3\0" 715 716 /* 717 * For emulation this causes u-boot to jump to the start of the 718 * proof point app code automatically 719 */ 720 #define CONFIG_PROOF_POINTS \ 721 "setenv bootargs root=/dev/$bdev rw " \ 722 "console=$consoledev,$baudrate $othbootargs;" \ 723 "cpu 1 release 0x29000000 - - -;" \ 724 "cpu 2 release 0x29000000 - - -;" \ 725 "cpu 3 release 0x29000000 - - -;" \ 726 "cpu 4 release 0x29000000 - - -;" \ 727 "cpu 5 release 0x29000000 - - -;" \ 728 "cpu 6 release 0x29000000 - - -;" \ 729 "cpu 7 release 0x29000000 - - -;" \ 730 "go 0x29000000" 731 732 #define CONFIG_HVBOOT \ 733 "setenv bootargs config-addr=0x60000000; " \ 734 "bootm 0x01000000 - 0x00f00000" 735 736 #define CONFIG_ALU \ 737 "setenv bootargs root=/dev/$bdev rw " \ 738 "console=$consoledev,$baudrate $othbootargs;" \ 739 "cpu 1 release 0x01000000 - - -;" \ 740 "cpu 2 release 0x01000000 - - -;" \ 741 "cpu 3 release 0x01000000 - - -;" \ 742 "cpu 4 release 0x01000000 - - -;" \ 743 "cpu 5 release 0x01000000 - - -;" \ 744 "cpu 6 release 0x01000000 - - -;" \ 745 "cpu 7 release 0x01000000 - - -;" \ 746 "go 0x01000000" 747 748 #define CONFIG_LINUX \ 749 "setenv bootargs root=/dev/ram rw " \ 750 "console=$consoledev,$baudrate $othbootargs;" \ 751 "setenv ramdiskaddr 0x02000000;" \ 752 "setenv fdtaddr 0x00c00000;" \ 753 "setenv loadaddr 0x1000000;" \ 754 "bootm $loadaddr $ramdiskaddr $fdtaddr" 755 756 #define CONFIG_HDBOOT \ 757 "setenv bootargs root=/dev/$bdev rw " \ 758 "console=$consoledev,$baudrate $othbootargs;" \ 759 "tftp $loadaddr $bootfile;" \ 760 "tftp $fdtaddr $fdtfile;" \ 761 "bootm $loadaddr - $fdtaddr" 762 763 #define CONFIG_NFSBOOTCOMMAND \ 764 "setenv bootargs root=/dev/nfs rw " \ 765 "nfsroot=$serverip:$rootpath " \ 766 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 767 "console=$consoledev,$baudrate $othbootargs;" \ 768 "tftp $loadaddr $bootfile;" \ 769 "tftp $fdtaddr $fdtfile;" \ 770 "bootm $loadaddr - $fdtaddr" 771 772 #define CONFIG_RAMBOOTCOMMAND \ 773 "setenv bootargs root=/dev/ram rw " \ 774 "console=$consoledev,$baudrate $othbootargs;" \ 775 "tftp $ramdiskaddr $ramdiskfile;" \ 776 "tftp $loadaddr $bootfile;" \ 777 "tftp $fdtaddr $fdtfile;" \ 778 "bootm $loadaddr $ramdiskaddr $fdtaddr" 779 780 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 781 782 #include <asm/fsl_secure_boot.h> 783 784 #endif /* __T2080RDB_H */ 785