1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_T2080RDB 17 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 18 #define CONFIG_MMC 19 #define CONFIG_SPI_FLASH 20 #define CONFIG_USB_EHCI 21 #define CONFIG_FSL_SATA_V2 22 23 /* High Level Configuration Options */ 24 #define CONFIG_PHYS_64BIT 25 #define CONFIG_BOOKE 26 #define CONFIG_E500 /* BOOKE e500 family */ 27 #define CONFIG_E500MC /* BOOKE e500mc family */ 28 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 29 #define CONFIG_MP /* support multiple processors */ 30 #define CONFIG_ENABLE_36BIT_PHYS 31 32 #ifdef CONFIG_PHYS_64BIT 33 #define CONFIG_ADDR_MAP 1 34 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 35 #endif 36 37 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 38 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 39 #define CONFIG_FSL_IFC /* Enable IFC Support */ 40 #define CONFIG_FSL_LAW /* Use common FSL init code */ 41 #define CONFIG_ENV_OVERWRITE 42 43 #ifdef CONFIG_RAMBOOT_PBL 44 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 45 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 46 47 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 48 #define CONFIG_SPL_ENV_SUPPORT 49 #define CONFIG_SPL_SERIAL_SUPPORT 50 #define CONFIG_SPL_FLUSH_IMAGE 51 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 52 #define CONFIG_SPL_LIBGENERIC_SUPPORT 53 #define CONFIG_SPL_LIBCOMMON_SUPPORT 54 #define CONFIG_SPL_I2C_SUPPORT 55 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 56 #define CONFIG_FSL_LAW /* Use common FSL init code */ 57 #define CONFIG_SYS_TEXT_BASE 0x00201000 58 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 59 #define CONFIG_SPL_PAD_TO 0x40000 60 #define CONFIG_SPL_MAX_SIZE 0x28000 61 #define RESET_VECTOR_OFFSET 0x27FFC 62 #define BOOT_PAGE_OFFSET 0x27000 63 #ifdef CONFIG_SPL_BUILD 64 #define CONFIG_SPL_SKIP_RELOCATE 65 #define CONFIG_SPL_COMMON_INIT_DDR 66 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 67 #define CONFIG_SYS_NO_FLASH 68 #endif 69 70 #ifdef CONFIG_NAND 71 #define CONFIG_SPL_NAND_SUPPORT 72 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 73 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 74 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 75 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 76 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 77 #define CONFIG_SPL_NAND_BOOT 78 #endif 79 80 #ifdef CONFIG_SPIFLASH 81 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 82 #define CONFIG_SPL_SPI_SUPPORT 83 #define CONFIG_SPL_SPI_FLASH_SUPPORT 84 #define CONFIG_SPL_SPI_FLASH_MINIMAL 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 90 #ifndef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #endif 93 #define CONFIG_SPL_SPI_BOOT 94 #endif 95 96 #ifdef CONFIG_SDCARD 97 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 98 #define CONFIG_SPL_MMC_SUPPORT 99 #define CONFIG_SPL_MMC_MINIMAL 100 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 101 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 102 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 103 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 104 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 105 #ifndef CONFIG_SPL_BUILD 106 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 107 #endif 108 #define CONFIG_SPL_MMC_BOOT 109 #endif 110 111 #endif /* CONFIG_RAMBOOT_PBL */ 112 113 #define CONFIG_SRIO_PCIE_BOOT_MASTER 114 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 115 /* Set 1M boot space */ 116 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 117 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 118 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 119 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 120 #define CONFIG_SYS_NO_FLASH 121 #endif 122 123 #ifndef CONFIG_SYS_TEXT_BASE 124 #define CONFIG_SYS_TEXT_BASE 0xeff40000 125 #endif 126 127 #ifndef CONFIG_RESET_VECTOR_ADDRESS 128 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 129 #endif 130 131 /* 132 * These can be toggled for performance analysis, otherwise use default. 133 */ 134 #define CONFIG_SYS_CACHE_STASHING 135 #define CONFIG_BTB /* toggle branch predition */ 136 #define CONFIG_DDR_ECC 137 #ifdef CONFIG_DDR_ECC 138 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 139 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 140 #endif 141 142 #ifndef CONFIG_SYS_NO_FLASH 143 #define CONFIG_FLASH_CFI_DRIVER 144 #define CONFIG_SYS_FLASH_CFI 145 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 146 #endif 147 148 #if defined(CONFIG_SPIFLASH) 149 #define CONFIG_SYS_EXTRA_ENV_RELOC 150 #define CONFIG_ENV_IS_IN_SPI_FLASH 151 #define CONFIG_ENV_SPI_BUS 0 152 #define CONFIG_ENV_SPI_CS 0 153 #define CONFIG_ENV_SPI_MAX_HZ 10000000 154 #define CONFIG_ENV_SPI_MODE 0 155 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 156 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 157 #define CONFIG_ENV_SECT_SIZE 0x10000 158 #elif defined(CONFIG_SDCARD) 159 #define CONFIG_SYS_EXTRA_ENV_RELOC 160 #define CONFIG_ENV_IS_IN_MMC 161 #define CONFIG_SYS_MMC_ENV_DEV 0 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_OFFSET (512 * 0x800) 164 #elif defined(CONFIG_NAND) 165 #define CONFIG_SYS_EXTRA_ENV_RELOC 166 #define CONFIG_ENV_IS_IN_NAND 167 #define CONFIG_ENV_SIZE 0x2000 168 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 169 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 170 #define CONFIG_ENV_IS_IN_REMOTE 171 #define CONFIG_ENV_ADDR 0xffe20000 172 #define CONFIG_ENV_SIZE 0x2000 173 #elif defined(CONFIG_ENV_IS_NOWHERE) 174 #define CONFIG_ENV_SIZE 0x2000 175 #else 176 #define CONFIG_ENV_IS_IN_FLASH 177 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 178 #define CONFIG_ENV_SIZE 0x2000 179 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 180 #endif 181 182 #ifndef __ASSEMBLY__ 183 unsigned long get_board_sys_clk(void); 184 unsigned long get_board_ddr_clk(void); 185 #endif 186 187 #define CONFIG_SYS_CLK_FREQ 66660000 188 #define CONFIG_DDR_CLK_FREQ 133330000 189 190 /* 191 * Config the L3 Cache as L3 SRAM 192 */ 193 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 194 #define CONFIG_SYS_L3_SIZE (512 << 10) 195 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 196 #ifdef CONFIG_RAMBOOT_PBL 197 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 198 #endif 199 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 200 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 201 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 202 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 203 204 #define CONFIG_SYS_DCSRBAR 0xf0000000 205 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 206 207 /* EEPROM */ 208 #define CONFIG_ID_EEPROM 209 #define CONFIG_SYS_I2C_EEPROM_NXID 210 #define CONFIG_SYS_EEPROM_BUS_NUM 0 211 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 212 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 213 214 /* 215 * DDR Setup 216 */ 217 #define CONFIG_VERY_BIG_RAM 218 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 219 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 220 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 221 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 222 #define CONFIG_DDR_SPD 223 #define CONFIG_SYS_FSL_DDR3 224 #undef CONFIG_FSL_DDR_INTERACTIVE 225 #define CONFIG_SYS_SPD_BUS_NUM 0 226 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 227 #define SPD_EEPROM_ADDRESS1 0x51 228 #define SPD_EEPROM_ADDRESS2 0x52 229 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 230 #define CTRL_INTLV_PREFERED cacheline 231 232 /* 233 * IFC Definitions 234 */ 235 #define CONFIG_SYS_FLASH_BASE 0xe8000000 236 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 237 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 238 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 239 CSPR_PORT_SIZE_16 | \ 240 CSPR_MSEL_NOR | \ 241 CSPR_V) 242 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 243 244 /* NOR Flash Timing Params */ 245 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 246 247 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 248 FTIM0_NOR_TEADC(0x5) | \ 249 FTIM0_NOR_TEAHC(0x5)) 250 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 251 FTIM1_NOR_TRAD_NOR(0x1A) |\ 252 FTIM1_NOR_TSEQRAD_NOR(0x13)) 253 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 254 FTIM2_NOR_TCH(0x4) | \ 255 FTIM2_NOR_TWPH(0x0E) | \ 256 FTIM2_NOR_TWP(0x1c)) 257 #define CONFIG_SYS_NOR_FTIM3 0x0 258 259 #define CONFIG_SYS_FLASH_QUIET_TEST 260 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 261 262 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 263 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 264 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 265 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 266 #define CONFIG_SYS_FLASH_EMPTY_INFO 267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 268 269 /* CPLD on IFC */ 270 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 271 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 272 #define CONFIG_SYS_CSPR2_EXT (0xf) 273 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 274 | CSPR_PORT_SIZE_8 \ 275 | CSPR_MSEL_GPCM \ 276 | CSPR_V) 277 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 278 #define CONFIG_SYS_CSOR2 0x0 279 280 /* CPLD Timing parameters for IFC CS2 */ 281 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 282 FTIM0_GPCM_TEADC(0x0e) | \ 283 FTIM0_GPCM_TEAHC(0x0e)) 284 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 285 FTIM1_GPCM_TRAD(0x1f)) 286 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 287 FTIM2_GPCM_TCH(0x8) | \ 288 FTIM2_GPCM_TWP(0x1f)) 289 #define CONFIG_SYS_CS2_FTIM3 0x0 290 291 /* NAND Flash on IFC */ 292 #define CONFIG_NAND_FSL_IFC 293 #define CONFIG_SYS_NAND_BASE 0xff800000 294 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 295 296 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 297 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 298 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 299 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 300 | CSPR_V) 301 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 302 303 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 304 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 305 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 306 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 307 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 308 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 309 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 310 311 #define CONFIG_SYS_NAND_ONFI_DETECTION 312 313 /* ONFI NAND Flash mode0 Timing Params */ 314 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 315 FTIM0_NAND_TWP(0x18) | \ 316 FTIM0_NAND_TWCHT(0x07) | \ 317 FTIM0_NAND_TWH(0x0a)) 318 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 319 FTIM1_NAND_TWBE(0x39) | \ 320 FTIM1_NAND_TRR(0x0e) | \ 321 FTIM1_NAND_TRP(0x18)) 322 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 323 FTIM2_NAND_TREH(0x0a) | \ 324 FTIM2_NAND_TWHRE(0x1e)) 325 #define CONFIG_SYS_NAND_FTIM3 0x0 326 327 #define CONFIG_SYS_NAND_DDR_LAW 11 328 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 329 #define CONFIG_SYS_MAX_NAND_DEVICE 1 330 #define CONFIG_MTD_NAND_VERIFY_WRITE 331 #define CONFIG_CMD_NAND 332 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 333 334 #if defined(CONFIG_NAND) 335 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 336 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 337 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 338 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 339 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 340 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 341 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 342 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 343 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 344 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 345 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #else 352 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 353 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 354 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 355 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 356 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 357 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 358 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 359 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 360 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 361 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 362 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 363 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 364 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 365 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 366 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 367 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 368 #endif 369 370 #if defined(CONFIG_RAMBOOT_PBL) 371 #define CONFIG_SYS_RAMBOOT 372 #endif 373 374 #ifdef CONFIG_SPL_BUILD 375 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 376 #else 377 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 378 #endif 379 380 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 381 #define CONFIG_MISC_INIT_R 382 #define CONFIG_HWCONFIG 383 384 /* define to use L1 as initial stack */ 385 #define CONFIG_L1_INIT_RAM 386 #define CONFIG_SYS_INIT_RAM_LOCK 387 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 390 /* The assembler doesn't like typecast */ 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 392 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 393 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 394 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 395 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 396 GENERATED_GBL_DATA_SIZE) 397 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 398 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 399 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 400 401 /* 402 * Serial Port 403 */ 404 #define CONFIG_CONS_INDEX 1 405 #define CONFIG_SYS_NS16550 406 #define CONFIG_SYS_NS16550_SERIAL 407 #define CONFIG_SYS_NS16550_REG_SIZE 1 408 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 409 #define CONFIG_SYS_BAUDRATE_TABLE \ 410 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 411 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 412 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 413 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 414 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 415 416 /* Use the HUSH parser */ 417 #define CONFIG_SYS_HUSH_PARSER 418 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 419 420 /* pass open firmware flat tree */ 421 #define CONFIG_OF_LIBFDT 422 #define CONFIG_OF_BOARD_SETUP 423 #define CONFIG_OF_STDOUT_VIA_ALIAS 424 425 /* new uImage format support */ 426 #define CONFIG_FIT 427 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 428 429 /* 430 * I2C 431 */ 432 #define CONFIG_SYS_I2C 433 #define CONFIG_SYS_I2C_FSL 434 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 435 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 437 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 438 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 439 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 440 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 441 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 442 #define CONFIG_SYS_FSL_I2C_SPEED 100000 443 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 444 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 445 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 446 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 447 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 448 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 449 #define I2C_MUX_CH_DEFAULT 0x8 450 451 452 /* 453 * RapidIO 454 */ 455 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 456 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 457 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 458 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 459 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 460 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 461 /* 462 * for slave u-boot IMAGE instored in master memory space, 463 * PHYS must be aligned based on the SIZE 464 */ 465 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 466 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 467 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 468 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 469 /* 470 * for slave UCODE and ENV instored in master memory space, 471 * PHYS must be aligned based on the SIZE 472 */ 473 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 474 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 475 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 476 477 /* slave core release by master*/ 478 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 479 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 480 481 /* 482 * SRIO_PCIE_BOOT - SLAVE 483 */ 484 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 485 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 486 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 487 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 488 #endif 489 490 /* 491 * eSPI - Enhanced SPI 492 */ 493 #ifdef CONFIG_SPI_FLASH 494 #define CONFIG_FSL_ESPI 495 #define CONFIG_SPI_FLASH_STMICRO 496 #define CONFIG_SPI_FLASH_BAR 497 #define CONFIG_CMD_SF 498 #define CONFIG_SF_DEFAULT_SPEED 10000000 499 #define CONFIG_SF_DEFAULT_MODE 0 500 #endif 501 502 /* 503 * General PCI 504 * Memory space is mapped 1-1, but I/O space must start from 0. 505 */ 506 #define CONFIG_PCI /* Enable PCI/PCIE */ 507 #define CONFIG_PCIE1 /* PCIE controler 1 */ 508 #define CONFIG_PCIE2 /* PCIE controler 2 */ 509 #define CONFIG_PCIE3 /* PCIE controler 3 */ 510 #define CONFIG_PCIE4 /* PCIE controler 4 */ 511 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 512 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 513 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 514 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 515 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 516 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 517 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 518 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 519 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 520 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 521 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 522 523 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 524 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 525 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 526 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 527 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 528 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 529 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 530 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 531 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 532 533 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 534 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 535 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 536 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 537 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 538 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 539 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 540 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 541 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 542 543 /* controller 4, Base address 203000 */ 544 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 545 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 546 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 547 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 548 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 549 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 550 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 551 552 #ifdef CONFIG_PCI 553 #define CONFIG_PCI_INDIRECT_BRIDGE 554 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 555 #define CONFIG_NET_MULTI 556 #define CONFIG_E1000 557 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 558 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 559 #define CONFIG_DOS_PARTITION 560 #endif 561 562 /* Qman/Bman */ 563 #ifndef CONFIG_NOBQFMAN 564 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 565 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 566 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 567 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 568 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 569 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 570 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 571 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 572 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 573 574 #define CONFIG_SYS_DPAA_FMAN 575 #define CONFIG_SYS_DPAA_PME 576 #define CONFIG_SYS_PMAN 577 #define CONFIG_SYS_DPAA_DCE 578 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 579 #define CONFIG_SYS_INTERLAKEN 580 581 /* Default address of microcode for the Linux Fman driver */ 582 #if defined(CONFIG_SPIFLASH) 583 /* 584 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 585 * env, so we got 0x110000. 586 */ 587 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 588 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 589 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 590 #define CONFIG_CORTINA_FW_ADDR 0x120000 591 592 #elif defined(CONFIG_SDCARD) 593 /* 594 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 595 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 596 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 597 */ 598 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 599 #define CONFIG_SYS_CORTINA_FW_IN_MMC 600 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 601 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 602 603 #elif defined(CONFIG_NAND) 604 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 605 #define CONFIG_SYS_CORTINA_FW_IN_NAND 606 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 607 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 608 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 609 /* 610 * Slave has no ucode locally, it can fetch this from remote. When implementing 611 * in two corenet boards, slave's ucode could be stored in master's memory 612 * space, the address can be mapped from slave TLB->slave LAW-> 613 * slave SRIO or PCIE outbound window->master inbound window-> 614 * master LAW->the ucode address in master's memory space. 615 */ 616 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 617 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 618 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 619 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 620 #else 621 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 622 #define CONFIG_SYS_CORTINA_FW_IN_NOR 623 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 624 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 625 #endif 626 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 627 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 628 #endif /* CONFIG_NOBQFMAN */ 629 630 #ifdef CONFIG_SYS_DPAA_FMAN 631 #define CONFIG_FMAN_ENET 632 #define CONFIG_PHYLIB_10G 633 #define CONFIG_PHY_CORTINA 634 #define CONFIG_PHY_AQ1202 635 #define CONFIG_PHY_REALTEK 636 #define CONFIG_CORTINA_FW_LENGTH 0x40000 637 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 638 #define RGMII_PHY2_ADDR 0x02 639 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 640 #define CORTINA_PHY_ADDR2 0x0d 641 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 642 #define FM1_10GEC4_PHY_ADDR 0x01 643 #endif 644 645 646 #ifdef CONFIG_FMAN_ENET 647 #define CONFIG_MII /* MII PHY management */ 648 #define CONFIG_ETHPRIME "FM1@DTSEC3" 649 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 650 #endif 651 652 /* 653 * SATA 654 */ 655 #ifdef CONFIG_FSL_SATA_V2 656 #define CONFIG_LIBATA 657 #define CONFIG_FSL_SATA 658 #define CONFIG_SYS_SATA_MAX_DEVICE 2 659 #define CONFIG_SATA1 660 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 661 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 662 #define CONFIG_SATA2 663 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 664 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 665 #define CONFIG_LBA48 666 #define CONFIG_CMD_SATA 667 #define CONFIG_DOS_PARTITION 668 #define CONFIG_CMD_EXT2 669 #endif 670 671 /* 672 * USB 673 */ 674 #ifdef CONFIG_USB_EHCI 675 #define CONFIG_CMD_USB 676 #define CONFIG_USB_STORAGE 677 #define CONFIG_USB_EHCI_FSL 678 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 679 #define CONFIG_CMD_EXT2 680 #define CONFIG_HAS_FSL_DR_USB 681 #endif 682 683 /* 684 * SDHC 685 */ 686 #ifdef CONFIG_MMC 687 #define CONFIG_CMD_MMC 688 #define CONFIG_FSL_ESDHC 689 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 690 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 691 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 692 #define CONFIG_GENERIC_MMC 693 #define CONFIG_CMD_EXT2 694 #define CONFIG_CMD_FAT 695 #define CONFIG_DOS_PARTITION 696 #endif 697 698 /* 699 * Dynamic MTD Partition support with mtdparts 700 */ 701 #ifndef CONFIG_SYS_NO_FLASH 702 #define CONFIG_MTD_DEVICE 703 #define CONFIG_MTD_PARTITIONS 704 #define CONFIG_CMD_MTDPARTS 705 #define CONFIG_FLASH_CFI_MTD 706 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 707 "spi0=spife110000.1" 708 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 709 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 710 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 711 "1m(uboot),5m(kernel),128k(dtb),-(user)" 712 #endif 713 714 /* 715 * Environment 716 */ 717 718 /* 719 * Command line configuration. 720 */ 721 #include <config_cmd_default.h> 722 723 #define CONFIG_CMD_DHCP 724 #define CONFIG_CMD_ELF 725 #define CONFIG_CMD_ERRATA 726 #define CONFIG_CMD_MII 727 #define CONFIG_CMD_I2C 728 #define CONFIG_CMD_PING 729 #define CONFIG_CMD_ECHO 730 #define CONFIG_CMD_SETEXPR 731 #define CONFIG_CMD_REGINFO 732 #define CONFIG_CMD_BDI 733 734 #ifdef CONFIG_PCI 735 #define CONFIG_CMD_PCI 736 #define CONFIG_CMD_NET 737 #endif 738 739 /* 740 * Miscellaneous configurable options 741 */ 742 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 743 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 744 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 745 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 746 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 747 #ifdef CONFIG_CMD_KGDB 748 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 749 #else 750 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 751 #endif 752 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 753 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 754 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 755 756 /* 757 * For booting Linux, the board info and command line data 758 * have to be in the first 64 MB of memory, since this is 759 * the maximum mapped by the Linux kernel during initialization. 760 */ 761 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 762 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 763 764 #ifdef CONFIG_CMD_KGDB 765 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 766 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 767 #endif 768 769 /* 770 * Environment Configuration 771 */ 772 #define CONFIG_ROOTPATH "/opt/nfsroot" 773 #define CONFIG_BOOTFILE "uImage" 774 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 775 776 /* default location for tftp and bootm */ 777 #define CONFIG_LOADADDR 1000000 778 #define CONFIG_BAUDRATE 115200 779 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 780 #define __USB_PHY_TYPE utmi 781 782 #define CONFIG_EXTRA_ENV_SETTINGS \ 783 "hwconfig=fsl_ddr:" \ 784 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 785 "bank_intlv=auto;" \ 786 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 787 "netdev=eth0\0" \ 788 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 789 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 790 "tftpflash=tftpboot $loadaddr $uboot && " \ 791 "protect off $ubootaddr +$filesize && " \ 792 "erase $ubootaddr +$filesize && " \ 793 "cp.b $loadaddr $ubootaddr $filesize && " \ 794 "protect on $ubootaddr +$filesize && " \ 795 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 796 "consoledev=ttyS0\0" \ 797 "ramdiskaddr=2000000\0" \ 798 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 799 "fdtaddr=c00000\0" \ 800 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 801 "bdev=sda3\0" 802 803 /* 804 * For emulation this causes u-boot to jump to the start of the 805 * proof point app code automatically 806 */ 807 #define CONFIG_PROOF_POINTS \ 808 "setenv bootargs root=/dev/$bdev rw " \ 809 "console=$consoledev,$baudrate $othbootargs;" \ 810 "cpu 1 release 0x29000000 - - -;" \ 811 "cpu 2 release 0x29000000 - - -;" \ 812 "cpu 3 release 0x29000000 - - -;" \ 813 "cpu 4 release 0x29000000 - - -;" \ 814 "cpu 5 release 0x29000000 - - -;" \ 815 "cpu 6 release 0x29000000 - - -;" \ 816 "cpu 7 release 0x29000000 - - -;" \ 817 "go 0x29000000" 818 819 #define CONFIG_HVBOOT \ 820 "setenv bootargs config-addr=0x60000000; " \ 821 "bootm 0x01000000 - 0x00f00000" 822 823 #define CONFIG_ALU \ 824 "setenv bootargs root=/dev/$bdev rw " \ 825 "console=$consoledev,$baudrate $othbootargs;" \ 826 "cpu 1 release 0x01000000 - - -;" \ 827 "cpu 2 release 0x01000000 - - -;" \ 828 "cpu 3 release 0x01000000 - - -;" \ 829 "cpu 4 release 0x01000000 - - -;" \ 830 "cpu 5 release 0x01000000 - - -;" \ 831 "cpu 6 release 0x01000000 - - -;" \ 832 "cpu 7 release 0x01000000 - - -;" \ 833 "go 0x01000000" 834 835 #define CONFIG_LINUX \ 836 "setenv bootargs root=/dev/ram rw " \ 837 "console=$consoledev,$baudrate $othbootargs;" \ 838 "setenv ramdiskaddr 0x02000000;" \ 839 "setenv fdtaddr 0x00c00000;" \ 840 "setenv loadaddr 0x1000000;" \ 841 "bootm $loadaddr $ramdiskaddr $fdtaddr" 842 843 #define CONFIG_HDBOOT \ 844 "setenv bootargs root=/dev/$bdev rw " \ 845 "console=$consoledev,$baudrate $othbootargs;" \ 846 "tftp $loadaddr $bootfile;" \ 847 "tftp $fdtaddr $fdtfile;" \ 848 "bootm $loadaddr - $fdtaddr" 849 850 #define CONFIG_NFSBOOTCOMMAND \ 851 "setenv bootargs root=/dev/nfs rw " \ 852 "nfsroot=$serverip:$rootpath " \ 853 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 854 "console=$consoledev,$baudrate $othbootargs;" \ 855 "tftp $loadaddr $bootfile;" \ 856 "tftp $fdtaddr $fdtfile;" \ 857 "bootm $loadaddr - $fdtaddr" 858 859 #define CONFIG_RAMBOOTCOMMAND \ 860 "setenv bootargs root=/dev/ram rw " \ 861 "console=$consoledev,$baudrate $othbootargs;" \ 862 "tftp $ramdiskaddr $ramdiskfile;" \ 863 "tftp $loadaddr $bootfile;" \ 864 "tftp $fdtaddr $fdtfile;" \ 865 "bootm $loadaddr $ramdiskaddr $fdtaddr" 866 867 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 868 869 #ifdef CONFIG_SECURE_BOOT 870 #include <asm/fsl_secure_boot.h> 871 #undef CONFIG_CMD_USB 872 #endif 873 874 #endif /* __T2080RDB_H */ 875