1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_T2080RDB 17 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 18 #define CONFIG_MMC 19 #define CONFIG_SPI_FLASH 20 #define CONFIG_USB_EHCI 21 #define CONFIG_FSL_SATA_V2 22 23 /* High Level Configuration Options */ 24 #define CONFIG_PHYS_64BIT 25 #define CONFIG_BOOKE 26 #define CONFIG_E500 /* BOOKE e500 family */ 27 #define CONFIG_E500MC /* BOOKE e500mc family */ 28 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 29 #define CONFIG_MP /* support multiple processors */ 30 #define CONFIG_ENABLE_36BIT_PHYS 31 32 #ifdef CONFIG_PHYS_64BIT 33 #define CONFIG_ADDR_MAP 1 34 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 35 #endif 36 37 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 38 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 39 #define CONFIG_FSL_IFC /* Enable IFC Support */ 40 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 41 #define CONFIG_FSL_LAW /* Use common FSL init code */ 42 #define CONFIG_ENV_OVERWRITE 43 44 #ifdef CONFIG_RAMBOOT_PBL 45 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 46 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 47 48 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 49 #define CONFIG_SPL_ENV_SUPPORT 50 #define CONFIG_SPL_SERIAL_SUPPORT 51 #define CONFIG_SPL_FLUSH_IMAGE 52 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 53 #define CONFIG_SPL_LIBGENERIC_SUPPORT 54 #define CONFIG_SPL_LIBCOMMON_SUPPORT 55 #define CONFIG_SPL_I2C_SUPPORT 56 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 57 #define CONFIG_FSL_LAW /* Use common FSL init code */ 58 #define CONFIG_SYS_TEXT_BASE 0x00201000 59 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 60 #define CONFIG_SPL_PAD_TO 0x40000 61 #define CONFIG_SPL_MAX_SIZE 0x28000 62 #define RESET_VECTOR_OFFSET 0x27FFC 63 #define BOOT_PAGE_OFFSET 0x27000 64 #ifdef CONFIG_SPL_BUILD 65 #define CONFIG_SPL_SKIP_RELOCATE 66 #define CONFIG_SPL_COMMON_INIT_DDR 67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 68 #define CONFIG_SYS_NO_FLASH 69 #endif 70 71 #ifdef CONFIG_NAND 72 #define CONFIG_SPL_NAND_SUPPORT 73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 74 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 75 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 78 #define CONFIG_SPL_NAND_BOOT 79 #endif 80 81 #ifdef CONFIG_SPIFLASH 82 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 83 #define CONFIG_SPL_SPI_SUPPORT 84 #define CONFIG_SPL_SPI_FLASH_SUPPORT 85 #define CONFIG_SPL_SPI_FLASH_MINIMAL 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 88 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 91 #ifndef CONFIG_SPL_BUILD 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #endif 94 #define CONFIG_SPL_SPI_BOOT 95 #endif 96 97 #ifdef CONFIG_SDCARD 98 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 99 #define CONFIG_SPL_MMC_SUPPORT 100 #define CONFIG_SPL_MMC_MINIMAL 101 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 102 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 103 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 104 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 105 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 106 #ifndef CONFIG_SPL_BUILD 107 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 108 #endif 109 #define CONFIG_SPL_MMC_BOOT 110 #endif 111 112 #endif /* CONFIG_RAMBOOT_PBL */ 113 114 #define CONFIG_SRIO_PCIE_BOOT_MASTER 115 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 116 /* Set 1M boot space */ 117 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 118 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 119 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 120 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 121 #define CONFIG_SYS_NO_FLASH 122 #endif 123 124 #ifndef CONFIG_SYS_TEXT_BASE 125 #define CONFIG_SYS_TEXT_BASE 0xeff40000 126 #endif 127 128 #ifndef CONFIG_RESET_VECTOR_ADDRESS 129 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 130 #endif 131 132 /* 133 * These can be toggled for performance analysis, otherwise use default. 134 */ 135 #define CONFIG_SYS_CACHE_STASHING 136 #define CONFIG_BTB /* toggle branch predition */ 137 #define CONFIG_DDR_ECC 138 #ifdef CONFIG_DDR_ECC 139 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 140 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 141 #endif 142 143 #ifndef CONFIG_SYS_NO_FLASH 144 #define CONFIG_FLASH_CFI_DRIVER 145 #define CONFIG_SYS_FLASH_CFI 146 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 147 #endif 148 149 #if defined(CONFIG_SPIFLASH) 150 #define CONFIG_SYS_EXTRA_ENV_RELOC 151 #define CONFIG_ENV_IS_IN_SPI_FLASH 152 #define CONFIG_ENV_SPI_BUS 0 153 #define CONFIG_ENV_SPI_CS 0 154 #define CONFIG_ENV_SPI_MAX_HZ 10000000 155 #define CONFIG_ENV_SPI_MODE 0 156 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 157 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 158 #define CONFIG_ENV_SECT_SIZE 0x10000 159 #elif defined(CONFIG_SDCARD) 160 #define CONFIG_SYS_EXTRA_ENV_RELOC 161 #define CONFIG_ENV_IS_IN_MMC 162 #define CONFIG_SYS_MMC_ENV_DEV 0 163 #define CONFIG_ENV_SIZE 0x2000 164 #define CONFIG_ENV_OFFSET (512 * 0x800) 165 #elif defined(CONFIG_NAND) 166 #define CONFIG_SYS_EXTRA_ENV_RELOC 167 #define CONFIG_ENV_IS_IN_NAND 168 #define CONFIG_ENV_SIZE 0x2000 169 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 170 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 171 #define CONFIG_ENV_IS_IN_REMOTE 172 #define CONFIG_ENV_ADDR 0xffe20000 173 #define CONFIG_ENV_SIZE 0x2000 174 #elif defined(CONFIG_ENV_IS_NOWHERE) 175 #define CONFIG_ENV_SIZE 0x2000 176 #else 177 #define CONFIG_ENV_IS_IN_FLASH 178 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 179 #define CONFIG_ENV_SIZE 0x2000 180 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 181 #endif 182 183 #ifndef __ASSEMBLY__ 184 unsigned long get_board_sys_clk(void); 185 unsigned long get_board_ddr_clk(void); 186 #endif 187 188 #define CONFIG_SYS_CLK_FREQ 66660000 189 #define CONFIG_DDR_CLK_FREQ 133330000 190 191 /* 192 * Config the L3 Cache as L3 SRAM 193 */ 194 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 195 #define CONFIG_SYS_L3_SIZE (512 << 10) 196 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 197 #ifdef CONFIG_RAMBOOT_PBL 198 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 199 #endif 200 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 201 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 202 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 203 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 204 205 #define CONFIG_SYS_DCSRBAR 0xf0000000 206 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 207 208 /* EEPROM */ 209 #define CONFIG_ID_EEPROM 210 #define CONFIG_SYS_I2C_EEPROM_NXID 211 #define CONFIG_SYS_EEPROM_BUS_NUM 0 212 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 213 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 214 215 /* 216 * DDR Setup 217 */ 218 #define CONFIG_VERY_BIG_RAM 219 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 220 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 221 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 222 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 223 #define CONFIG_DDR_SPD 224 #define CONFIG_SYS_FSL_DDR3 225 #undef CONFIG_FSL_DDR_INTERACTIVE 226 #define CONFIG_SYS_SPD_BUS_NUM 0 227 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 228 #define SPD_EEPROM_ADDRESS1 0x51 229 #define SPD_EEPROM_ADDRESS2 0x52 230 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 231 #define CTRL_INTLV_PREFERED cacheline 232 233 /* 234 * IFC Definitions 235 */ 236 #define CONFIG_SYS_FLASH_BASE 0xe8000000 237 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 238 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 239 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 240 CSPR_PORT_SIZE_16 | \ 241 CSPR_MSEL_NOR | \ 242 CSPR_V) 243 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 244 245 /* NOR Flash Timing Params */ 246 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 247 248 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 249 FTIM0_NOR_TEADC(0x5) | \ 250 FTIM0_NOR_TEAHC(0x5)) 251 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 252 FTIM1_NOR_TRAD_NOR(0x1A) |\ 253 FTIM1_NOR_TSEQRAD_NOR(0x13)) 254 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 255 FTIM2_NOR_TCH(0x4) | \ 256 FTIM2_NOR_TWPH(0x0E) | \ 257 FTIM2_NOR_TWP(0x1c)) 258 #define CONFIG_SYS_NOR_FTIM3 0x0 259 260 #define CONFIG_SYS_FLASH_QUIET_TEST 261 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 262 263 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 264 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 265 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 266 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 267 #define CONFIG_SYS_FLASH_EMPTY_INFO 268 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 269 270 /* CPLD on IFC */ 271 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 272 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 273 #define CONFIG_SYS_CSPR2_EXT (0xf) 274 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 275 | CSPR_PORT_SIZE_8 \ 276 | CSPR_MSEL_GPCM \ 277 | CSPR_V) 278 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 279 #define CONFIG_SYS_CSOR2 0x0 280 281 /* CPLD Timing parameters for IFC CS2 */ 282 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 283 FTIM0_GPCM_TEADC(0x0e) | \ 284 FTIM0_GPCM_TEAHC(0x0e)) 285 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 286 FTIM1_GPCM_TRAD(0x1f)) 287 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 288 FTIM2_GPCM_TCH(0x8) | \ 289 FTIM2_GPCM_TWP(0x1f)) 290 #define CONFIG_SYS_CS2_FTIM3 0x0 291 292 /* NAND Flash on IFC */ 293 #define CONFIG_NAND_FSL_IFC 294 #define CONFIG_SYS_NAND_BASE 0xff800000 295 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 296 297 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 298 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 299 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 300 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 301 | CSPR_V) 302 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 303 304 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 305 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 306 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 307 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 308 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 309 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 310 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 311 312 #define CONFIG_SYS_NAND_ONFI_DETECTION 313 314 /* ONFI NAND Flash mode0 Timing Params */ 315 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 316 FTIM0_NAND_TWP(0x18) | \ 317 FTIM0_NAND_TWCHT(0x07) | \ 318 FTIM0_NAND_TWH(0x0a)) 319 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 320 FTIM1_NAND_TWBE(0x39) | \ 321 FTIM1_NAND_TRR(0x0e) | \ 322 FTIM1_NAND_TRP(0x18)) 323 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 324 FTIM2_NAND_TREH(0x0a) | \ 325 FTIM2_NAND_TWHRE(0x1e)) 326 #define CONFIG_SYS_NAND_FTIM3 0x0 327 328 #define CONFIG_SYS_NAND_DDR_LAW 11 329 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 330 #define CONFIG_SYS_MAX_NAND_DEVICE 1 331 #define CONFIG_CMD_NAND 332 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 333 334 #if defined(CONFIG_NAND) 335 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 336 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 337 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 338 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 339 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 340 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 341 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 342 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 343 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 344 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 345 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #else 352 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 353 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 354 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 355 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 356 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 357 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 358 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 359 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 360 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 361 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 362 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 363 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 364 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 365 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 366 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 367 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 368 #endif 369 370 #if defined(CONFIG_RAMBOOT_PBL) 371 #define CONFIG_SYS_RAMBOOT 372 #endif 373 374 #ifdef CONFIG_SPL_BUILD 375 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 376 #else 377 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 378 #endif 379 380 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 381 #define CONFIG_MISC_INIT_R 382 #define CONFIG_HWCONFIG 383 384 /* define to use L1 as initial stack */ 385 #define CONFIG_L1_INIT_RAM 386 #define CONFIG_SYS_INIT_RAM_LOCK 387 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 389 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 390 /* The assembler doesn't like typecast */ 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 392 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 393 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 394 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 395 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 396 GENERATED_GBL_DATA_SIZE) 397 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 398 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 399 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 400 401 /* 402 * Serial Port 403 */ 404 #define CONFIG_CONS_INDEX 1 405 #define CONFIG_SYS_NS16550 406 #define CONFIG_SYS_NS16550_SERIAL 407 #define CONFIG_SYS_NS16550_REG_SIZE 1 408 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 409 #define CONFIG_SYS_BAUDRATE_TABLE \ 410 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 411 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 412 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 413 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 414 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 415 416 /* Use the HUSH parser */ 417 #define CONFIG_SYS_HUSH_PARSER 418 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 419 420 /* pass open firmware flat tree */ 421 #define CONFIG_OF_LIBFDT 422 #define CONFIG_OF_BOARD_SETUP 423 #define CONFIG_OF_STDOUT_VIA_ALIAS 424 425 /* new uImage format support */ 426 #define CONFIG_FIT 427 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 428 429 /* 430 * I2C 431 */ 432 #define CONFIG_SYS_I2C 433 #define CONFIG_SYS_I2C_FSL 434 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 435 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 437 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 438 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 439 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 440 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 441 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 442 #define CONFIG_SYS_FSL_I2C_SPEED 100000 443 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 444 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 445 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 446 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 447 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 448 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 449 #define I2C_MUX_CH_DEFAULT 0x8 450 451 452 /* 453 * RapidIO 454 */ 455 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 456 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 457 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 458 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 459 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 460 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 461 /* 462 * for slave u-boot IMAGE instored in master memory space, 463 * PHYS must be aligned based on the SIZE 464 */ 465 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 466 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 467 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 468 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 469 /* 470 * for slave UCODE and ENV instored in master memory space, 471 * PHYS must be aligned based on the SIZE 472 */ 473 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 474 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 475 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 476 477 /* slave core release by master*/ 478 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 479 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 480 481 /* 482 * SRIO_PCIE_BOOT - SLAVE 483 */ 484 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 485 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 486 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 487 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 488 #endif 489 490 /* 491 * eSPI - Enhanced SPI 492 */ 493 #ifdef CONFIG_SPI_FLASH 494 #define CONFIG_FSL_ESPI 495 #define CONFIG_SPI_FLASH_STMICRO 496 #define CONFIG_SPI_FLASH_BAR 497 #define CONFIG_CMD_SF 498 #define CONFIG_SF_DEFAULT_SPEED 10000000 499 #define CONFIG_SF_DEFAULT_MODE 0 500 #endif 501 502 /* 503 * General PCI 504 * Memory space is mapped 1-1, but I/O space must start from 0. 505 */ 506 #define CONFIG_PCI /* Enable PCI/PCIE */ 507 #define CONFIG_PCIE1 /* PCIE controler 1 */ 508 #define CONFIG_PCIE2 /* PCIE controler 2 */ 509 #define CONFIG_PCIE3 /* PCIE controler 3 */ 510 #define CONFIG_PCIE4 /* PCIE controler 4 */ 511 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 512 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 513 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 514 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 515 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 516 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 517 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 518 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 519 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 520 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 521 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 522 523 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 524 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 525 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 526 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 527 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 528 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 529 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 530 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 531 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 532 533 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 534 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 535 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 536 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 537 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 538 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 539 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 540 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 541 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 542 543 /* controller 4, Base address 203000 */ 544 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 545 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 546 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 547 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 548 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 549 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 550 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 551 552 #ifdef CONFIG_PCI 553 #define CONFIG_PCI_INDIRECT_BRIDGE 554 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 555 #define CONFIG_NET_MULTI 556 #define CONFIG_E1000 557 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 558 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 559 #define CONFIG_DOS_PARTITION 560 #endif 561 562 /* Qman/Bman */ 563 #ifndef CONFIG_NOBQFMAN 564 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 565 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 566 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 567 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 568 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 569 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 570 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 571 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 572 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 573 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 574 CONFIG_SYS_BMAN_CENA_SIZE) 575 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 576 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 577 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 578 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 579 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 580 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 581 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 582 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 583 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 584 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 585 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 586 CONFIG_SYS_QMAN_CENA_SIZE) 587 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 588 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 589 590 #define CONFIG_SYS_DPAA_FMAN 591 #define CONFIG_SYS_DPAA_PME 592 #define CONFIG_SYS_PMAN 593 #define CONFIG_SYS_DPAA_DCE 594 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 595 #define CONFIG_SYS_INTERLAKEN 596 597 /* Default address of microcode for the Linux Fman driver */ 598 #if defined(CONFIG_SPIFLASH) 599 /* 600 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 601 * env, so we got 0x110000. 602 */ 603 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 604 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 605 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 606 #define CONFIG_CORTINA_FW_ADDR 0x120000 607 608 #elif defined(CONFIG_SDCARD) 609 /* 610 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 611 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 612 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 613 */ 614 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 615 #define CONFIG_SYS_CORTINA_FW_IN_MMC 616 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 617 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 618 619 #elif defined(CONFIG_NAND) 620 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 621 #define CONFIG_SYS_CORTINA_FW_IN_NAND 622 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 623 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 624 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 625 /* 626 * Slave has no ucode locally, it can fetch this from remote. When implementing 627 * in two corenet boards, slave's ucode could be stored in master's memory 628 * space, the address can be mapped from slave TLB->slave LAW-> 629 * slave SRIO or PCIE outbound window->master inbound window-> 630 * master LAW->the ucode address in master's memory space. 631 */ 632 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 633 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 634 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 635 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 636 #else 637 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 638 #define CONFIG_SYS_CORTINA_FW_IN_NOR 639 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 640 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 641 #endif 642 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 643 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 644 #endif /* CONFIG_NOBQFMAN */ 645 646 #ifdef CONFIG_SYS_DPAA_FMAN 647 #define CONFIG_FMAN_ENET 648 #define CONFIG_PHYLIB_10G 649 #define CONFIG_PHY_CORTINA 650 #define CONFIG_PHY_AQ1202 651 #define CONFIG_PHY_REALTEK 652 #define CONFIG_CORTINA_FW_LENGTH 0x40000 653 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 654 #define RGMII_PHY2_ADDR 0x02 655 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 656 #define CORTINA_PHY_ADDR2 0x0d 657 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 658 #define FM1_10GEC4_PHY_ADDR 0x01 659 #endif 660 661 662 #ifdef CONFIG_FMAN_ENET 663 #define CONFIG_MII /* MII PHY management */ 664 #define CONFIG_ETHPRIME "FM1@DTSEC3" 665 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 666 #endif 667 668 /* 669 * SATA 670 */ 671 #ifdef CONFIG_FSL_SATA_V2 672 #define CONFIG_LIBATA 673 #define CONFIG_FSL_SATA 674 #define CONFIG_SYS_SATA_MAX_DEVICE 2 675 #define CONFIG_SATA1 676 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 677 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 678 #define CONFIG_SATA2 679 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 680 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 681 #define CONFIG_LBA48 682 #define CONFIG_CMD_SATA 683 #define CONFIG_DOS_PARTITION 684 #define CONFIG_CMD_EXT2 685 #endif 686 687 /* 688 * USB 689 */ 690 #ifdef CONFIG_USB_EHCI 691 #define CONFIG_CMD_USB 692 #define CONFIG_USB_STORAGE 693 #define CONFIG_USB_EHCI_FSL 694 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 695 #define CONFIG_CMD_EXT2 696 #define CONFIG_HAS_FSL_DR_USB 697 #endif 698 699 /* 700 * SDHC 701 */ 702 #ifdef CONFIG_MMC 703 #define CONFIG_CMD_MMC 704 #define CONFIG_FSL_ESDHC 705 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 706 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 707 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 708 #define CONFIG_GENERIC_MMC 709 #define CONFIG_CMD_EXT2 710 #define CONFIG_CMD_FAT 711 #define CONFIG_DOS_PARTITION 712 #endif 713 714 /* 715 * Dynamic MTD Partition support with mtdparts 716 */ 717 #ifndef CONFIG_SYS_NO_FLASH 718 #define CONFIG_MTD_DEVICE 719 #define CONFIG_MTD_PARTITIONS 720 #define CONFIG_CMD_MTDPARTS 721 #define CONFIG_FLASH_CFI_MTD 722 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 723 "spi0=spife110000.1" 724 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 725 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 726 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 727 "1m(uboot),5m(kernel),128k(dtb),-(user)" 728 #endif 729 730 /* 731 * Environment 732 */ 733 734 /* 735 * Command line configuration. 736 */ 737 #include <config_cmd_default.h> 738 739 #define CONFIG_CMD_DHCP 740 #define CONFIG_CMD_ELF 741 #define CONFIG_CMD_ERRATA 742 #define CONFIG_CMD_MII 743 #define CONFIG_CMD_I2C 744 #define CONFIG_CMD_PING 745 #define CONFIG_CMD_ECHO 746 #define CONFIG_CMD_SETEXPR 747 #define CONFIG_CMD_REGINFO 748 #define CONFIG_CMD_BDI 749 750 #ifdef CONFIG_PCI 751 #define CONFIG_CMD_PCI 752 #define CONFIG_CMD_NET 753 #endif 754 755 /* Hash command with SHA acceleration supported in hardware */ 756 #ifdef CONFIG_FSL_CAAM 757 #define CONFIG_CMD_HASH 758 #define CONFIG_SHA_HW_ACCEL 759 #endif 760 761 /* 762 * Miscellaneous configurable options 763 */ 764 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 765 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 766 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 767 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 768 #ifdef CONFIG_CMD_KGDB 769 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 770 #else 771 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 772 #endif 773 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 774 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 775 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 776 777 /* 778 * For booting Linux, the board info and command line data 779 * have to be in the first 64 MB of memory, since this is 780 * the maximum mapped by the Linux kernel during initialization. 781 */ 782 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 783 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 784 785 #ifdef CONFIG_CMD_KGDB 786 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 787 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 788 #endif 789 790 /* 791 * Environment Configuration 792 */ 793 #define CONFIG_ROOTPATH "/opt/nfsroot" 794 #define CONFIG_BOOTFILE "uImage" 795 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 796 797 /* default location for tftp and bootm */ 798 #define CONFIG_LOADADDR 1000000 799 #define CONFIG_BAUDRATE 115200 800 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 801 #define __USB_PHY_TYPE utmi 802 803 #define CONFIG_EXTRA_ENV_SETTINGS \ 804 "hwconfig=fsl_ddr:" \ 805 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 806 "bank_intlv=auto;" \ 807 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 808 "netdev=eth0\0" \ 809 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 810 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 811 "tftpflash=tftpboot $loadaddr $uboot && " \ 812 "protect off $ubootaddr +$filesize && " \ 813 "erase $ubootaddr +$filesize && " \ 814 "cp.b $loadaddr $ubootaddr $filesize && " \ 815 "protect on $ubootaddr +$filesize && " \ 816 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 817 "consoledev=ttyS0\0" \ 818 "ramdiskaddr=2000000\0" \ 819 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 820 "fdtaddr=c00000\0" \ 821 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 822 "bdev=sda3\0" 823 824 /* 825 * For emulation this causes u-boot to jump to the start of the 826 * proof point app code automatically 827 */ 828 #define CONFIG_PROOF_POINTS \ 829 "setenv bootargs root=/dev/$bdev rw " \ 830 "console=$consoledev,$baudrate $othbootargs;" \ 831 "cpu 1 release 0x29000000 - - -;" \ 832 "cpu 2 release 0x29000000 - - -;" \ 833 "cpu 3 release 0x29000000 - - -;" \ 834 "cpu 4 release 0x29000000 - - -;" \ 835 "cpu 5 release 0x29000000 - - -;" \ 836 "cpu 6 release 0x29000000 - - -;" \ 837 "cpu 7 release 0x29000000 - - -;" \ 838 "go 0x29000000" 839 840 #define CONFIG_HVBOOT \ 841 "setenv bootargs config-addr=0x60000000; " \ 842 "bootm 0x01000000 - 0x00f00000" 843 844 #define CONFIG_ALU \ 845 "setenv bootargs root=/dev/$bdev rw " \ 846 "console=$consoledev,$baudrate $othbootargs;" \ 847 "cpu 1 release 0x01000000 - - -;" \ 848 "cpu 2 release 0x01000000 - - -;" \ 849 "cpu 3 release 0x01000000 - - -;" \ 850 "cpu 4 release 0x01000000 - - -;" \ 851 "cpu 5 release 0x01000000 - - -;" \ 852 "cpu 6 release 0x01000000 - - -;" \ 853 "cpu 7 release 0x01000000 - - -;" \ 854 "go 0x01000000" 855 856 #define CONFIG_LINUX \ 857 "setenv bootargs root=/dev/ram rw " \ 858 "console=$consoledev,$baudrate $othbootargs;" \ 859 "setenv ramdiskaddr 0x02000000;" \ 860 "setenv fdtaddr 0x00c00000;" \ 861 "setenv loadaddr 0x1000000;" \ 862 "bootm $loadaddr $ramdiskaddr $fdtaddr" 863 864 #define CONFIG_HDBOOT \ 865 "setenv bootargs root=/dev/$bdev rw " \ 866 "console=$consoledev,$baudrate $othbootargs;" \ 867 "tftp $loadaddr $bootfile;" \ 868 "tftp $fdtaddr $fdtfile;" \ 869 "bootm $loadaddr - $fdtaddr" 870 871 #define CONFIG_NFSBOOTCOMMAND \ 872 "setenv bootargs root=/dev/nfs rw " \ 873 "nfsroot=$serverip:$rootpath " \ 874 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 875 "console=$consoledev,$baudrate $othbootargs;" \ 876 "tftp $loadaddr $bootfile;" \ 877 "tftp $fdtaddr $fdtfile;" \ 878 "bootm $loadaddr - $fdtaddr" 879 880 #define CONFIG_RAMBOOTCOMMAND \ 881 "setenv bootargs root=/dev/ram rw " \ 882 "console=$consoledev,$baudrate $othbootargs;" \ 883 "tftp $ramdiskaddr $ramdiskfile;" \ 884 "tftp $loadaddr $bootfile;" \ 885 "tftp $fdtaddr $fdtfile;" \ 886 "bootm $loadaddr $ramdiskaddr $fdtaddr" 887 888 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 889 890 #ifdef CONFIG_SECURE_BOOT 891 #include <asm/fsl_secure_boot.h> 892 #define CONFIG_CMD_BLOB 893 #undef CONFIG_CMD_USB 894 #endif 895 896 #endif /* __T2080RDB_H */ 897