1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T2080 RDB/PCIe board configuration file 8 */ 9 10 #ifndef __T2080RDB_H 11 #define __T2080RDB_H 12 13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 14 #define CONFIG_FSL_SATA_V2 15 16 /* High Level Configuration Options */ 17 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 18 #define CONFIG_ENABLE_36BIT_PHYS 19 20 #ifdef CONFIG_PHYS_64BIT 21 #define CONFIG_ADDR_MAP 1 22 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 23 #endif 24 25 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 26 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 27 #define CONFIG_ENV_OVERWRITE 28 29 #ifdef CONFIG_RAMBOOT_PBL 30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 31 32 #define CONFIG_SPL_FLUSH_IMAGE 33 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 34 #define CONFIG_SPL_PAD_TO 0x40000 35 #define CONFIG_SPL_MAX_SIZE 0x28000 36 #define RESET_VECTOR_OFFSET 0x27FFC 37 #define BOOT_PAGE_OFFSET 0x27000 38 #ifdef CONFIG_SPL_BUILD 39 #define CONFIG_SPL_SKIP_RELOCATE 40 #define CONFIG_SPL_COMMON_INIT_DDR 41 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 42 #endif 43 44 #ifdef CONFIG_NAND 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 46 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 47 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 48 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 49 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 51 #define CONFIG_SPL_NAND_BOOT 52 #endif 53 54 #ifdef CONFIG_SPIFLASH 55 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 56 #define CONFIG_SPL_SPI_FLASH_MINIMAL 57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 60 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 62 #ifndef CONFIG_SPL_BUILD 63 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 64 #endif 65 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 66 #define CONFIG_SPL_SPI_BOOT 67 #endif 68 69 #ifdef CONFIG_SDCARD 70 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 71 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 72 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 73 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 74 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 76 #ifndef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 78 #endif 79 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 80 #define CONFIG_SPL_MMC_BOOT 81 #endif 82 83 #endif /* CONFIG_RAMBOOT_PBL */ 84 85 #define CONFIG_SRIO_PCIE_BOOT_MASTER 86 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 87 /* Set 1M boot space */ 88 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 89 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 90 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 91 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 92 #endif 93 94 #ifndef CONFIG_RESET_VECTOR_ADDRESS 95 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 96 #endif 97 98 /* 99 * These can be toggled for performance analysis, otherwise use default. 100 */ 101 #define CONFIG_SYS_CACHE_STASHING 102 #define CONFIG_BTB /* toggle branch predition */ 103 #define CONFIG_DDR_ECC 104 #ifdef CONFIG_DDR_ECC 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 106 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 107 #endif 108 109 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 110 #define CONFIG_SYS_MEMTEST_END 0x00400000 111 112 #ifdef CONFIG_MTD_NOR_FLASH 113 #define CONFIG_FLASH_CFI_DRIVER 114 #define CONFIG_SYS_FLASH_CFI 115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 116 #endif 117 118 #if defined(CONFIG_SPIFLASH) 119 #define CONFIG_SYS_EXTRA_ENV_RELOC 120 #define CONFIG_ENV_SPI_BUS 0 121 #define CONFIG_ENV_SPI_CS 0 122 #define CONFIG_ENV_SPI_MAX_HZ 10000000 123 #define CONFIG_ENV_SPI_MODE 0 124 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 125 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 126 #define CONFIG_ENV_SECT_SIZE 0x10000 127 #elif defined(CONFIG_SDCARD) 128 #define CONFIG_SYS_EXTRA_ENV_RELOC 129 #define CONFIG_SYS_MMC_ENV_DEV 0 130 #define CONFIG_ENV_SIZE 0x2000 131 #define CONFIG_ENV_OFFSET (512 * 0x800) 132 #elif defined(CONFIG_NAND) 133 #define CONFIG_SYS_EXTRA_ENV_RELOC 134 #define CONFIG_ENV_SIZE 0x2000 135 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 136 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 137 #define CONFIG_ENV_ADDR 0xffe20000 138 #define CONFIG_ENV_SIZE 0x2000 139 #elif defined(CONFIG_ENV_IS_NOWHERE) 140 #define CONFIG_ENV_SIZE 0x2000 141 #else 142 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 143 #define CONFIG_ENV_SIZE 0x2000 144 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 145 #endif 146 147 #ifndef __ASSEMBLY__ 148 unsigned long get_board_sys_clk(void); 149 unsigned long get_board_ddr_clk(void); 150 #endif 151 152 #define CONFIG_SYS_CLK_FREQ 66660000 153 #define CONFIG_DDR_CLK_FREQ 133330000 154 155 /* 156 * Config the L3 Cache as L3 SRAM 157 */ 158 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 159 #define CONFIG_SYS_L3_SIZE (512 << 10) 160 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 161 #ifdef CONFIG_RAMBOOT_PBL 162 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 163 #endif 164 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 165 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 166 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 167 168 #define CONFIG_SYS_DCSRBAR 0xf0000000 169 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 170 171 /* EEPROM */ 172 #define CONFIG_ID_EEPROM 173 #define CONFIG_SYS_I2C_EEPROM_NXID 174 #define CONFIG_SYS_EEPROM_BUS_NUM 0 175 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 176 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 177 178 /* 179 * DDR Setup 180 */ 181 #define CONFIG_VERY_BIG_RAM 182 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 183 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 184 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 185 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 186 #define CONFIG_DDR_SPD 187 #undef CONFIG_FSL_DDR_INTERACTIVE 188 #define CONFIG_SYS_SPD_BUS_NUM 0 189 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 190 #define SPD_EEPROM_ADDRESS1 0x51 191 #define SPD_EEPROM_ADDRESS2 0x52 192 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 193 #define CTRL_INTLV_PREFERED cacheline 194 195 /* 196 * IFC Definitions 197 */ 198 #define CONFIG_SYS_FLASH_BASE 0xe8000000 199 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 200 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 201 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 202 CSPR_PORT_SIZE_16 | \ 203 CSPR_MSEL_NOR | \ 204 CSPR_V) 205 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 206 207 /* NOR Flash Timing Params */ 208 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 209 210 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 211 FTIM0_NOR_TEADC(0x5) | \ 212 FTIM0_NOR_TEAHC(0x5)) 213 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 214 FTIM1_NOR_TRAD_NOR(0x1A) |\ 215 FTIM1_NOR_TSEQRAD_NOR(0x13)) 216 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 217 FTIM2_NOR_TCH(0x4) | \ 218 FTIM2_NOR_TWPH(0x0E) | \ 219 FTIM2_NOR_TWP(0x1c)) 220 #define CONFIG_SYS_NOR_FTIM3 0x0 221 222 #define CONFIG_SYS_FLASH_QUIET_TEST 223 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 224 225 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 226 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 227 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 228 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 229 #define CONFIG_SYS_FLASH_EMPTY_INFO 230 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 231 232 /* CPLD on IFC */ 233 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 234 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 235 #define CONFIG_SYS_CSPR2_EXT (0xf) 236 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 237 | CSPR_PORT_SIZE_8 \ 238 | CSPR_MSEL_GPCM \ 239 | CSPR_V) 240 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 241 #define CONFIG_SYS_CSOR2 0x0 242 243 /* CPLD Timing parameters for IFC CS2 */ 244 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 245 FTIM0_GPCM_TEADC(0x0e) | \ 246 FTIM0_GPCM_TEAHC(0x0e)) 247 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 248 FTIM1_GPCM_TRAD(0x1f)) 249 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 250 FTIM2_GPCM_TCH(0x8) | \ 251 FTIM2_GPCM_TWP(0x1f)) 252 #define CONFIG_SYS_CS2_FTIM3 0x0 253 254 /* NAND Flash on IFC */ 255 #define CONFIG_NAND_FSL_IFC 256 #define CONFIG_SYS_NAND_BASE 0xff800000 257 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 258 259 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 260 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 261 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 262 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 263 | CSPR_V) 264 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 265 266 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 267 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 268 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 269 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 270 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 271 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 272 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 273 274 #define CONFIG_SYS_NAND_ONFI_DETECTION 275 276 /* ONFI NAND Flash mode0 Timing Params */ 277 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 278 FTIM0_NAND_TWP(0x18) | \ 279 FTIM0_NAND_TWCHT(0x07) | \ 280 FTIM0_NAND_TWH(0x0a)) 281 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 282 FTIM1_NAND_TWBE(0x39) | \ 283 FTIM1_NAND_TRR(0x0e) | \ 284 FTIM1_NAND_TRP(0x18)) 285 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 286 FTIM2_NAND_TREH(0x0a) | \ 287 FTIM2_NAND_TWHRE(0x1e)) 288 #define CONFIG_SYS_NAND_FTIM3 0x0 289 290 #define CONFIG_SYS_NAND_DDR_LAW 11 291 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 292 #define CONFIG_SYS_MAX_NAND_DEVICE 1 293 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 294 295 #if defined(CONFIG_NAND) 296 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 297 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 298 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 299 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 300 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 301 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 302 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 303 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 304 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 305 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 306 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 307 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 308 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 309 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 310 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 311 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 312 #else 313 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 314 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 315 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 316 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 317 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 318 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 319 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 320 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 321 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 322 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 323 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 324 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 325 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 326 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 327 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 328 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 329 #endif 330 331 #if defined(CONFIG_RAMBOOT_PBL) 332 #define CONFIG_SYS_RAMBOOT 333 #endif 334 335 #ifdef CONFIG_SPL_BUILD 336 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 337 #else 338 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 339 #endif 340 341 #define CONFIG_HWCONFIG 342 343 /* define to use L1 as initial stack */ 344 #define CONFIG_L1_INIT_RAM 345 #define CONFIG_SYS_INIT_RAM_LOCK 346 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 347 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 348 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 349 /* The assembler doesn't like typecast */ 350 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 351 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 352 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 353 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 354 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 355 GENERATED_GBL_DATA_SIZE) 356 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 357 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 358 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 359 360 /* 361 * Serial Port 362 */ 363 #define CONFIG_SYS_NS16550_SERIAL 364 #define CONFIG_SYS_NS16550_REG_SIZE 1 365 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 366 #define CONFIG_SYS_BAUDRATE_TABLE \ 367 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 368 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 369 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 370 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 371 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 372 373 /* 374 * I2C 375 */ 376 #define CONFIG_SYS_I2C 377 #define CONFIG_SYS_I2C_FSL 378 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 379 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 380 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 381 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 382 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 383 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 384 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 385 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 386 #define CONFIG_SYS_FSL_I2C_SPEED 100000 387 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 388 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 389 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 390 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 391 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 392 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 393 #define I2C_MUX_CH_DEFAULT 0x8 394 395 #define I2C_MUX_CH_VOL_MONITOR 0xa 396 397 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 398 #ifndef CONFIG_SPL_BUILD 399 #define CONFIG_VID 400 #endif 401 #define CONFIG_VOL_MONITOR_IR36021_SET 402 #define CONFIG_VOL_MONITOR_IR36021_READ 403 /* The lowest and highest voltage allowed for T208xRDB */ 404 #define VDD_MV_MIN 819 405 #define VDD_MV_MAX 1212 406 407 /* 408 * RapidIO 409 */ 410 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 411 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 412 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 413 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 414 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 415 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 416 /* 417 * for slave u-boot IMAGE instored in master memory space, 418 * PHYS must be aligned based on the SIZE 419 */ 420 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 421 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 422 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 423 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 424 /* 425 * for slave UCODE and ENV instored in master memory space, 426 * PHYS must be aligned based on the SIZE 427 */ 428 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 429 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 430 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 431 432 /* slave core release by master*/ 433 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 434 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 435 436 /* 437 * SRIO_PCIE_BOOT - SLAVE 438 */ 439 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 440 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 441 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 442 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 443 #endif 444 445 /* 446 * eSPI - Enhanced SPI 447 */ 448 #ifdef CONFIG_SPI_FLASH 449 #define CONFIG_SPI_FLASH_BAR 450 #define CONFIG_SF_DEFAULT_SPEED 10000000 451 #define CONFIG_SF_DEFAULT_MODE 0 452 #endif 453 454 /* 455 * General PCI 456 * Memory space is mapped 1-1, but I/O space must start from 0. 457 */ 458 #define CONFIG_PCIE1 /* PCIE controller 1 */ 459 #define CONFIG_PCIE2 /* PCIE controller 2 */ 460 #define CONFIG_PCIE3 /* PCIE controller 3 */ 461 #define CONFIG_PCIE4 /* PCIE controller 4 */ 462 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 463 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 464 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 465 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 466 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 467 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 468 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 469 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 470 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 471 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 472 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 473 474 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 475 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 476 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 477 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 478 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 479 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 480 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 481 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 482 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 483 484 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 485 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 486 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 487 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 488 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 489 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 490 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 491 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 492 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 493 494 /* controller 4, Base address 203000 */ 495 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 496 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 497 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 498 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 499 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 500 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 501 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 502 503 #ifdef CONFIG_PCI 504 #define CONFIG_PCI_INDIRECT_BRIDGE 505 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 506 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 507 #endif 508 509 /* Qman/Bman */ 510 #ifndef CONFIG_NOBQFMAN 511 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 512 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 513 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 514 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 515 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 516 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 517 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 518 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 519 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 520 CONFIG_SYS_BMAN_CENA_SIZE) 521 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 522 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 523 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 524 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 525 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 526 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 527 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 528 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 529 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 530 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 531 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 532 CONFIG_SYS_QMAN_CENA_SIZE) 533 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 534 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 535 536 #define CONFIG_SYS_DPAA_FMAN 537 #define CONFIG_SYS_DPAA_PME 538 #define CONFIG_SYS_PMAN 539 #define CONFIG_SYS_DPAA_DCE 540 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 541 #define CONFIG_SYS_INTERLAKEN 542 543 /* Default address of microcode for the Linux Fman driver */ 544 #if defined(CONFIG_SPIFLASH) 545 /* 546 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 547 * env, so we got 0x110000. 548 */ 549 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 550 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 551 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 552 #define CONFIG_CORTINA_FW_ADDR 0x120000 553 554 #elif defined(CONFIG_SDCARD) 555 /* 556 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 557 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 558 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 559 */ 560 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 561 #define CONFIG_SYS_CORTINA_FW_IN_MMC 562 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 563 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 564 565 #elif defined(CONFIG_NAND) 566 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 567 #define CONFIG_SYS_CORTINA_FW_IN_NAND 568 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 569 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 570 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 571 /* 572 * Slave has no ucode locally, it can fetch this from remote. When implementing 573 * in two corenet boards, slave's ucode could be stored in master's memory 574 * space, the address can be mapped from slave TLB->slave LAW-> 575 * slave SRIO or PCIE outbound window->master inbound window-> 576 * master LAW->the ucode address in master's memory space. 577 */ 578 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 579 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 580 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 581 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 582 #else 583 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 584 #define CONFIG_SYS_CORTINA_FW_IN_NOR 585 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 586 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 587 #endif 588 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 589 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 590 #endif /* CONFIG_NOBQFMAN */ 591 592 #ifdef CONFIG_SYS_DPAA_FMAN 593 #define CONFIG_FMAN_ENET 594 #define CONFIG_PHYLIB_10G 595 #define CONFIG_PHY_AQUANTIA 596 #define CONFIG_PHY_CORTINA 597 #define CONFIG_PHY_REALTEK 598 #define CONFIG_CORTINA_FW_LENGTH 0x40000 599 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 600 #define RGMII_PHY2_ADDR 0x02 601 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 602 #define CORTINA_PHY_ADDR2 0x0d 603 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 604 #define FM1_10GEC4_PHY_ADDR 0x01 605 #endif 606 607 #ifdef CONFIG_FMAN_ENET 608 #define CONFIG_ETHPRIME "FM1@DTSEC3" 609 #endif 610 611 /* 612 * SATA 613 */ 614 #ifdef CONFIG_FSL_SATA_V2 615 #define CONFIG_SYS_SATA_MAX_DEVICE 2 616 #define CONFIG_SATA1 617 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 618 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 619 #define CONFIG_SATA2 620 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 621 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 622 #define CONFIG_LBA48 623 #endif 624 625 /* 626 * USB 627 */ 628 #ifdef CONFIG_USB_EHCI_HCD 629 #define CONFIG_USB_EHCI_FSL 630 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 631 #define CONFIG_HAS_FSL_DR_USB 632 #endif 633 634 /* 635 * SDHC 636 */ 637 #ifdef CONFIG_MMC 638 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 639 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 640 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 641 #endif 642 643 /* 644 * Dynamic MTD Partition support with mtdparts 645 */ 646 #ifdef CONFIG_MTD_NOR_FLASH 647 #define CONFIG_FLASH_CFI_MTD 648 #endif 649 650 /* 651 * Environment 652 */ 653 654 /* 655 * Miscellaneous configurable options 656 */ 657 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 658 659 /* 660 * For booting Linux, the board info and command line data 661 * have to be in the first 64 MB of memory, since this is 662 * the maximum mapped by the Linux kernel during initialization. 663 */ 664 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 665 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 666 667 #ifdef CONFIG_CMD_KGDB 668 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 669 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 670 #endif 671 672 /* 673 * Environment Configuration 674 */ 675 #define CONFIG_ROOTPATH "/opt/nfsroot" 676 #define CONFIG_BOOTFILE "uImage" 677 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 678 679 /* default location for tftp and bootm */ 680 #define CONFIG_LOADADDR 1000000 681 #define __USB_PHY_TYPE utmi 682 683 #define CONFIG_EXTRA_ENV_SETTINGS \ 684 "hwconfig=fsl_ddr:" \ 685 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 686 "bank_intlv=auto;" \ 687 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 688 "netdev=eth0\0" \ 689 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 690 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 691 "tftpflash=tftpboot $loadaddr $uboot && " \ 692 "protect off $ubootaddr +$filesize && " \ 693 "erase $ubootaddr +$filesize && " \ 694 "cp.b $loadaddr $ubootaddr $filesize && " \ 695 "protect on $ubootaddr +$filesize && " \ 696 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 697 "consoledev=ttyS0\0" \ 698 "ramdiskaddr=2000000\0" \ 699 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 700 "fdtaddr=1e00000\0" \ 701 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 702 "bdev=sda3\0" 703 704 /* 705 * For emulation this causes u-boot to jump to the start of the 706 * proof point app code automatically 707 */ 708 #define CONFIG_PROOF_POINTS \ 709 "setenv bootargs root=/dev/$bdev rw " \ 710 "console=$consoledev,$baudrate $othbootargs;" \ 711 "cpu 1 release 0x29000000 - - -;" \ 712 "cpu 2 release 0x29000000 - - -;" \ 713 "cpu 3 release 0x29000000 - - -;" \ 714 "cpu 4 release 0x29000000 - - -;" \ 715 "cpu 5 release 0x29000000 - - -;" \ 716 "cpu 6 release 0x29000000 - - -;" \ 717 "cpu 7 release 0x29000000 - - -;" \ 718 "go 0x29000000" 719 720 #define CONFIG_HVBOOT \ 721 "setenv bootargs config-addr=0x60000000; " \ 722 "bootm 0x01000000 - 0x00f00000" 723 724 #define CONFIG_ALU \ 725 "setenv bootargs root=/dev/$bdev rw " \ 726 "console=$consoledev,$baudrate $othbootargs;" \ 727 "cpu 1 release 0x01000000 - - -;" \ 728 "cpu 2 release 0x01000000 - - -;" \ 729 "cpu 3 release 0x01000000 - - -;" \ 730 "cpu 4 release 0x01000000 - - -;" \ 731 "cpu 5 release 0x01000000 - - -;" \ 732 "cpu 6 release 0x01000000 - - -;" \ 733 "cpu 7 release 0x01000000 - - -;" \ 734 "go 0x01000000" 735 736 #define CONFIG_LINUX \ 737 "setenv bootargs root=/dev/ram rw " \ 738 "console=$consoledev,$baudrate $othbootargs;" \ 739 "setenv ramdiskaddr 0x02000000;" \ 740 "setenv fdtaddr 0x00c00000;" \ 741 "setenv loadaddr 0x1000000;" \ 742 "bootm $loadaddr $ramdiskaddr $fdtaddr" 743 744 #define CONFIG_HDBOOT \ 745 "setenv bootargs root=/dev/$bdev rw " \ 746 "console=$consoledev,$baudrate $othbootargs;" \ 747 "tftp $loadaddr $bootfile;" \ 748 "tftp $fdtaddr $fdtfile;" \ 749 "bootm $loadaddr - $fdtaddr" 750 751 #define CONFIG_NFSBOOTCOMMAND \ 752 "setenv bootargs root=/dev/nfs rw " \ 753 "nfsroot=$serverip:$rootpath " \ 754 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 755 "console=$consoledev,$baudrate $othbootargs;" \ 756 "tftp $loadaddr $bootfile;" \ 757 "tftp $fdtaddr $fdtfile;" \ 758 "bootm $loadaddr - $fdtaddr" 759 760 #define CONFIG_RAMBOOTCOMMAND \ 761 "setenv bootargs root=/dev/ram rw " \ 762 "console=$consoledev,$baudrate $othbootargs;" \ 763 "tftp $ramdiskaddr $ramdiskfile;" \ 764 "tftp $loadaddr $bootfile;" \ 765 "tftp $fdtaddr $fdtfile;" \ 766 "bootm $loadaddr $ramdiskaddr $fdtaddr" 767 768 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 769 770 #include <asm/fsl_secure_boot.h> 771 772 #endif /* __T2080RDB_H */ 773