1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_T2080RDB 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 #define CONFIG_MMC 17 #define CONFIG_SPI_FLASH 18 #define CONFIG_USB_EHCI 19 #define CONFIG_FSL_SATA_V2 20 21 /* High Level Configuration Options */ 22 #define CONFIG_PHYS_64BIT 23 #define CONFIG_BOOKE 24 #define CONFIG_E500 /* BOOKE e500 family */ 25 #define CONFIG_E500MC /* BOOKE e500mc family */ 26 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 27 #define CONFIG_MP /* support multiple processors */ 28 #define CONFIG_ENABLE_36BIT_PHYS 29 30 #ifdef CONFIG_PHYS_64BIT 31 #define CONFIG_ADDR_MAP 1 32 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 33 #endif 34 35 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 36 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 37 #define CONFIG_FSL_IFC /* Enable IFC Support */ 38 #define CONFIG_FSL_LAW /* Use common FSL init code */ 39 #define CONFIG_ENV_OVERWRITE 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg 44 45 #define CONFIG_SPL 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_ENV_SUPPORT 48 #define CONFIG_SPL_SERIAL_SUPPORT 49 #define CONFIG_SPL_FLUSH_IMAGE 50 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 51 #define CONFIG_SPL_LIBGENERIC_SUPPORT 52 #define CONFIG_SPL_LIBCOMMON_SUPPORT 53 #define CONFIG_SPL_I2C_SUPPORT 54 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 55 #define CONFIG_FSL_LAW /* Use common FSL init code */ 56 #define CONFIG_SYS_TEXT_BASE 0x00201000 57 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 58 #define CONFIG_SPL_PAD_TO 0x40000 59 #define CONFIG_SPL_MAX_SIZE 0x28000 60 #define RESET_VECTOR_OFFSET 0x27FFC 61 #define BOOT_PAGE_OFFSET 0x27000 62 #ifdef CONFIG_SPL_BUILD 63 #define CONFIG_SPL_SKIP_RELOCATE 64 #define CONFIG_SPL_COMMON_INIT_DDR 65 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 66 #define CONFIG_SYS_NO_FLASH 67 #endif 68 69 #ifdef CONFIG_NAND 70 #define CONFIG_SPL_NAND_SUPPORT 71 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 72 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 73 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 74 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 76 #define CONFIG_SPL_NAND_BOOT 77 #endif 78 79 #ifdef CONFIG_SPIFLASH 80 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 81 #define CONFIG_SPL_SPI_SUPPORT 82 #define CONFIG_SPL_SPI_FLASH_SUPPORT 83 #define CONFIG_SPL_SPI_FLASH_MINIMAL 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 88 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 89 #ifndef CONFIG_SPL_BUILD 90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 91 #endif 92 #define CONFIG_SPL_SPI_BOOT 93 #endif 94 95 #ifdef CONFIG_SDCARD 96 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 97 #define CONFIG_SPL_MMC_SUPPORT 98 #define CONFIG_SPL_MMC_MINIMAL 99 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 100 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 101 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 102 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 103 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 104 #ifndef CONFIG_SPL_BUILD 105 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 106 #endif 107 #define CONFIG_SPL_MMC_BOOT 108 #endif 109 110 #endif /* CONFIG_RAMBOOT_PBL */ 111 112 #define CONFIG_SRIO_PCIE_BOOT_MASTER 113 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 114 /* Set 1M boot space */ 115 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 116 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 117 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 118 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 119 #define CONFIG_SYS_NO_FLASH 120 #endif 121 122 #ifndef CONFIG_SYS_TEXT_BASE 123 #define CONFIG_SYS_TEXT_BASE 0xeff40000 124 #endif 125 126 #ifndef CONFIG_RESET_VECTOR_ADDRESS 127 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 128 #endif 129 130 /* 131 * These can be toggled for performance analysis, otherwise use default. 132 */ 133 #define CONFIG_SYS_CACHE_STASHING 134 #define CONFIG_BTB /* toggle branch predition */ 135 #define CONFIG_DDR_ECC 136 #ifdef CONFIG_DDR_ECC 137 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 138 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 139 #endif 140 141 #ifndef CONFIG_SYS_NO_FLASH 142 #define CONFIG_FLASH_CFI_DRIVER 143 #define CONFIG_SYS_FLASH_CFI 144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 145 #endif 146 147 #if defined(CONFIG_SPIFLASH) 148 #define CONFIG_SYS_EXTRA_ENV_RELOC 149 #define CONFIG_ENV_IS_IN_SPI_FLASH 150 #define CONFIG_ENV_SPI_BUS 0 151 #define CONFIG_ENV_SPI_CS 0 152 #define CONFIG_ENV_SPI_MAX_HZ 10000000 153 #define CONFIG_ENV_SPI_MODE 0 154 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 155 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 156 #define CONFIG_ENV_SECT_SIZE 0x10000 157 #elif defined(CONFIG_SDCARD) 158 #define CONFIG_SYS_EXTRA_ENV_RELOC 159 #define CONFIG_ENV_IS_IN_MMC 160 #define CONFIG_SYS_MMC_ENV_DEV 0 161 #define CONFIG_ENV_SIZE 0x2000 162 #define CONFIG_ENV_OFFSET (512 * 0x800) 163 #elif defined(CONFIG_NAND) 164 #define CONFIG_SYS_EXTRA_ENV_RELOC 165 #define CONFIG_ENV_IS_IN_NAND 166 #define CONFIG_ENV_SIZE 0x2000 167 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 168 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 169 #define CONFIG_ENV_IS_IN_REMOTE 170 #define CONFIG_ENV_ADDR 0xffe20000 171 #define CONFIG_ENV_SIZE 0x2000 172 #elif defined(CONFIG_ENV_IS_NOWHERE) 173 #define CONFIG_ENV_SIZE 0x2000 174 #else 175 #define CONFIG_ENV_IS_IN_FLASH 176 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 177 #define CONFIG_ENV_SIZE 0x2000 178 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 179 #endif 180 181 #ifndef __ASSEMBLY__ 182 unsigned long get_board_sys_clk(void); 183 unsigned long get_board_ddr_clk(void); 184 #endif 185 186 #define CONFIG_SYS_CLK_FREQ 66660000 187 #define CONFIG_DDR_CLK_FREQ 133330000 188 189 /* 190 * Config the L3 Cache as L3 SRAM 191 */ 192 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 193 #define CONFIG_SYS_L3_SIZE (512 << 10) 194 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 195 #ifdef CONFIG_RAMBOOT_PBL 196 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 197 #endif 198 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 199 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 200 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 201 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 202 203 #define CONFIG_SYS_DCSRBAR 0xf0000000 204 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 205 206 /* EEPROM */ 207 #define CONFIG_ID_EEPROM 208 #define CONFIG_SYS_I2C_EEPROM_NXID 209 #define CONFIG_SYS_EEPROM_BUS_NUM 0 210 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 211 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 212 213 /* 214 * DDR Setup 215 */ 216 #define CONFIG_VERY_BIG_RAM 217 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 218 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 219 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 220 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 221 #define CONFIG_DDR_SPD 222 #define CONFIG_SYS_FSL_DDR3 223 #undef CONFIG_FSL_DDR_INTERACTIVE 224 #define CONFIG_SYS_SPD_BUS_NUM 0 225 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 226 #define SPD_EEPROM_ADDRESS1 0x51 227 #define SPD_EEPROM_ADDRESS2 0x52 228 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 229 #define CTRL_INTLV_PREFERED cacheline 230 231 /* 232 * IFC Definitions 233 */ 234 #define CONFIG_SYS_FLASH_BASE 0xe8000000 235 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 236 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 237 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 238 CSPR_PORT_SIZE_16 | \ 239 CSPR_MSEL_NOR | \ 240 CSPR_V) 241 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 242 243 /* NOR Flash Timing Params */ 244 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 245 246 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 247 FTIM0_NOR_TEADC(0x5) | \ 248 FTIM0_NOR_TEAHC(0x5)) 249 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 250 FTIM1_NOR_TRAD_NOR(0x1A) |\ 251 FTIM1_NOR_TSEQRAD_NOR(0x13)) 252 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 253 FTIM2_NOR_TCH(0x4) | \ 254 FTIM2_NOR_TWPH(0x0E) | \ 255 FTIM2_NOR_TWP(0x1c)) 256 #define CONFIG_SYS_NOR_FTIM3 0x0 257 258 #define CONFIG_SYS_FLASH_QUIET_TEST 259 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 260 261 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 262 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 263 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 264 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 265 #define CONFIG_SYS_FLASH_EMPTY_INFO 266 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 267 268 /* CPLD on IFC */ 269 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 270 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 271 #define CONFIG_SYS_CSPR2_EXT (0xf) 272 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 273 | CSPR_PORT_SIZE_8 \ 274 | CSPR_MSEL_GPCM \ 275 | CSPR_V) 276 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 277 #define CONFIG_SYS_CSOR2 0x0 278 279 /* CPLD Timing parameters for IFC CS2 */ 280 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 281 FTIM0_GPCM_TEADC(0x0e) | \ 282 FTIM0_GPCM_TEAHC(0x0e)) 283 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 284 FTIM1_GPCM_TRAD(0x1f)) 285 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 286 FTIM2_GPCM_TCH(0x0) | \ 287 FTIM2_GPCM_TWP(0x1f)) 288 #define CONFIG_SYS_CS2_FTIM3 0x0 289 290 /* NAND Flash on IFC */ 291 #define CONFIG_NAND_FSL_IFC 292 #define CONFIG_SYS_NAND_BASE 0xff800000 293 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 294 295 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 296 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 297 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 298 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 299 | CSPR_V) 300 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 301 302 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 303 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 304 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 305 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 306 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 307 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 308 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 309 310 #define CONFIG_SYS_NAND_ONFI_DETECTION 311 312 /* ONFI NAND Flash mode0 Timing Params */ 313 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 314 FTIM0_NAND_TWP(0x18) | \ 315 FTIM0_NAND_TWCHT(0x07) | \ 316 FTIM0_NAND_TWH(0x0a)) 317 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 318 FTIM1_NAND_TWBE(0x39) | \ 319 FTIM1_NAND_TRR(0x0e) | \ 320 FTIM1_NAND_TRP(0x18)) 321 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 322 FTIM2_NAND_TREH(0x0a) | \ 323 FTIM2_NAND_TWHRE(0x1e)) 324 #define CONFIG_SYS_NAND_FTIM3 0x0 325 326 #define CONFIG_SYS_NAND_DDR_LAW 11 327 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 328 #define CONFIG_SYS_MAX_NAND_DEVICE 1 329 #define CONFIG_MTD_NAND_VERIFY_WRITE 330 #define CONFIG_CMD_NAND 331 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 332 333 #if defined(CONFIG_NAND) 334 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 335 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 336 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 337 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 338 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 339 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 340 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 341 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 342 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 343 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 344 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 345 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 346 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 347 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 348 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 349 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 350 #else 351 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 352 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 353 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 354 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 355 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 356 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 357 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 358 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 359 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 360 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 361 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 362 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 363 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 364 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 365 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 366 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 367 #endif 368 369 #if defined(CONFIG_RAMBOOT_PBL) 370 #define CONFIG_SYS_RAMBOOT 371 #endif 372 373 #ifdef CONFIG_SPL_BUILD 374 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 375 #else 376 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 377 #endif 378 379 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 380 #define CONFIG_MISC_INIT_R 381 #define CONFIG_HWCONFIG 382 383 /* define to use L1 as initial stack */ 384 #define CONFIG_L1_INIT_RAM 385 #define CONFIG_SYS_INIT_RAM_LOCK 386 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 387 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 389 /* The assembler doesn't like typecast */ 390 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 391 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 392 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 393 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 394 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 395 GENERATED_GBL_DATA_SIZE) 396 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 397 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 398 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 399 400 /* 401 * Serial Port 402 */ 403 #define CONFIG_CONS_INDEX 1 404 #define CONFIG_SYS_NS16550 405 #define CONFIG_SYS_NS16550_SERIAL 406 #define CONFIG_SYS_NS16550_REG_SIZE 1 407 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 408 #define CONFIG_SYS_BAUDRATE_TABLE \ 409 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 410 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 411 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 412 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 413 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 414 415 /* Use the HUSH parser */ 416 #define CONFIG_SYS_HUSH_PARSER 417 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 418 419 /* pass open firmware flat tree */ 420 #define CONFIG_OF_LIBFDT 421 #define CONFIG_OF_BOARD_SETUP 422 #define CONFIG_OF_STDOUT_VIA_ALIAS 423 424 /* new uImage format support */ 425 #define CONFIG_FIT 426 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 427 428 /* 429 * I2C 430 */ 431 #define CONFIG_SYS_I2C 432 #define CONFIG_SYS_I2C_FSL 433 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 434 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 435 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 437 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 438 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 439 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 440 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 441 #define CONFIG_SYS_FSL_I2C_SPEED 100000 442 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 443 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 444 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 445 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 446 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 447 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 448 #define I2C_MUX_CH_DEFAULT 0x8 449 450 451 /* 452 * RapidIO 453 */ 454 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 455 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 456 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 457 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 458 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 459 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 460 /* 461 * for slave u-boot IMAGE instored in master memory space, 462 * PHYS must be aligned based on the SIZE 463 */ 464 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 465 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 466 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 467 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 468 /* 469 * for slave UCODE and ENV instored in master memory space, 470 * PHYS must be aligned based on the SIZE 471 */ 472 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 473 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 474 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 475 476 /* slave core release by master*/ 477 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 478 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 479 480 /* 481 * SRIO_PCIE_BOOT - SLAVE 482 */ 483 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 484 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 485 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 486 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 487 #endif 488 489 /* 490 * eSPI - Enhanced SPI 491 */ 492 #ifdef CONFIG_SPI_FLASH 493 #define CONFIG_FSL_ESPI 494 #define CONFIG_SPI_FLASH_STMICRO 495 #define CONFIG_SPI_FLASH_BAR 496 #define CONFIG_CMD_SF 497 #define CONFIG_SF_DEFAULT_SPEED 10000000 498 #define CONFIG_SF_DEFAULT_MODE 0 499 #endif 500 501 /* 502 * General PCI 503 * Memory space is mapped 1-1, but I/O space must start from 0. 504 */ 505 #define CONFIG_PCI /* Enable PCI/PCIE */ 506 #define CONFIG_PCIE1 /* PCIE controler 1 */ 507 #define CONFIG_PCIE2 /* PCIE controler 2 */ 508 #define CONFIG_PCIE3 /* PCIE controler 3 */ 509 #define CONFIG_PCIE4 /* PCIE controler 4 */ 510 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 511 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 512 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 513 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 514 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 515 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 516 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 517 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 518 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 519 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 520 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 521 522 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 523 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 524 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 525 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 526 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 527 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 528 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 529 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 530 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 531 532 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 533 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 534 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 535 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 536 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 537 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 538 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 539 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 540 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 541 542 /* controller 4, Base address 203000 */ 543 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 544 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 545 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 546 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 547 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 548 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 549 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 550 551 #ifdef CONFIG_PCI 552 #define CONFIG_PCI_INDIRECT_BRIDGE 553 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 554 #define CONFIG_NET_MULTI 555 #define CONFIG_E1000 556 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 557 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 558 #define CONFIG_DOS_PARTITION 559 #endif 560 561 /* Qman/Bman */ 562 #ifndef CONFIG_NOBQFMAN 563 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 564 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 565 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 566 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 567 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 568 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 569 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 570 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 571 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 572 573 #define CONFIG_SYS_DPAA_FMAN 574 #define CONFIG_SYS_DPAA_PME 575 #define CONFIG_SYS_PMAN 576 #define CONFIG_SYS_DPAA_DCE 577 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 578 #define CONFIG_SYS_INTERLAKEN 579 580 /* Default address of microcode for the Linux Fman driver */ 581 #if defined(CONFIG_SPIFLASH) 582 /* 583 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 584 * env, so we got 0x110000. 585 */ 586 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 587 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 588 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 589 #define CONFIG_CORTINA_FW_ADDR 0x120000 590 591 #elif defined(CONFIG_SDCARD) 592 /* 593 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 594 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 595 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 596 */ 597 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 598 #define CONFIG_SYS_CORTINA_FW_IN_MMC 599 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 600 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 601 602 #elif defined(CONFIG_NAND) 603 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 604 #define CONFIG_SYS_CORTINA_FW_IN_NAND 605 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 606 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 607 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 608 /* 609 * Slave has no ucode locally, it can fetch this from remote. When implementing 610 * in two corenet boards, slave's ucode could be stored in master's memory 611 * space, the address can be mapped from slave TLB->slave LAW-> 612 * slave SRIO or PCIE outbound window->master inbound window-> 613 * master LAW->the ucode address in master's memory space. 614 */ 615 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 616 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 617 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 618 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 619 #else 620 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 621 #define CONFIG_SYS_CORTINA_FW_IN_NOR 622 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 623 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 624 #endif 625 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 626 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 627 #endif /* CONFIG_NOBQFMAN */ 628 629 #ifdef CONFIG_SYS_DPAA_FMAN 630 #define CONFIG_FMAN_ENET 631 #define CONFIG_PHYLIB_10G 632 #define CONFIG_PHY_CORTINA 633 #define CONFIG_PHY_AQ1202 634 #define CONFIG_PHY_REALTEK 635 #define CONFIG_CORTINA_FW_LENGTH 0x40000 636 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 637 #define RGMII_PHY2_ADDR 0x02 638 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 639 #define CORTINA_PHY_ADDR2 0x0d 640 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 641 #define FM1_10GEC4_PHY_ADDR 0x01 642 #endif 643 644 645 #ifdef CONFIG_FMAN_ENET 646 #define CONFIG_MII /* MII PHY management */ 647 #define CONFIG_ETHPRIME "FM1@DTSEC3" 648 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 649 #endif 650 651 /* 652 * SATA 653 */ 654 #ifdef CONFIG_FSL_SATA_V2 655 #define CONFIG_LIBATA 656 #define CONFIG_FSL_SATA 657 #define CONFIG_SYS_SATA_MAX_DEVICE 2 658 #define CONFIG_SATA1 659 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 660 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 661 #define CONFIG_SATA2 662 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 663 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 664 #define CONFIG_LBA48 665 #define CONFIG_CMD_SATA 666 #define CONFIG_DOS_PARTITION 667 #define CONFIG_CMD_EXT2 668 #endif 669 670 /* 671 * USB 672 */ 673 #ifdef CONFIG_USB_EHCI 674 #define CONFIG_CMD_USB 675 #define CONFIG_USB_STORAGE 676 #define CONFIG_USB_EHCI_FSL 677 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 678 #define CONFIG_CMD_EXT2 679 #define CONFIG_HAS_FSL_DR_USB 680 #endif 681 682 /* 683 * SDHC 684 */ 685 #ifdef CONFIG_MMC 686 #define CONFIG_CMD_MMC 687 #define CONFIG_FSL_ESDHC 688 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 689 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 690 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 691 #define CONFIG_GENERIC_MMC 692 #define CONFIG_CMD_EXT2 693 #define CONFIG_CMD_FAT 694 #define CONFIG_DOS_PARTITION 695 #endif 696 697 /* 698 * Dynamic MTD Partition support with mtdparts 699 */ 700 #ifndef CONFIG_SYS_NO_FLASH 701 #define CONFIG_MTD_DEVICE 702 #define CONFIG_MTD_PARTITIONS 703 #define CONFIG_CMD_MTDPARTS 704 #define CONFIG_FLASH_CFI_MTD 705 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 706 "spi0=spife110000.1" 707 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 708 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 709 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 710 "1m(uboot),5m(kernel),128k(dtb),-(user)" 711 #endif 712 713 /* 714 * Environment 715 */ 716 717 /* 718 * Command line configuration. 719 */ 720 #include <config_cmd_default.h> 721 722 #define CONFIG_CMD_DHCP 723 #define CONFIG_CMD_ELF 724 #define CONFIG_CMD_MII 725 #define CONFIG_CMD_I2C 726 #define CONFIG_CMD_PING 727 #define CONFIG_CMD_ECHO 728 #define CONFIG_CMD_SETEXPR 729 #define CONFIG_CMD_REGINFO 730 #define CONFIG_CMD_BDI 731 732 #ifdef CONFIG_PCI 733 #define CONFIG_CMD_PCI 734 #define CONFIG_CMD_NET 735 #endif 736 737 /* 738 * Miscellaneous configurable options 739 */ 740 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 741 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 742 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 743 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 744 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 745 #ifdef CONFIG_CMD_KGDB 746 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 747 #else 748 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 749 #endif 750 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 751 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 752 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 753 754 /* 755 * For booting Linux, the board info and command line data 756 * have to be in the first 64 MB of memory, since this is 757 * the maximum mapped by the Linux kernel during initialization. 758 */ 759 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 760 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 761 762 #ifdef CONFIG_CMD_KGDB 763 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 764 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 765 #endif 766 767 /* 768 * Environment Configuration 769 */ 770 #define CONFIG_ROOTPATH "/opt/nfsroot" 771 #define CONFIG_BOOTFILE "uImage" 772 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 773 774 /* default location for tftp and bootm */ 775 #define CONFIG_LOADADDR 1000000 776 #define CONFIG_BAUDRATE 115200 777 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 778 #define __USB_PHY_TYPE utmi 779 780 #define CONFIG_EXTRA_ENV_SETTINGS \ 781 "hwconfig=fsl_ddr:" \ 782 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 783 "bank_intlv=auto;" \ 784 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 785 "netdev=eth0\0" \ 786 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 787 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 788 "tftpflash=tftpboot $loadaddr $uboot && " \ 789 "protect off $ubootaddr +$filesize && " \ 790 "erase $ubootaddr +$filesize && " \ 791 "cp.b $loadaddr $ubootaddr $filesize && " \ 792 "protect on $ubootaddr +$filesize && " \ 793 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 794 "consoledev=ttyS0\0" \ 795 "ramdiskaddr=2000000\0" \ 796 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 797 "fdtaddr=c00000\0" \ 798 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 799 "bdev=sda3\0" \ 800 "c=ffe\0" 801 802 /* 803 * For emulation this causes u-boot to jump to the start of the 804 * proof point app code automatically 805 */ 806 #define CONFIG_PROOF_POINTS \ 807 "setenv bootargs root=/dev/$bdev rw " \ 808 "console=$consoledev,$baudrate $othbootargs;" \ 809 "cpu 1 release 0x29000000 - - -;" \ 810 "cpu 2 release 0x29000000 - - -;" \ 811 "cpu 3 release 0x29000000 - - -;" \ 812 "cpu 4 release 0x29000000 - - -;" \ 813 "cpu 5 release 0x29000000 - - -;" \ 814 "cpu 6 release 0x29000000 - - -;" \ 815 "cpu 7 release 0x29000000 - - -;" \ 816 "go 0x29000000" 817 818 #define CONFIG_HVBOOT \ 819 "setenv bootargs config-addr=0x60000000; " \ 820 "bootm 0x01000000 - 0x00f00000" 821 822 #define CONFIG_ALU \ 823 "setenv bootargs root=/dev/$bdev rw " \ 824 "console=$consoledev,$baudrate $othbootargs;" \ 825 "cpu 1 release 0x01000000 - - -;" \ 826 "cpu 2 release 0x01000000 - - -;" \ 827 "cpu 3 release 0x01000000 - - -;" \ 828 "cpu 4 release 0x01000000 - - -;" \ 829 "cpu 5 release 0x01000000 - - -;" \ 830 "cpu 6 release 0x01000000 - - -;" \ 831 "cpu 7 release 0x01000000 - - -;" \ 832 "go 0x01000000" 833 834 #define CONFIG_LINUX \ 835 "setenv bootargs root=/dev/ram rw " \ 836 "console=$consoledev,$baudrate $othbootargs;" \ 837 "setenv ramdiskaddr 0x02000000;" \ 838 "setenv fdtaddr 0x00c00000;" \ 839 "setenv loadaddr 0x1000000;" \ 840 "bootm $loadaddr $ramdiskaddr $fdtaddr" 841 842 #define CONFIG_HDBOOT \ 843 "setenv bootargs root=/dev/$bdev rw " \ 844 "console=$consoledev,$baudrate $othbootargs;" \ 845 "tftp $loadaddr $bootfile;" \ 846 "tftp $fdtaddr $fdtfile;" \ 847 "bootm $loadaddr - $fdtaddr" 848 849 #define CONFIG_NFSBOOTCOMMAND \ 850 "setenv bootargs root=/dev/nfs rw " \ 851 "nfsroot=$serverip:$rootpath " \ 852 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 853 "console=$consoledev,$baudrate $othbootargs;" \ 854 "tftp $loadaddr $bootfile;" \ 855 "tftp $fdtaddr $fdtfile;" \ 856 "bootm $loadaddr - $fdtaddr" 857 858 #define CONFIG_RAMBOOTCOMMAND \ 859 "setenv bootargs root=/dev/ram rw " \ 860 "console=$consoledev,$baudrate $othbootargs;" \ 861 "tftp $ramdiskaddr $ramdiskfile;" \ 862 "tftp $loadaddr $bootfile;" \ 863 "tftp $fdtaddr $fdtfile;" \ 864 "bootm $loadaddr $ramdiskaddr $fdtaddr" 865 866 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 867 868 #ifdef CONFIG_SECURE_BOOT 869 #include <asm/fsl_secure_boot.h> 870 #undef CONFIG_CMD_USB 871 #endif 872 873 #endif /* __T2080RDB_H */ 874