1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080 RDB/PCIe board configuration file 9 */ 10 11 #ifndef __T2080RDB_H 12 #define __T2080RDB_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_USB_EHCI 16 #define CONFIG_FSL_SATA_V2 17 18 /* High Level Configuration Options */ 19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 20 #define CONFIG_MP /* support multiple processors */ 21 #define CONFIG_ENABLE_36BIT_PHYS 22 23 #ifdef CONFIG_PHYS_64BIT 24 #define CONFIG_ADDR_MAP 1 25 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 26 #endif 27 28 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 29 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 30 #define CONFIG_ENV_OVERWRITE 31 32 #ifdef CONFIG_RAMBOOT_PBL 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg 34 35 #define CONFIG_SPL_FLUSH_IMAGE 36 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 37 #define CONFIG_SYS_TEXT_BASE 0x00201000 38 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 39 #define CONFIG_SPL_PAD_TO 0x40000 40 #define CONFIG_SPL_MAX_SIZE 0x28000 41 #define RESET_VECTOR_OFFSET 0x27FFC 42 #define BOOT_PAGE_OFFSET 0x27000 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SPL_SKIP_RELOCATE 45 #define CONFIG_SPL_COMMON_INIT_DDR 46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 47 #endif 48 49 #ifdef CONFIG_NAND 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg 56 #define CONFIG_SPL_NAND_BOOT 57 #endif 58 59 #ifdef CONFIG_SPIFLASH 60 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 61 #define CONFIG_SPL_SPI_FLASH_MINIMAL 62 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 66 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 67 #ifndef CONFIG_SPL_BUILD 68 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 69 #endif 70 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg 71 #define CONFIG_SPL_SPI_BOOT 72 #endif 73 74 #ifdef CONFIG_SDCARD 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 76 #define CONFIG_SPL_MMC_MINIMAL 77 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 78 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 79 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 80 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 82 #ifndef CONFIG_SPL_BUILD 83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 84 #endif 85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg 86 #define CONFIG_SPL_MMC_BOOT 87 #endif 88 89 #endif /* CONFIG_RAMBOOT_PBL */ 90 91 #define CONFIG_SRIO_PCIE_BOOT_MASTER 92 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 93 /* Set 1M boot space */ 94 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 95 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 96 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 97 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 98 #endif 99 100 #ifndef CONFIG_SYS_TEXT_BASE 101 #define CONFIG_SYS_TEXT_BASE 0xeff40000 102 #endif 103 104 #ifndef CONFIG_RESET_VECTOR_ADDRESS 105 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 106 #endif 107 108 /* 109 * These can be toggled for performance analysis, otherwise use default. 110 */ 111 #define CONFIG_SYS_CACHE_STASHING 112 #define CONFIG_BTB /* toggle branch predition */ 113 #define CONFIG_DDR_ECC 114 #ifdef CONFIG_DDR_ECC 115 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 116 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 117 #endif 118 119 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 120 #define CONFIG_SYS_MEMTEST_END 0x00400000 121 #define CONFIG_SYS_ALT_MEMTEST 122 123 #ifdef CONFIG_MTD_NOR_FLASH 124 #define CONFIG_FLASH_CFI_DRIVER 125 #define CONFIG_SYS_FLASH_CFI 126 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 127 #endif 128 129 #if defined(CONFIG_SPIFLASH) 130 #define CONFIG_SYS_EXTRA_ENV_RELOC 131 #define CONFIG_ENV_IS_IN_SPI_FLASH 132 #define CONFIG_ENV_SPI_BUS 0 133 #define CONFIG_ENV_SPI_CS 0 134 #define CONFIG_ENV_SPI_MAX_HZ 10000000 135 #define CONFIG_ENV_SPI_MODE 0 136 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 137 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 138 #define CONFIG_ENV_SECT_SIZE 0x10000 139 #elif defined(CONFIG_SDCARD) 140 #define CONFIG_SYS_EXTRA_ENV_RELOC 141 #define CONFIG_ENV_IS_IN_MMC 142 #define CONFIG_SYS_MMC_ENV_DEV 0 143 #define CONFIG_ENV_SIZE 0x2000 144 #define CONFIG_ENV_OFFSET (512 * 0x800) 145 #elif defined(CONFIG_NAND) 146 #define CONFIG_SYS_EXTRA_ENV_RELOC 147 #define CONFIG_ENV_IS_IN_NAND 148 #define CONFIG_ENV_SIZE 0x2000 149 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 150 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 151 #define CONFIG_ENV_IS_IN_REMOTE 152 #define CONFIG_ENV_ADDR 0xffe20000 153 #define CONFIG_ENV_SIZE 0x2000 154 #elif defined(CONFIG_ENV_IS_NOWHERE) 155 #define CONFIG_ENV_SIZE 0x2000 156 #else 157 #define CONFIG_ENV_IS_IN_FLASH 158 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 159 #define CONFIG_ENV_SIZE 0x2000 160 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 161 #endif 162 163 #ifndef __ASSEMBLY__ 164 unsigned long get_board_sys_clk(void); 165 unsigned long get_board_ddr_clk(void); 166 #endif 167 168 #define CONFIG_SYS_CLK_FREQ 66660000 169 #define CONFIG_DDR_CLK_FREQ 133330000 170 171 /* 172 * Config the L3 Cache as L3 SRAM 173 */ 174 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 175 #define CONFIG_SYS_L3_SIZE (512 << 10) 176 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 177 #ifdef CONFIG_RAMBOOT_PBL 178 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 179 #endif 180 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 181 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 182 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 183 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 184 185 #define CONFIG_SYS_DCSRBAR 0xf0000000 186 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 187 188 /* EEPROM */ 189 #define CONFIG_ID_EEPROM 190 #define CONFIG_SYS_I2C_EEPROM_NXID 191 #define CONFIG_SYS_EEPROM_BUS_NUM 0 192 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 193 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 194 195 /* 196 * DDR Setup 197 */ 198 #define CONFIG_VERY_BIG_RAM 199 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 200 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 201 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 202 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 203 #define CONFIG_DDR_SPD 204 #undef CONFIG_FSL_DDR_INTERACTIVE 205 #define CONFIG_SYS_SPD_BUS_NUM 0 206 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 207 #define SPD_EEPROM_ADDRESS1 0x51 208 #define SPD_EEPROM_ADDRESS2 0x52 209 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 210 #define CTRL_INTLV_PREFERED cacheline 211 212 /* 213 * IFC Definitions 214 */ 215 #define CONFIG_SYS_FLASH_BASE 0xe8000000 216 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 217 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 218 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 219 CSPR_PORT_SIZE_16 | \ 220 CSPR_MSEL_NOR | \ 221 CSPR_V) 222 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 223 224 /* NOR Flash Timing Params */ 225 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 226 227 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 228 FTIM0_NOR_TEADC(0x5) | \ 229 FTIM0_NOR_TEAHC(0x5)) 230 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 231 FTIM1_NOR_TRAD_NOR(0x1A) |\ 232 FTIM1_NOR_TSEQRAD_NOR(0x13)) 233 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 234 FTIM2_NOR_TCH(0x4) | \ 235 FTIM2_NOR_TWPH(0x0E) | \ 236 FTIM2_NOR_TWP(0x1c)) 237 #define CONFIG_SYS_NOR_FTIM3 0x0 238 239 #define CONFIG_SYS_FLASH_QUIET_TEST 240 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 241 242 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 243 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 244 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 245 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 246 #define CONFIG_SYS_FLASH_EMPTY_INFO 247 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } 248 249 /* CPLD on IFC */ 250 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 251 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 252 #define CONFIG_SYS_CSPR2_EXT (0xf) 253 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 254 | CSPR_PORT_SIZE_8 \ 255 | CSPR_MSEL_GPCM \ 256 | CSPR_V) 257 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 258 #define CONFIG_SYS_CSOR2 0x0 259 260 /* CPLD Timing parameters for IFC CS2 */ 261 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 262 FTIM0_GPCM_TEADC(0x0e) | \ 263 FTIM0_GPCM_TEAHC(0x0e)) 264 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 265 FTIM1_GPCM_TRAD(0x1f)) 266 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 267 FTIM2_GPCM_TCH(0x8) | \ 268 FTIM2_GPCM_TWP(0x1f)) 269 #define CONFIG_SYS_CS2_FTIM3 0x0 270 271 /* NAND Flash on IFC */ 272 #define CONFIG_NAND_FSL_IFC 273 #define CONFIG_SYS_NAND_BASE 0xff800000 274 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 275 276 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 277 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 278 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 279 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 280 | CSPR_V) 281 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 282 283 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 284 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 285 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 286 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 287 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 288 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 289 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 290 291 #define CONFIG_SYS_NAND_ONFI_DETECTION 292 293 /* ONFI NAND Flash mode0 Timing Params */ 294 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 295 FTIM0_NAND_TWP(0x18) | \ 296 FTIM0_NAND_TWCHT(0x07) | \ 297 FTIM0_NAND_TWH(0x0a)) 298 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 299 FTIM1_NAND_TWBE(0x39) | \ 300 FTIM1_NAND_TRR(0x0e) | \ 301 FTIM1_NAND_TRP(0x18)) 302 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 303 FTIM2_NAND_TREH(0x0a) | \ 304 FTIM2_NAND_TWHRE(0x1e)) 305 #define CONFIG_SYS_NAND_FTIM3 0x0 306 307 #define CONFIG_SYS_NAND_DDR_LAW 11 308 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 309 #define CONFIG_SYS_MAX_NAND_DEVICE 1 310 #define CONFIG_CMD_NAND 311 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 312 313 #if defined(CONFIG_NAND) 314 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 315 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 316 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 317 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 318 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 319 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 320 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 321 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 322 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 323 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 324 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 325 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 326 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 327 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 328 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 329 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 330 #else 331 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 332 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 333 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 334 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 335 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 336 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 337 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 338 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 339 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 340 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 341 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 342 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 343 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 344 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 345 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 346 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 347 #endif 348 349 #if defined(CONFIG_RAMBOOT_PBL) 350 #define CONFIG_SYS_RAMBOOT 351 #endif 352 353 #ifdef CONFIG_SPL_BUILD 354 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 355 #else 356 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 357 #endif 358 359 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 360 #define CONFIG_MISC_INIT_R 361 #define CONFIG_HWCONFIG 362 363 /* define to use L1 as initial stack */ 364 #define CONFIG_L1_INIT_RAM 365 #define CONFIG_SYS_INIT_RAM_LOCK 366 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 367 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 369 /* The assembler doesn't like typecast */ 370 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 371 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 372 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 373 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 374 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 375 GENERATED_GBL_DATA_SIZE) 376 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 377 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 378 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 379 380 /* 381 * Serial Port 382 */ 383 #define CONFIG_CONS_INDEX 1 384 #define CONFIG_SYS_NS16550_SERIAL 385 #define CONFIG_SYS_NS16550_REG_SIZE 1 386 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 387 #define CONFIG_SYS_BAUDRATE_TABLE \ 388 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 389 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 390 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 391 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 392 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 393 394 /* 395 * I2C 396 */ 397 #define CONFIG_SYS_I2C 398 #define CONFIG_SYS_I2C_FSL 399 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 400 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 401 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 402 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 403 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 404 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 405 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 406 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 407 #define CONFIG_SYS_FSL_I2C_SPEED 100000 408 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 409 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 410 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 411 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 412 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 413 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 414 #define I2C_MUX_CH_DEFAULT 0x8 415 416 #define I2C_MUX_CH_VOL_MONITOR 0xa 417 418 #define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" 419 #ifndef CONFIG_SPL_BUILD 420 #define CONFIG_VID 421 #endif 422 #define CONFIG_VOL_MONITOR_IR36021_SET 423 #define CONFIG_VOL_MONITOR_IR36021_READ 424 /* The lowest and highest voltage allowed for T208xRDB */ 425 #define VDD_MV_MIN 819 426 #define VDD_MV_MAX 1212 427 428 /* 429 * RapidIO 430 */ 431 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 432 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 433 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 434 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 435 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 436 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 437 /* 438 * for slave u-boot IMAGE instored in master memory space, 439 * PHYS must be aligned based on the SIZE 440 */ 441 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 442 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 443 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 444 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 445 /* 446 * for slave UCODE and ENV instored in master memory space, 447 * PHYS must be aligned based on the SIZE 448 */ 449 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 450 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 451 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 452 453 /* slave core release by master*/ 454 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 455 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 456 457 /* 458 * SRIO_PCIE_BOOT - SLAVE 459 */ 460 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 461 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 462 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 463 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 464 #endif 465 466 /* 467 * eSPI - Enhanced SPI 468 */ 469 #ifdef CONFIG_SPI_FLASH 470 #define CONFIG_SPI_FLASH_BAR 471 #define CONFIG_SF_DEFAULT_SPEED 10000000 472 #define CONFIG_SF_DEFAULT_MODE 0 473 #endif 474 475 /* 476 * General PCI 477 * Memory space is mapped 1-1, but I/O space must start from 0. 478 */ 479 #define CONFIG_PCIE1 /* PCIE controller 1 */ 480 #define CONFIG_PCIE2 /* PCIE controller 2 */ 481 #define CONFIG_PCIE3 /* PCIE controller 3 */ 482 #define CONFIG_PCIE4 /* PCIE controller 4 */ 483 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 484 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 485 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 486 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 487 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 488 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 489 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 490 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 491 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 492 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 493 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 494 495 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 496 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 497 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 498 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 499 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 500 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 501 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 502 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 503 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 504 505 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 506 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 507 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 508 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 509 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 510 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 511 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 512 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 513 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 514 515 /* controller 4, Base address 203000 */ 516 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 517 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 518 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 519 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 520 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 521 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 522 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 523 524 #ifdef CONFIG_PCI 525 #define CONFIG_PCI_INDIRECT_BRIDGE 526 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ 527 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 528 #endif 529 530 /* Qman/Bman */ 531 #ifndef CONFIG_NOBQFMAN 532 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 533 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 534 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 535 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 536 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 537 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 538 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 539 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 540 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 541 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 542 CONFIG_SYS_BMAN_CENA_SIZE) 543 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 544 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 545 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 546 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 547 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 548 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 549 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 550 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 551 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 552 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 553 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 554 CONFIG_SYS_QMAN_CENA_SIZE) 555 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 556 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 557 558 #define CONFIG_SYS_DPAA_FMAN 559 #define CONFIG_SYS_DPAA_PME 560 #define CONFIG_SYS_PMAN 561 #define CONFIG_SYS_DPAA_DCE 562 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 563 #define CONFIG_SYS_INTERLAKEN 564 565 /* Default address of microcode for the Linux Fman driver */ 566 #if defined(CONFIG_SPIFLASH) 567 /* 568 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 569 * env, so we got 0x110000. 570 */ 571 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 572 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH 573 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 574 #define CONFIG_CORTINA_FW_ADDR 0x120000 575 576 #elif defined(CONFIG_SDCARD) 577 /* 578 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 579 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 580 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 581 */ 582 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 583 #define CONFIG_SYS_CORTINA_FW_IN_MMC 584 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 585 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) 586 587 #elif defined(CONFIG_NAND) 588 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 589 #define CONFIG_SYS_CORTINA_FW_IN_NAND 590 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 591 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 592 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 593 /* 594 * Slave has no ucode locally, it can fetch this from remote. When implementing 595 * in two corenet boards, slave's ucode could be stored in master's memory 596 * space, the address can be mapped from slave TLB->slave LAW-> 597 * slave SRIO or PCIE outbound window->master inbound window-> 598 * master LAW->the ucode address in master's memory space. 599 */ 600 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 601 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE 602 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 603 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000 604 #else 605 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 606 #define CONFIG_SYS_CORTINA_FW_IN_NOR 607 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 608 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000 609 #endif 610 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 611 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 612 #endif /* CONFIG_NOBQFMAN */ 613 614 #ifdef CONFIG_SYS_DPAA_FMAN 615 #define CONFIG_FMAN_ENET 616 #define CONFIG_PHYLIB_10G 617 #define CONFIG_PHY_AQUANTIA 618 #define CONFIG_PHY_CORTINA 619 #define CONFIG_PHY_REALTEK 620 #define CONFIG_CORTINA_FW_LENGTH 0x40000 621 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ 622 #define RGMII_PHY2_ADDR 0x02 623 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ 624 #define CORTINA_PHY_ADDR2 0x0d 625 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ 626 #define FM1_10GEC4_PHY_ADDR 0x01 627 #endif 628 629 #ifdef CONFIG_FMAN_ENET 630 #define CONFIG_MII /* MII PHY management */ 631 #define CONFIG_ETHPRIME "FM1@DTSEC3" 632 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 633 #endif 634 635 /* 636 * SATA 637 */ 638 #ifdef CONFIG_FSL_SATA_V2 639 #define CONFIG_LIBATA 640 #define CONFIG_FSL_SATA 641 #define CONFIG_SYS_SATA_MAX_DEVICE 2 642 #define CONFIG_SATA1 643 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 644 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 645 #define CONFIG_SATA2 646 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 647 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 648 #define CONFIG_LBA48 649 #define CONFIG_CMD_SATA 650 #endif 651 652 /* 653 * USB 654 */ 655 #ifdef CONFIG_USB_EHCI 656 #define CONFIG_USB_EHCI_FSL 657 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 658 #define CONFIG_HAS_FSL_DR_USB 659 #endif 660 661 /* 662 * SDHC 663 */ 664 #ifdef CONFIG_MMC 665 #define CONFIG_FSL_ESDHC 666 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 667 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 668 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 669 #endif 670 671 /* 672 * Dynamic MTD Partition support with mtdparts 673 */ 674 #ifdef CONFIG_MTD_NOR_FLASH 675 #define CONFIG_MTD_DEVICE 676 #define CONFIG_MTD_PARTITIONS 677 #define CONFIG_CMD_MTDPARTS 678 #define CONFIG_FLASH_CFI_MTD 679 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 680 "spi0=spife110000.1" 681 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 682 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 683 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \ 684 "1m(uboot),5m(kernel),128k(dtb),-(user)" 685 #endif 686 687 /* 688 * Environment 689 */ 690 691 /* 692 * Command line configuration. 693 */ 694 #define CONFIG_CMD_ERRATA 695 #define CONFIG_CMD_REGINFO 696 697 #ifdef CONFIG_PCI 698 #define CONFIG_CMD_PCI 699 #endif 700 701 /* Hash command with SHA acceleration supported in hardware */ 702 #ifdef CONFIG_FSL_CAAM 703 #define CONFIG_CMD_HASH 704 #define CONFIG_SHA_HW_ACCEL 705 #endif 706 707 /* 708 * Miscellaneous configurable options 709 */ 710 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 711 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 712 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 713 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 714 #ifdef CONFIG_CMD_KGDB 715 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 716 #else 717 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 718 #endif 719 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 720 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 721 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 722 723 /* 724 * For booting Linux, the board info and command line data 725 * have to be in the first 64 MB of memory, since this is 726 * the maximum mapped by the Linux kernel during initialization. 727 */ 728 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 729 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 730 731 #ifdef CONFIG_CMD_KGDB 732 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 733 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 734 #endif 735 736 /* 737 * Environment Configuration 738 */ 739 #define CONFIG_ROOTPATH "/opt/nfsroot" 740 #define CONFIG_BOOTFILE "uImage" 741 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 742 743 /* default location for tftp and bootm */ 744 #define CONFIG_LOADADDR 1000000 745 #define __USB_PHY_TYPE utmi 746 747 #define CONFIG_EXTRA_ENV_SETTINGS \ 748 "hwconfig=fsl_ddr:" \ 749 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 750 "bank_intlv=auto;" \ 751 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 752 "netdev=eth0\0" \ 753 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 754 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 755 "tftpflash=tftpboot $loadaddr $uboot && " \ 756 "protect off $ubootaddr +$filesize && " \ 757 "erase $ubootaddr +$filesize && " \ 758 "cp.b $loadaddr $ubootaddr $filesize && " \ 759 "protect on $ubootaddr +$filesize && " \ 760 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 761 "consoledev=ttyS0\0" \ 762 "ramdiskaddr=2000000\0" \ 763 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ 764 "fdtaddr=1e00000\0" \ 765 "fdtfile=t2080rdb/t2080rdb.dtb\0" \ 766 "bdev=sda3\0" 767 768 /* 769 * For emulation this causes u-boot to jump to the start of the 770 * proof point app code automatically 771 */ 772 #define CONFIG_PROOF_POINTS \ 773 "setenv bootargs root=/dev/$bdev rw " \ 774 "console=$consoledev,$baudrate $othbootargs;" \ 775 "cpu 1 release 0x29000000 - - -;" \ 776 "cpu 2 release 0x29000000 - - -;" \ 777 "cpu 3 release 0x29000000 - - -;" \ 778 "cpu 4 release 0x29000000 - - -;" \ 779 "cpu 5 release 0x29000000 - - -;" \ 780 "cpu 6 release 0x29000000 - - -;" \ 781 "cpu 7 release 0x29000000 - - -;" \ 782 "go 0x29000000" 783 784 #define CONFIG_HVBOOT \ 785 "setenv bootargs config-addr=0x60000000; " \ 786 "bootm 0x01000000 - 0x00f00000" 787 788 #define CONFIG_ALU \ 789 "setenv bootargs root=/dev/$bdev rw " \ 790 "console=$consoledev,$baudrate $othbootargs;" \ 791 "cpu 1 release 0x01000000 - - -;" \ 792 "cpu 2 release 0x01000000 - - -;" \ 793 "cpu 3 release 0x01000000 - - -;" \ 794 "cpu 4 release 0x01000000 - - -;" \ 795 "cpu 5 release 0x01000000 - - -;" \ 796 "cpu 6 release 0x01000000 - - -;" \ 797 "cpu 7 release 0x01000000 - - -;" \ 798 "go 0x01000000" 799 800 #define CONFIG_LINUX \ 801 "setenv bootargs root=/dev/ram rw " \ 802 "console=$consoledev,$baudrate $othbootargs;" \ 803 "setenv ramdiskaddr 0x02000000;" \ 804 "setenv fdtaddr 0x00c00000;" \ 805 "setenv loadaddr 0x1000000;" \ 806 "bootm $loadaddr $ramdiskaddr $fdtaddr" 807 808 #define CONFIG_HDBOOT \ 809 "setenv bootargs root=/dev/$bdev rw " \ 810 "console=$consoledev,$baudrate $othbootargs;" \ 811 "tftp $loadaddr $bootfile;" \ 812 "tftp $fdtaddr $fdtfile;" \ 813 "bootm $loadaddr - $fdtaddr" 814 815 #define CONFIG_NFSBOOTCOMMAND \ 816 "setenv bootargs root=/dev/nfs rw " \ 817 "nfsroot=$serverip:$rootpath " \ 818 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 819 "console=$consoledev,$baudrate $othbootargs;" \ 820 "tftp $loadaddr $bootfile;" \ 821 "tftp $fdtaddr $fdtfile;" \ 822 "bootm $loadaddr - $fdtaddr" 823 824 #define CONFIG_RAMBOOTCOMMAND \ 825 "setenv bootargs root=/dev/ram rw " \ 826 "console=$consoledev,$baudrate $othbootargs;" \ 827 "tftp $ramdiskaddr $ramdiskfile;" \ 828 "tftp $loadaddr $bootfile;" \ 829 "tftp $fdtaddr $fdtfile;" \ 830 "bootm $loadaddr $ramdiskaddr $fdtaddr" 831 832 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 833 834 #include <asm/fsl_secure_boot.h> 835 836 #endif /* __T2080RDB_H */ 837