1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_USB_EHCI 16 #if defined(CONFIG_ARCH_T2080) 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 19 #define CONFIG_SRIO1 /* SRIO port 1 */ 20 #define CONFIG_SRIO2 /* SRIO port 2 */ 21 #elif defined(CONFIG_ARCH_T2081) 22 #endif 23 24 /* High Level Configuration Options */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 36 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 37 #define CONFIG_ENV_OVERWRITE 38 39 #ifdef CONFIG_RAMBOOT_PBL 40 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 41 42 #define CONFIG_SPL_FLUSH_IMAGE 43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 44 #define CONFIG_SYS_TEXT_BASE 0x00201000 45 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 46 #define CONFIG_SPL_PAD_TO 0x40000 47 #define CONFIG_SPL_MAX_SIZE 0x28000 48 #define RESET_VECTOR_OFFSET 0x27FFC 49 #define BOOT_PAGE_OFFSET 0x27000 50 #ifdef CONFIG_SPL_BUILD 51 #define CONFIG_SPL_SKIP_RELOCATE 52 #define CONFIG_SPL_COMMON_INIT_DDR 53 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 54 #endif 55 56 #ifdef CONFIG_NAND 57 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 58 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 59 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 60 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 61 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 62 #if defined(CONFIG_ARCH_T2080) 63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 64 #elif defined(CONFIG_ARCH_T2081) 65 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 66 #endif 67 #define CONFIG_SPL_NAND_BOOT 68 #endif 69 70 #ifdef CONFIG_SPIFLASH 71 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 72 #define CONFIG_SPL_SPI_FLASH_MINIMAL 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 78 #ifndef CONFIG_SPL_BUILD 79 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 80 #endif 81 #if defined(CONFIG_ARCH_T2080) 82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 83 #elif defined(CONFIG_ARCH_T2081) 84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 85 #endif 86 #define CONFIG_SPL_SPI_BOOT 87 #endif 88 89 #ifdef CONFIG_SDCARD 90 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 91 #define CONFIG_SPL_MMC_MINIMAL 92 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 93 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 94 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 95 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 96 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 97 #ifndef CONFIG_SPL_BUILD 98 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 99 #endif 100 #if defined(CONFIG_ARCH_T2080) 101 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 102 #elif defined(CONFIG_ARCH_T2081) 103 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 104 #endif 105 #define CONFIG_SPL_MMC_BOOT 106 #endif 107 108 #endif /* CONFIG_RAMBOOT_PBL */ 109 110 #define CONFIG_SRIO_PCIE_BOOT_MASTER 111 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 112 /* Set 1M boot space */ 113 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 114 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 115 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 116 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 117 #endif 118 119 #ifndef CONFIG_SYS_TEXT_BASE 120 #define CONFIG_SYS_TEXT_BASE 0xeff40000 121 #endif 122 123 #ifndef CONFIG_RESET_VECTOR_ADDRESS 124 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 125 #endif 126 127 /* 128 * These can be toggled for performance analysis, otherwise use default. 129 */ 130 #define CONFIG_SYS_CACHE_STASHING 131 #define CONFIG_BTB /* toggle branch predition */ 132 #define CONFIG_DDR_ECC 133 #ifdef CONFIG_DDR_ECC 134 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 135 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 136 #endif 137 138 #ifdef CONFIG_MTD_NOR_FLASH 139 #define CONFIG_FLASH_CFI_DRIVER 140 #define CONFIG_SYS_FLASH_CFI 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 142 #endif 143 144 #if defined(CONFIG_SPIFLASH) 145 #define CONFIG_SYS_EXTRA_ENV_RELOC 146 #define CONFIG_ENV_IS_IN_SPI_FLASH 147 #define CONFIG_ENV_SPI_BUS 0 148 #define CONFIG_ENV_SPI_CS 0 149 #define CONFIG_ENV_SPI_MAX_HZ 10000000 150 #define CONFIG_ENV_SPI_MODE 0 151 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 152 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 153 #define CONFIG_ENV_SECT_SIZE 0x10000 154 #elif defined(CONFIG_SDCARD) 155 #define CONFIG_SYS_EXTRA_ENV_RELOC 156 #define CONFIG_ENV_IS_IN_MMC 157 #define CONFIG_SYS_MMC_ENV_DEV 0 158 #define CONFIG_ENV_SIZE 0x2000 159 #define CONFIG_ENV_OFFSET (512 * 0x800) 160 #elif defined(CONFIG_NAND) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_IS_IN_NAND 163 #define CONFIG_ENV_SIZE 0x2000 164 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 165 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 166 #define CONFIG_ENV_IS_IN_REMOTE 167 #define CONFIG_ENV_ADDR 0xffe20000 168 #define CONFIG_ENV_SIZE 0x2000 169 #elif defined(CONFIG_ENV_IS_NOWHERE) 170 #define CONFIG_ENV_SIZE 0x2000 171 #else 172 #define CONFIG_ENV_IS_IN_FLASH 173 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 174 #define CONFIG_ENV_SIZE 0x2000 175 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 176 #endif 177 178 #ifndef __ASSEMBLY__ 179 unsigned long get_board_sys_clk(void); 180 unsigned long get_board_ddr_clk(void); 181 #endif 182 183 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 184 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 185 186 /* 187 * Config the L3 Cache as L3 SRAM 188 */ 189 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 190 #define CONFIG_SYS_L3_SIZE (512 << 10) 191 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 192 #ifdef CONFIG_RAMBOOT_PBL 193 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 194 #endif 195 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 196 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 197 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 198 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 199 200 #define CONFIG_SYS_DCSRBAR 0xf0000000 201 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 202 203 /* EEPROM */ 204 #define CONFIG_ID_EEPROM 205 #define CONFIG_SYS_I2C_EEPROM_NXID 206 #define CONFIG_SYS_EEPROM_BUS_NUM 0 207 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 208 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 209 210 /* 211 * DDR Setup 212 */ 213 #define CONFIG_VERY_BIG_RAM 214 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 215 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 216 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 217 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 218 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 219 #define CONFIG_DDR_SPD 220 #define CONFIG_FSL_DDR_INTERACTIVE 221 #define CONFIG_SYS_SPD_BUS_NUM 0 222 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 223 #define SPD_EEPROM_ADDRESS1 0x51 224 #define SPD_EEPROM_ADDRESS2 0x52 225 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 226 #define CTRL_INTLV_PREFERED cacheline 227 228 /* 229 * IFC Definitions 230 */ 231 #define CONFIG_SYS_FLASH_BASE 0xe0000000 232 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 233 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 234 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 235 + 0x8000000) | \ 236 CSPR_PORT_SIZE_16 | \ 237 CSPR_MSEL_NOR | \ 238 CSPR_V) 239 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 240 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 241 CSPR_PORT_SIZE_16 | \ 242 CSPR_MSEL_NOR | \ 243 CSPR_V) 244 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 245 /* NOR Flash Timing Params */ 246 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 247 248 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 249 FTIM0_NOR_TEADC(0x5) | \ 250 FTIM0_NOR_TEAHC(0x5)) 251 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 252 FTIM1_NOR_TRAD_NOR(0x1A) |\ 253 FTIM1_NOR_TSEQRAD_NOR(0x13)) 254 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 255 FTIM2_NOR_TCH(0x4) | \ 256 FTIM2_NOR_TWPH(0x0E) | \ 257 FTIM2_NOR_TWP(0x1c)) 258 #define CONFIG_SYS_NOR_FTIM3 0x0 259 260 #define CONFIG_SYS_FLASH_QUIET_TEST 261 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 262 263 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 264 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 265 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 266 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 267 268 #define CONFIG_SYS_FLASH_EMPTY_INFO 269 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 270 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 271 272 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 273 #define QIXIS_BASE 0xffdf0000 274 #define QIXIS_LBMAP_SWITCH 6 275 #define QIXIS_LBMAP_MASK 0x0f 276 #define QIXIS_LBMAP_SHIFT 0 277 #define QIXIS_LBMAP_DFLTBANK 0x00 278 #define QIXIS_LBMAP_ALTBANK 0x04 279 #define QIXIS_LBMAP_NAND 0x09 280 #define QIXIS_LBMAP_SD 0x00 281 #define QIXIS_RCW_SRC_NAND 0x104 282 #define QIXIS_RCW_SRC_SD 0x040 283 #define QIXIS_RST_CTL_RESET 0x83 284 #define QIXIS_RST_FORCE_MEM 0x1 285 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 286 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 287 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 288 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 289 290 #define CONFIG_SYS_CSPR3_EXT (0xf) 291 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 292 | CSPR_PORT_SIZE_8 \ 293 | CSPR_MSEL_GPCM \ 294 | CSPR_V) 295 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 296 #define CONFIG_SYS_CSOR3 0x0 297 /* QIXIS Timing parameters for IFC CS3 */ 298 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 299 FTIM0_GPCM_TEADC(0x0e) | \ 300 FTIM0_GPCM_TEAHC(0x0e)) 301 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 302 FTIM1_GPCM_TRAD(0x3f)) 303 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 304 FTIM2_GPCM_TCH(0x8) | \ 305 FTIM2_GPCM_TWP(0x1f)) 306 #define CONFIG_SYS_CS3_FTIM3 0x0 307 308 /* NAND Flash on IFC */ 309 #define CONFIG_NAND_FSL_IFC 310 #define CONFIG_SYS_NAND_BASE 0xff800000 311 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 312 313 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 314 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 315 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 316 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 317 | CSPR_V) 318 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 319 320 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 321 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 322 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 323 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 324 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 325 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 326 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 327 328 #define CONFIG_SYS_NAND_ONFI_DETECTION 329 330 /* ONFI NAND Flash mode0 Timing Params */ 331 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 332 FTIM0_NAND_TWP(0x18) | \ 333 FTIM0_NAND_TWCHT(0x07) | \ 334 FTIM0_NAND_TWH(0x0a)) 335 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 336 FTIM1_NAND_TWBE(0x39) | \ 337 FTIM1_NAND_TRR(0x0e) | \ 338 FTIM1_NAND_TRP(0x18)) 339 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 340 FTIM2_NAND_TREH(0x0a) | \ 341 FTIM2_NAND_TWHRE(0x1e)) 342 #define CONFIG_SYS_NAND_FTIM3 0x0 343 344 #define CONFIG_SYS_NAND_DDR_LAW 11 345 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 346 #define CONFIG_SYS_MAX_NAND_DEVICE 1 347 #define CONFIG_CMD_NAND 348 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 349 350 #if defined(CONFIG_NAND) 351 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 352 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 353 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 354 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 355 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 356 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 357 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 358 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 359 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 360 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 361 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 362 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 363 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 364 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 365 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 366 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 367 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 368 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 369 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 370 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 371 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 372 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 373 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 374 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 375 #else 376 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 377 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 378 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 379 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 380 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 381 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 382 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 383 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 384 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 385 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 386 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 387 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 388 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 389 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 390 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 391 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 392 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 393 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 394 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 395 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 396 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 397 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 398 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 399 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 400 #endif 401 402 #if defined(CONFIG_RAMBOOT_PBL) 403 #define CONFIG_SYS_RAMBOOT 404 #endif 405 406 #ifdef CONFIG_SPL_BUILD 407 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 408 #else 409 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 410 #endif 411 412 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 413 #define CONFIG_MISC_INIT_R 414 #define CONFIG_HWCONFIG 415 416 /* define to use L1 as initial stack */ 417 #define CONFIG_L1_INIT_RAM 418 #define CONFIG_SYS_INIT_RAM_LOCK 419 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 421 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 422 /* The assembler doesn't like typecast */ 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 424 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 425 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 426 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 427 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 428 GENERATED_GBL_DATA_SIZE) 429 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 430 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 431 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 432 433 /* 434 * Serial Port 435 */ 436 #define CONFIG_CONS_INDEX 1 437 #define CONFIG_SYS_NS16550_SERIAL 438 #define CONFIG_SYS_NS16550_REG_SIZE 1 439 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 440 #define CONFIG_SYS_BAUDRATE_TABLE \ 441 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 442 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 443 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 444 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 445 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 446 447 /* 448 * I2C 449 */ 450 #define CONFIG_SYS_I2C 451 #define CONFIG_SYS_I2C_FSL 452 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 453 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 454 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 455 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 456 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 457 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 458 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 459 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 460 #define CONFIG_SYS_FSL_I2C_SPEED 100000 461 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 462 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 463 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 464 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 465 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 466 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 467 #define I2C_MUX_CH_DEFAULT 0x8 468 469 #define I2C_MUX_CH_VOL_MONITOR 0xa 470 471 /* Voltage monitor on channel 2*/ 472 #define I2C_VOL_MONITOR_ADDR 0x40 473 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 474 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 475 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 476 477 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 478 #ifndef CONFIG_SPL_BUILD 479 #define CONFIG_VID 480 #endif 481 #define CONFIG_VOL_MONITOR_IR36021_SET 482 #define CONFIG_VOL_MONITOR_IR36021_READ 483 /* The lowest and highest voltage allowed for T208xQDS */ 484 #define VDD_MV_MIN 819 485 #define VDD_MV_MAX 1212 486 487 /* 488 * RapidIO 489 */ 490 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 491 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 492 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 493 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 494 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 495 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 496 /* 497 * for slave u-boot IMAGE instored in master memory space, 498 * PHYS must be aligned based on the SIZE 499 */ 500 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 504 /* 505 * for slave UCODE and ENV instored in master memory space, 506 * PHYS must be aligned based on the SIZE 507 */ 508 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 509 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 510 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 511 512 /* slave core release by master*/ 513 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 514 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 515 516 /* 517 * SRIO_PCIE_BOOT - SLAVE 518 */ 519 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 520 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 521 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 522 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 523 #endif 524 525 /* 526 * eSPI - Enhanced SPI 527 */ 528 #ifdef CONFIG_SPI_FLASH 529 #ifndef CONFIG_SPL_BUILD 530 #endif 531 532 #define CONFIG_SPI_FLASH_BAR 533 #define CONFIG_SF_DEFAULT_SPEED 10000000 534 #define CONFIG_SF_DEFAULT_MODE 0 535 #endif 536 537 /* 538 * General PCI 539 * Memory space is mapped 1-1, but I/O space must start from 0. 540 */ 541 #define CONFIG_PCIE1 /* PCIE controller 1 */ 542 #define CONFIG_PCIE2 /* PCIE controller 2 */ 543 #define CONFIG_PCIE3 /* PCIE controller 3 */ 544 #define CONFIG_PCIE4 /* PCIE controller 4 */ 545 #define CONFIG_FSL_PCIE_RESET 546 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 547 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 548 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 549 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 550 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 551 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 552 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 553 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 554 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 555 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 556 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 557 558 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 559 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 560 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 561 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 562 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 563 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 564 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 565 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 566 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 567 568 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 569 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 570 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 571 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 572 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 573 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 574 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 575 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 576 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 577 578 /* controller 4, Base address 203000 */ 579 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 580 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 581 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 582 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 583 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 584 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 585 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 586 587 #ifdef CONFIG_PCI 588 #define CONFIG_PCI_INDIRECT_BRIDGE 589 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 590 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 591 #endif 592 593 /* Qman/Bman */ 594 #ifndef CONFIG_NOBQFMAN 595 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 596 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 597 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 598 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 599 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 600 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 601 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 602 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 603 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 604 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 605 CONFIG_SYS_BMAN_CENA_SIZE) 606 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 607 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 608 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 609 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 610 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 611 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 612 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 613 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 614 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 615 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 616 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 617 CONFIG_SYS_QMAN_CENA_SIZE) 618 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 619 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 620 621 #define CONFIG_SYS_DPAA_FMAN 622 #define CONFIG_SYS_DPAA_PME 623 #define CONFIG_SYS_PMAN 624 #define CONFIG_SYS_DPAA_DCE 625 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 626 #define CONFIG_SYS_INTERLAKEN 627 628 /* Default address of microcode for the Linux Fman driver */ 629 #if defined(CONFIG_SPIFLASH) 630 /* 631 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 632 * env, so we got 0x110000. 633 */ 634 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 635 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 636 #elif defined(CONFIG_SDCARD) 637 /* 638 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 639 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 640 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 641 */ 642 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 643 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 644 #elif defined(CONFIG_NAND) 645 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 646 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 647 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 648 /* 649 * Slave has no ucode locally, it can fetch this from remote. When implementing 650 * in two corenet boards, slave's ucode could be stored in master's memory 651 * space, the address can be mapped from slave TLB->slave LAW-> 652 * slave SRIO or PCIE outbound window->master inbound window-> 653 * master LAW->the ucode address in master's memory space. 654 */ 655 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 656 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 657 #else 658 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 659 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 660 #endif 661 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 662 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 663 #endif /* CONFIG_NOBQFMAN */ 664 665 #ifdef CONFIG_SYS_DPAA_FMAN 666 #define CONFIG_FMAN_ENET 667 #define CONFIG_PHYLIB_10G 668 #define CONFIG_PHY_VITESSE 669 #define CONFIG_PHY_REALTEK 670 #define CONFIG_PHY_TERANETICS 671 #define RGMII_PHY1_ADDR 0x1 672 #define RGMII_PHY2_ADDR 0x2 673 #define FM1_10GEC1_PHY_ADDR 0x3 674 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 675 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 676 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 677 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 678 #endif 679 680 #ifdef CONFIG_FMAN_ENET 681 #define CONFIG_MII /* MII PHY management */ 682 #define CONFIG_ETHPRIME "FM1@DTSEC3" 683 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 684 #endif 685 686 /* 687 * SATA 688 */ 689 #ifdef CONFIG_FSL_SATA_V2 690 #define CONFIG_LIBATA 691 #define CONFIG_FSL_SATA 692 #define CONFIG_SYS_SATA_MAX_DEVICE 2 693 #define CONFIG_SATA1 694 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 695 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 696 #define CONFIG_SATA2 697 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 698 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 699 #define CONFIG_LBA48 700 #define CONFIG_CMD_SATA 701 #endif 702 703 /* 704 * USB 705 */ 706 #ifdef CONFIG_USB_EHCI 707 #define CONFIG_USB_EHCI_FSL 708 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 709 #define CONFIG_HAS_FSL_DR_USB 710 #endif 711 712 /* 713 * SDHC 714 */ 715 #ifdef CONFIG_MMC 716 #define CONFIG_FSL_ESDHC 717 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 718 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 719 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 720 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 721 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 722 #endif 723 724 /* 725 * Dynamic MTD Partition support with mtdparts 726 */ 727 #ifdef CONFIG_MTD_NOR_FLASH 728 #define CONFIG_MTD_DEVICE 729 #define CONFIG_MTD_PARTITIONS 730 #define CONFIG_CMD_MTDPARTS 731 #define CONFIG_FLASH_CFI_MTD 732 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 733 "spi0=spife110000.0" 734 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 735 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 736 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 737 "1m(uboot),5m(kernel),128k(dtb),-(user)" 738 #endif 739 740 /* 741 * Environment 742 */ 743 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 744 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 745 746 /* 747 * Command line configuration. 748 */ 749 #define CONFIG_CMD_ERRATA 750 #define CONFIG_CMD_IRQ 751 #define CONFIG_CMD_REGINFO 752 753 #ifdef CONFIG_PCI 754 #define CONFIG_CMD_PCI 755 #endif 756 757 /* Hash command with SHA acceleration supported in hardware */ 758 #ifdef CONFIG_FSL_CAAM 759 #define CONFIG_CMD_HASH 760 #define CONFIG_SHA_HW_ACCEL 761 #endif 762 763 /* 764 * Miscellaneous configurable options 765 */ 766 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 767 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 768 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 769 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 770 #ifdef CONFIG_CMD_KGDB 771 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 772 #else 773 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 774 #endif 775 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 776 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 777 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 778 779 /* 780 * For booting Linux, the board info and command line data 781 * have to be in the first 64 MB of memory, since this is 782 * the maximum mapped by the Linux kernel during initialization. 783 */ 784 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 785 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 786 787 #ifdef CONFIG_CMD_KGDB 788 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 789 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 790 #endif 791 792 /* 793 * Environment Configuration 794 */ 795 #define CONFIG_ROOTPATH "/opt/nfsroot" 796 #define CONFIG_BOOTFILE "uImage" 797 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 798 799 /* default location for tftp and bootm */ 800 #define CONFIG_LOADADDR 1000000 801 #define CONFIG_BAUDRATE 115200 802 #define __USB_PHY_TYPE utmi 803 804 #define CONFIG_EXTRA_ENV_SETTINGS \ 805 "hwconfig=fsl_ddr:" \ 806 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 807 "bank_intlv=auto;" \ 808 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 809 "netdev=eth0\0" \ 810 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 811 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 812 "tftpflash=tftpboot $loadaddr $uboot && " \ 813 "protect off $ubootaddr +$filesize && " \ 814 "erase $ubootaddr +$filesize && " \ 815 "cp.b $loadaddr $ubootaddr $filesize && " \ 816 "protect on $ubootaddr +$filesize && " \ 817 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 818 "consoledev=ttyS0\0" \ 819 "ramdiskaddr=2000000\0" \ 820 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 821 "fdtaddr=1e00000\0" \ 822 "fdtfile=t2080qds/t2080qds.dtb\0" \ 823 "bdev=sda3\0" 824 825 /* 826 * For emulation this causes u-boot to jump to the start of the 827 * proof point app code automatically 828 */ 829 #define CONFIG_PROOF_POINTS \ 830 "setenv bootargs root=/dev/$bdev rw " \ 831 "console=$consoledev,$baudrate $othbootargs;" \ 832 "cpu 1 release 0x29000000 - - -;" \ 833 "cpu 2 release 0x29000000 - - -;" \ 834 "cpu 3 release 0x29000000 - - -;" \ 835 "cpu 4 release 0x29000000 - - -;" \ 836 "cpu 5 release 0x29000000 - - -;" \ 837 "cpu 6 release 0x29000000 - - -;" \ 838 "cpu 7 release 0x29000000 - - -;" \ 839 "go 0x29000000" 840 841 #define CONFIG_HVBOOT \ 842 "setenv bootargs config-addr=0x60000000; " \ 843 "bootm 0x01000000 - 0x00f00000" 844 845 #define CONFIG_ALU \ 846 "setenv bootargs root=/dev/$bdev rw " \ 847 "console=$consoledev,$baudrate $othbootargs;" \ 848 "cpu 1 release 0x01000000 - - -;" \ 849 "cpu 2 release 0x01000000 - - -;" \ 850 "cpu 3 release 0x01000000 - - -;" \ 851 "cpu 4 release 0x01000000 - - -;" \ 852 "cpu 5 release 0x01000000 - - -;" \ 853 "cpu 6 release 0x01000000 - - -;" \ 854 "cpu 7 release 0x01000000 - - -;" \ 855 "go 0x01000000" 856 857 #define CONFIG_LINUX \ 858 "setenv bootargs root=/dev/ram rw " \ 859 "console=$consoledev,$baudrate $othbootargs;" \ 860 "setenv ramdiskaddr 0x02000000;" \ 861 "setenv fdtaddr 0x00c00000;" \ 862 "setenv loadaddr 0x1000000;" \ 863 "bootm $loadaddr $ramdiskaddr $fdtaddr" 864 865 #define CONFIG_HDBOOT \ 866 "setenv bootargs root=/dev/$bdev rw " \ 867 "console=$consoledev,$baudrate $othbootargs;" \ 868 "tftp $loadaddr $bootfile;" \ 869 "tftp $fdtaddr $fdtfile;" \ 870 "bootm $loadaddr - $fdtaddr" 871 872 #define CONFIG_NFSBOOTCOMMAND \ 873 "setenv bootargs root=/dev/nfs rw " \ 874 "nfsroot=$serverip:$rootpath " \ 875 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 876 "console=$consoledev,$baudrate $othbootargs;" \ 877 "tftp $loadaddr $bootfile;" \ 878 "tftp $fdtaddr $fdtfile;" \ 879 "bootm $loadaddr - $fdtaddr" 880 881 #define CONFIG_RAMBOOTCOMMAND \ 882 "setenv bootargs root=/dev/ram rw " \ 883 "console=$consoledev,$baudrate $othbootargs;" \ 884 "tftp $ramdiskaddr $ramdiskfile;" \ 885 "tftp $loadaddr $bootfile;" \ 886 "tftp $fdtaddr $fdtfile;" \ 887 "bootm $loadaddr $ramdiskaddr $fdtaddr" 888 889 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 890 891 #include <asm/fsl_secure_boot.h> 892 893 #endif /* __T208xQDS_H */ 894