1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T2080/T2081 QDS board configuration file 8 */ 9 10 #ifndef __T208xQDS_H 11 #define __T208xQDS_H 12 13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 14 #if defined(CONFIG_ARCH_T2080) 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 17 #define CONFIG_SRIO1 /* SRIO port 1 */ 18 #define CONFIG_SRIO2 /* SRIO port 2 */ 19 #elif defined(CONFIG_ARCH_T2081) 20 #endif 21 22 /* High Level Configuration Options */ 23 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 24 #define CONFIG_ENABLE_36BIT_PHYS 25 26 #ifdef CONFIG_PHYS_64BIT 27 #define CONFIG_ADDR_MAP 1 28 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 29 #endif 30 31 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 32 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 33 #define CONFIG_ENV_OVERWRITE 34 35 #ifdef CONFIG_RAMBOOT_PBL 36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 37 38 #define CONFIG_SPL_FLUSH_IMAGE 39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 40 #define CONFIG_SPL_PAD_TO 0x40000 41 #define CONFIG_SPL_MAX_SIZE 0x28000 42 #define RESET_VECTOR_OFFSET 0x27FFC 43 #define BOOT_PAGE_OFFSET 0x27000 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #endif 49 50 #ifdef CONFIG_NAND 51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 54 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 56 #if defined(CONFIG_ARCH_T2080) 57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 58 #elif defined(CONFIG_ARCH_T2081) 59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 60 #endif 61 #define CONFIG_SPL_NAND_BOOT 62 #endif 63 64 #ifdef CONFIG_SPIFLASH 65 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 66 #define CONFIG_SPL_SPI_FLASH_MINIMAL 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 71 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 72 #ifndef CONFIG_SPL_BUILD 73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 74 #endif 75 #if defined(CONFIG_ARCH_T2080) 76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 77 #elif defined(CONFIG_ARCH_T2081) 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 79 #endif 80 #define CONFIG_SPL_SPI_BOOT 81 #endif 82 83 #ifdef CONFIG_SDCARD 84 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 85 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 86 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 87 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 88 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 90 #ifndef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #endif 93 #if defined(CONFIG_ARCH_T2080) 94 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 95 #elif defined(CONFIG_ARCH_T2081) 96 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 97 #endif 98 #define CONFIG_SPL_MMC_BOOT 99 #endif 100 101 #endif /* CONFIG_RAMBOOT_PBL */ 102 103 #define CONFIG_SRIO_PCIE_BOOT_MASTER 104 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 105 /* Set 1M boot space */ 106 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 107 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 108 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 109 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 110 #endif 111 112 #ifndef CONFIG_RESET_VECTOR_ADDRESS 113 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 114 #endif 115 116 /* 117 * These can be toggled for performance analysis, otherwise use default. 118 */ 119 #define CONFIG_SYS_CACHE_STASHING 120 #define CONFIG_BTB /* toggle branch predition */ 121 #define CONFIG_DDR_ECC 122 #ifdef CONFIG_DDR_ECC 123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 124 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 125 #endif 126 127 #ifdef CONFIG_MTD_NOR_FLASH 128 #define CONFIG_FLASH_CFI_DRIVER 129 #define CONFIG_SYS_FLASH_CFI 130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 131 #endif 132 133 #if defined(CONFIG_SPIFLASH) 134 #define CONFIG_ENV_SPI_BUS 0 135 #define CONFIG_ENV_SPI_CS 0 136 #define CONFIG_ENV_SPI_MAX_HZ 10000000 137 #define CONFIG_ENV_SPI_MODE 0 138 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 139 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 140 #define CONFIG_ENV_SECT_SIZE 0x10000 141 #elif defined(CONFIG_SDCARD) 142 #define CONFIG_SYS_MMC_ENV_DEV 0 143 #define CONFIG_ENV_SIZE 0x2000 144 #define CONFIG_ENV_OFFSET (512 * 0x800) 145 #elif defined(CONFIG_NAND) 146 #define CONFIG_ENV_SIZE 0x2000 147 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 148 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 149 #define CONFIG_ENV_ADDR 0xffe20000 150 #define CONFIG_ENV_SIZE 0x2000 151 #elif defined(CONFIG_ENV_IS_NOWHERE) 152 #define CONFIG_ENV_SIZE 0x2000 153 #else 154 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 155 #define CONFIG_ENV_SIZE 0x2000 156 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 157 #endif 158 159 #ifndef __ASSEMBLY__ 160 unsigned long get_board_sys_clk(void); 161 unsigned long get_board_ddr_clk(void); 162 #endif 163 164 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 165 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 166 167 /* 168 * Config the L3 Cache as L3 SRAM 169 */ 170 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 171 #define CONFIG_SYS_L3_SIZE (512 << 10) 172 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 173 #ifdef CONFIG_RAMBOOT_PBL 174 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 175 #endif 176 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 177 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 178 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 179 180 #define CONFIG_SYS_DCSRBAR 0xf0000000 181 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 182 183 /* EEPROM */ 184 #define CONFIG_ID_EEPROM 185 #define CONFIG_SYS_I2C_EEPROM_NXID 186 #define CONFIG_SYS_EEPROM_BUS_NUM 0 187 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 188 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 189 190 /* 191 * DDR Setup 192 */ 193 #define CONFIG_VERY_BIG_RAM 194 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 195 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 196 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 197 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 198 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 199 #define CONFIG_DDR_SPD 200 #define CONFIG_FSL_DDR_INTERACTIVE 201 #define CONFIG_SYS_SPD_BUS_NUM 0 202 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 203 #define SPD_EEPROM_ADDRESS1 0x51 204 #define SPD_EEPROM_ADDRESS2 0x52 205 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 206 #define CTRL_INTLV_PREFERED cacheline 207 208 /* 209 * IFC Definitions 210 */ 211 #define CONFIG_SYS_FLASH_BASE 0xe0000000 212 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 213 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 214 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 215 + 0x8000000) | \ 216 CSPR_PORT_SIZE_16 | \ 217 CSPR_MSEL_NOR | \ 218 CSPR_V) 219 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 220 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 221 CSPR_PORT_SIZE_16 | \ 222 CSPR_MSEL_NOR | \ 223 CSPR_V) 224 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 225 /* NOR Flash Timing Params */ 226 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 227 228 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 229 FTIM0_NOR_TEADC(0x5) | \ 230 FTIM0_NOR_TEAHC(0x5)) 231 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 232 FTIM1_NOR_TRAD_NOR(0x1A) |\ 233 FTIM1_NOR_TSEQRAD_NOR(0x13)) 234 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 235 FTIM2_NOR_TCH(0x4) | \ 236 FTIM2_NOR_TWPH(0x0E) | \ 237 FTIM2_NOR_TWP(0x1c)) 238 #define CONFIG_SYS_NOR_FTIM3 0x0 239 240 #define CONFIG_SYS_FLASH_QUIET_TEST 241 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 242 243 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 244 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 245 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 247 248 #define CONFIG_SYS_FLASH_EMPTY_INFO 249 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 250 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 251 252 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 253 #define QIXIS_BASE 0xffdf0000 254 #define QIXIS_LBMAP_SWITCH 6 255 #define QIXIS_LBMAP_MASK 0x0f 256 #define QIXIS_LBMAP_SHIFT 0 257 #define QIXIS_LBMAP_DFLTBANK 0x00 258 #define QIXIS_LBMAP_ALTBANK 0x04 259 #define QIXIS_LBMAP_NAND 0x09 260 #define QIXIS_LBMAP_SD 0x00 261 #define QIXIS_RCW_SRC_NAND 0x104 262 #define QIXIS_RCW_SRC_SD 0x040 263 #define QIXIS_RST_CTL_RESET 0x83 264 #define QIXIS_RST_FORCE_MEM 0x1 265 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 266 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 267 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 268 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 269 270 #define CONFIG_SYS_CSPR3_EXT (0xf) 271 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 272 | CSPR_PORT_SIZE_8 \ 273 | CSPR_MSEL_GPCM \ 274 | CSPR_V) 275 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 276 #define CONFIG_SYS_CSOR3 0x0 277 /* QIXIS Timing parameters for IFC CS3 */ 278 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 279 FTIM0_GPCM_TEADC(0x0e) | \ 280 FTIM0_GPCM_TEAHC(0x0e)) 281 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 282 FTIM1_GPCM_TRAD(0x3f)) 283 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 284 FTIM2_GPCM_TCH(0x8) | \ 285 FTIM2_GPCM_TWP(0x1f)) 286 #define CONFIG_SYS_CS3_FTIM3 0x0 287 288 /* NAND Flash on IFC */ 289 #define CONFIG_NAND_FSL_IFC 290 #define CONFIG_SYS_NAND_BASE 0xff800000 291 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 292 293 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 294 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 295 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 296 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 297 | CSPR_V) 298 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 299 300 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 301 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 302 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 303 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 304 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 305 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 306 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 307 308 #define CONFIG_SYS_NAND_ONFI_DETECTION 309 310 /* ONFI NAND Flash mode0 Timing Params */ 311 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 312 FTIM0_NAND_TWP(0x18) | \ 313 FTIM0_NAND_TWCHT(0x07) | \ 314 FTIM0_NAND_TWH(0x0a)) 315 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 316 FTIM1_NAND_TWBE(0x39) | \ 317 FTIM1_NAND_TRR(0x0e) | \ 318 FTIM1_NAND_TRP(0x18)) 319 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 320 FTIM2_NAND_TREH(0x0a) | \ 321 FTIM2_NAND_TWHRE(0x1e)) 322 #define CONFIG_SYS_NAND_FTIM3 0x0 323 324 #define CONFIG_SYS_NAND_DDR_LAW 11 325 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 326 #define CONFIG_SYS_MAX_NAND_DEVICE 1 327 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 328 329 #if defined(CONFIG_NAND) 330 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 331 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 332 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 333 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 334 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 335 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 336 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 337 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 338 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 339 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 340 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 341 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 342 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 343 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 344 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 345 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 346 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 347 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 348 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 349 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 350 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 351 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 352 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 353 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 354 #else 355 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 356 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 357 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 358 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 359 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 360 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 361 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 362 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 363 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 364 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 365 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 366 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 367 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 368 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 369 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 370 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 371 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 372 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 373 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 374 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 375 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 376 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 377 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 378 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 379 #endif 380 381 #if defined(CONFIG_RAMBOOT_PBL) 382 #define CONFIG_SYS_RAMBOOT 383 #endif 384 385 #ifdef CONFIG_SPL_BUILD 386 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 387 #else 388 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 389 #endif 390 391 #define CONFIG_HWCONFIG 392 393 /* define to use L1 as initial stack */ 394 #define CONFIG_L1_INIT_RAM 395 #define CONFIG_SYS_INIT_RAM_LOCK 396 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 397 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 398 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 399 /* The assembler doesn't like typecast */ 400 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 401 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 402 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 403 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 404 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 405 GENERATED_GBL_DATA_SIZE) 406 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 407 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 408 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 409 410 /* 411 * Serial Port 412 */ 413 #define CONFIG_SYS_NS16550_SERIAL 414 #define CONFIG_SYS_NS16550_REG_SIZE 1 415 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 416 #define CONFIG_SYS_BAUDRATE_TABLE \ 417 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 418 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 419 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 420 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 421 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 422 423 /* 424 * I2C 425 */ 426 #define CONFIG_SYS_I2C 427 #define CONFIG_SYS_I2C_FSL 428 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 429 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 430 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 431 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 432 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 433 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 434 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 435 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 436 #define CONFIG_SYS_FSL_I2C_SPEED 100000 437 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 438 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 439 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 440 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 441 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 442 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 443 #define I2C_MUX_CH_DEFAULT 0x8 444 445 #define I2C_MUX_CH_VOL_MONITOR 0xa 446 447 /* Voltage monitor on channel 2*/ 448 #define I2C_VOL_MONITOR_ADDR 0x40 449 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 450 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 451 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 452 453 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 454 #ifndef CONFIG_SPL_BUILD 455 #define CONFIG_VID 456 #endif 457 #define CONFIG_VOL_MONITOR_IR36021_SET 458 #define CONFIG_VOL_MONITOR_IR36021_READ 459 /* The lowest and highest voltage allowed for T208xQDS */ 460 #define VDD_MV_MIN 819 461 #define VDD_MV_MAX 1212 462 463 /* 464 * RapidIO 465 */ 466 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 467 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 468 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 469 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 470 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 471 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 472 /* 473 * for slave u-boot IMAGE instored in master memory space, 474 * PHYS must be aligned based on the SIZE 475 */ 476 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 477 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 478 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 479 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 480 /* 481 * for slave UCODE and ENV instored in master memory space, 482 * PHYS must be aligned based on the SIZE 483 */ 484 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 485 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 486 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 487 488 /* slave core release by master*/ 489 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 490 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 491 492 /* 493 * SRIO_PCIE_BOOT - SLAVE 494 */ 495 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 496 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 497 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 498 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 499 #endif 500 501 /* 502 * eSPI - Enhanced SPI 503 */ 504 #ifdef CONFIG_SPI_FLASH 505 506 #define CONFIG_SPI_FLASH_BAR 507 #define CONFIG_SF_DEFAULT_SPEED 10000000 508 #define CONFIG_SF_DEFAULT_MODE 0 509 #endif 510 511 /* 512 * General PCI 513 * Memory space is mapped 1-1, but I/O space must start from 0. 514 */ 515 #define CONFIG_PCIE1 /* PCIE controller 1 */ 516 #define CONFIG_PCIE2 /* PCIE controller 2 */ 517 #define CONFIG_PCIE3 /* PCIE controller 3 */ 518 #define CONFIG_PCIE4 /* PCIE controller 4 */ 519 #define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/ 520 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 521 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 522 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 523 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 524 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 525 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 526 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 527 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 528 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 529 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 530 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 531 532 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 533 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 534 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 535 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 536 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 537 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 538 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 539 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 540 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 541 542 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 543 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 544 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 545 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 546 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 547 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 548 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 549 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 550 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 551 552 /* controller 4, Base address 203000 */ 553 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 554 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 555 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 556 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 557 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 558 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 559 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 560 561 #ifdef CONFIG_PCI 562 #define CONFIG_PCI_INDIRECT_BRIDGE 563 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 564 #endif 565 566 /* Qman/Bman */ 567 #ifndef CONFIG_NOBQFMAN 568 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 569 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 570 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 571 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 572 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 573 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 574 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 575 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 576 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 577 CONFIG_SYS_BMAN_CENA_SIZE) 578 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 579 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 580 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 581 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 582 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 583 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 584 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 585 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 586 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 587 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 588 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 589 CONFIG_SYS_QMAN_CENA_SIZE) 590 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 591 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 592 593 #define CONFIG_SYS_DPAA_FMAN 594 #define CONFIG_SYS_DPAA_PME 595 #define CONFIG_SYS_PMAN 596 #define CONFIG_SYS_DPAA_DCE 597 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 598 #define CONFIG_SYS_INTERLAKEN 599 600 /* Default address of microcode for the Linux Fman driver */ 601 #if defined(CONFIG_SPIFLASH) 602 /* 603 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 604 * env, so we got 0x110000. 605 */ 606 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 607 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 608 #elif defined(CONFIG_SDCARD) 609 /* 610 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 611 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 612 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 613 */ 614 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 615 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 616 #elif defined(CONFIG_NAND) 617 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 618 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 619 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 620 /* 621 * Slave has no ucode locally, it can fetch this from remote. When implementing 622 * in two corenet boards, slave's ucode could be stored in master's memory 623 * space, the address can be mapped from slave TLB->slave LAW-> 624 * slave SRIO or PCIE outbound window->master inbound window-> 625 * master LAW->the ucode address in master's memory space. 626 */ 627 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 628 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 629 #else 630 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 631 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 632 #endif 633 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 634 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 635 #endif /* CONFIG_NOBQFMAN */ 636 637 #ifdef CONFIG_SYS_DPAA_FMAN 638 #define CONFIG_FMAN_ENET 639 #define CONFIG_PHYLIB_10G 640 #define CONFIG_PHY_VITESSE 641 #define CONFIG_PHY_REALTEK 642 #define CONFIG_PHY_TERANETICS 643 #define RGMII_PHY1_ADDR 0x1 644 #define RGMII_PHY2_ADDR 0x2 645 #define FM1_10GEC1_PHY_ADDR 0x3 646 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 647 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 648 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 649 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 650 #endif 651 652 #ifdef CONFIG_FMAN_ENET 653 #define CONFIG_ETHPRIME "FM1@DTSEC3" 654 #endif 655 656 /* 657 * SATA 658 */ 659 #ifdef CONFIG_FSL_SATA_V2 660 #define CONFIG_SYS_SATA_MAX_DEVICE 2 661 #define CONFIG_SATA1 662 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 663 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 664 #define CONFIG_SATA2 665 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 666 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 667 #define CONFIG_LBA48 668 #endif 669 670 /* 671 * USB 672 */ 673 #ifdef CONFIG_USB_EHCI_HCD 674 #define CONFIG_USB_EHCI_FSL 675 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 676 #define CONFIG_HAS_FSL_DR_USB 677 #endif 678 679 /* 680 * SDHC 681 */ 682 #ifdef CONFIG_MMC 683 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 684 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 685 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 686 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 687 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 688 #endif 689 690 /* 691 * Dynamic MTD Partition support with mtdparts 692 */ 693 #ifdef CONFIG_MTD_NOR_FLASH 694 #define CONFIG_FLASH_CFI_MTD 695 #endif 696 697 /* 698 * Environment 699 */ 700 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 701 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 702 703 /* 704 * Miscellaneous configurable options 705 */ 706 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 707 708 /* 709 * For booting Linux, the board info and command line data 710 * have to be in the first 64 MB of memory, since this is 711 * the maximum mapped by the Linux kernel during initialization. 712 */ 713 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 714 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 715 716 #ifdef CONFIG_CMD_KGDB 717 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 718 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 719 #endif 720 721 /* 722 * Environment Configuration 723 */ 724 #define CONFIG_ROOTPATH "/opt/nfsroot" 725 #define CONFIG_BOOTFILE "uImage" 726 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 727 728 /* default location for tftp and bootm */ 729 #define CONFIG_LOADADDR 1000000 730 #define __USB_PHY_TYPE utmi 731 732 #define CONFIG_EXTRA_ENV_SETTINGS \ 733 "hwconfig=fsl_ddr:" \ 734 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 735 "bank_intlv=auto;" \ 736 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 737 "netdev=eth0\0" \ 738 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 739 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 740 "tftpflash=tftpboot $loadaddr $uboot && " \ 741 "protect off $ubootaddr +$filesize && " \ 742 "erase $ubootaddr +$filesize && " \ 743 "cp.b $loadaddr $ubootaddr $filesize && " \ 744 "protect on $ubootaddr +$filesize && " \ 745 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 746 "consoledev=ttyS0\0" \ 747 "ramdiskaddr=2000000\0" \ 748 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 749 "fdtaddr=1e00000\0" \ 750 "fdtfile=t2080qds/t2080qds.dtb\0" \ 751 "bdev=sda3\0" 752 753 /* 754 * For emulation this causes u-boot to jump to the start of the 755 * proof point app code automatically 756 */ 757 #define CONFIG_PROOF_POINTS \ 758 "setenv bootargs root=/dev/$bdev rw " \ 759 "console=$consoledev,$baudrate $othbootargs;" \ 760 "cpu 1 release 0x29000000 - - -;" \ 761 "cpu 2 release 0x29000000 - - -;" \ 762 "cpu 3 release 0x29000000 - - -;" \ 763 "cpu 4 release 0x29000000 - - -;" \ 764 "cpu 5 release 0x29000000 - - -;" \ 765 "cpu 6 release 0x29000000 - - -;" \ 766 "cpu 7 release 0x29000000 - - -;" \ 767 "go 0x29000000" 768 769 #define CONFIG_HVBOOT \ 770 "setenv bootargs config-addr=0x60000000; " \ 771 "bootm 0x01000000 - 0x00f00000" 772 773 #define CONFIG_ALU \ 774 "setenv bootargs root=/dev/$bdev rw " \ 775 "console=$consoledev,$baudrate $othbootargs;" \ 776 "cpu 1 release 0x01000000 - - -;" \ 777 "cpu 2 release 0x01000000 - - -;" \ 778 "cpu 3 release 0x01000000 - - -;" \ 779 "cpu 4 release 0x01000000 - - -;" \ 780 "cpu 5 release 0x01000000 - - -;" \ 781 "cpu 6 release 0x01000000 - - -;" \ 782 "cpu 7 release 0x01000000 - - -;" \ 783 "go 0x01000000" 784 785 #define CONFIG_LINUX \ 786 "setenv bootargs root=/dev/ram rw " \ 787 "console=$consoledev,$baudrate $othbootargs;" \ 788 "setenv ramdiskaddr 0x02000000;" \ 789 "setenv fdtaddr 0x00c00000;" \ 790 "setenv loadaddr 0x1000000;" \ 791 "bootm $loadaddr $ramdiskaddr $fdtaddr" 792 793 #define CONFIG_HDBOOT \ 794 "setenv bootargs root=/dev/$bdev rw " \ 795 "console=$consoledev,$baudrate $othbootargs;" \ 796 "tftp $loadaddr $bootfile;" \ 797 "tftp $fdtaddr $fdtfile;" \ 798 "bootm $loadaddr - $fdtaddr" 799 800 #define CONFIG_NFSBOOTCOMMAND \ 801 "setenv bootargs root=/dev/nfs rw " \ 802 "nfsroot=$serverip:$rootpath " \ 803 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 804 "console=$consoledev,$baudrate $othbootargs;" \ 805 "tftp $loadaddr $bootfile;" \ 806 "tftp $fdtaddr $fdtfile;" \ 807 "bootm $loadaddr - $fdtaddr" 808 809 #define CONFIG_RAMBOOTCOMMAND \ 810 "setenv bootargs root=/dev/ram rw " \ 811 "console=$consoledev,$baudrate $othbootargs;" \ 812 "tftp $ramdiskaddr $ramdiskfile;" \ 813 "tftp $loadaddr $bootfile;" \ 814 "tftp $fdtaddr $fdtfile;" \ 815 "bootm $loadaddr $ramdiskaddr $fdtaddr" 816 817 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 818 819 #include <asm/fsl_secure_boot.h> 820 821 #endif /* __T208xQDS_H */ 822