1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T2080/T2081 QDS board configuration file 8 */ 9 10 #ifndef __T208xQDS_H 11 #define __T208xQDS_H 12 13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 14 #if defined(CONFIG_ARCH_T2080) 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 17 #define CONFIG_SRIO1 /* SRIO port 1 */ 18 #define CONFIG_SRIO2 /* SRIO port 2 */ 19 #elif defined(CONFIG_ARCH_T2081) 20 #endif 21 22 /* High Level Configuration Options */ 23 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 24 #define CONFIG_ENABLE_36BIT_PHYS 25 26 #ifdef CONFIG_PHYS_64BIT 27 #define CONFIG_ADDR_MAP 1 28 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 29 #endif 30 31 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 32 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 33 #define CONFIG_ENV_OVERWRITE 34 35 #ifdef CONFIG_RAMBOOT_PBL 36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 37 38 #define CONFIG_SPL_FLUSH_IMAGE 39 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 40 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 41 #define CONFIG_SPL_PAD_TO 0x40000 42 #define CONFIG_SPL_MAX_SIZE 0x28000 43 #define RESET_VECTOR_OFFSET 0x27FFC 44 #define BOOT_PAGE_OFFSET 0x27000 45 #ifdef CONFIG_SPL_BUILD 46 #define CONFIG_SPL_SKIP_RELOCATE 47 #define CONFIG_SPL_COMMON_INIT_DDR 48 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 49 #endif 50 51 #ifdef CONFIG_NAND 52 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 53 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 54 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 55 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 56 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 57 #if defined(CONFIG_ARCH_T2080) 58 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 59 #elif defined(CONFIG_ARCH_T2081) 60 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 61 #endif 62 #define CONFIG_SPL_NAND_BOOT 63 #endif 64 65 #ifdef CONFIG_SPIFLASH 66 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 67 #define CONFIG_SPL_SPI_FLASH_MINIMAL 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 72 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 73 #ifndef CONFIG_SPL_BUILD 74 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 75 #endif 76 #if defined(CONFIG_ARCH_T2080) 77 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 78 #elif defined(CONFIG_ARCH_T2081) 79 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 80 #endif 81 #define CONFIG_SPL_SPI_BOOT 82 #endif 83 84 #ifdef CONFIG_SDCARD 85 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 86 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 87 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 88 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 89 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 91 #ifndef CONFIG_SPL_BUILD 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #endif 94 #if defined(CONFIG_ARCH_T2080) 95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 96 #elif defined(CONFIG_ARCH_T2081) 97 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 98 #endif 99 #define CONFIG_SPL_MMC_BOOT 100 #endif 101 102 #endif /* CONFIG_RAMBOOT_PBL */ 103 104 #define CONFIG_SRIO_PCIE_BOOT_MASTER 105 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 106 /* Set 1M boot space */ 107 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 108 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 109 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 110 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 111 #endif 112 113 #ifndef CONFIG_RESET_VECTOR_ADDRESS 114 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 115 #endif 116 117 /* 118 * These can be toggled for performance analysis, otherwise use default. 119 */ 120 #define CONFIG_SYS_CACHE_STASHING 121 #define CONFIG_BTB /* toggle branch predition */ 122 #define CONFIG_DDR_ECC 123 #ifdef CONFIG_DDR_ECC 124 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 125 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 126 #endif 127 128 #ifdef CONFIG_MTD_NOR_FLASH 129 #define CONFIG_FLASH_CFI_DRIVER 130 #define CONFIG_SYS_FLASH_CFI 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 132 #endif 133 134 #if defined(CONFIG_SPIFLASH) 135 #define CONFIG_SYS_EXTRA_ENV_RELOC 136 #define CONFIG_ENV_SPI_BUS 0 137 #define CONFIG_ENV_SPI_CS 0 138 #define CONFIG_ENV_SPI_MAX_HZ 10000000 139 #define CONFIG_ENV_SPI_MODE 0 140 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 141 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 142 #define CONFIG_ENV_SECT_SIZE 0x10000 143 #elif defined(CONFIG_SDCARD) 144 #define CONFIG_SYS_EXTRA_ENV_RELOC 145 #define CONFIG_SYS_MMC_ENV_DEV 0 146 #define CONFIG_ENV_SIZE 0x2000 147 #define CONFIG_ENV_OFFSET (512 * 0x800) 148 #elif defined(CONFIG_NAND) 149 #define CONFIG_SYS_EXTRA_ENV_RELOC 150 #define CONFIG_ENV_SIZE 0x2000 151 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 152 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 153 #define CONFIG_ENV_ADDR 0xffe20000 154 #define CONFIG_ENV_SIZE 0x2000 155 #elif defined(CONFIG_ENV_IS_NOWHERE) 156 #define CONFIG_ENV_SIZE 0x2000 157 #else 158 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 159 #define CONFIG_ENV_SIZE 0x2000 160 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 161 #endif 162 163 #ifndef __ASSEMBLY__ 164 unsigned long get_board_sys_clk(void); 165 unsigned long get_board_ddr_clk(void); 166 #endif 167 168 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 169 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 170 171 /* 172 * Config the L3 Cache as L3 SRAM 173 */ 174 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 175 #define CONFIG_SYS_L3_SIZE (512 << 10) 176 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 177 #ifdef CONFIG_RAMBOOT_PBL 178 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 179 #endif 180 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 181 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 182 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 183 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 184 185 #define CONFIG_SYS_DCSRBAR 0xf0000000 186 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 187 188 /* EEPROM */ 189 #define CONFIG_ID_EEPROM 190 #define CONFIG_SYS_I2C_EEPROM_NXID 191 #define CONFIG_SYS_EEPROM_BUS_NUM 0 192 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 193 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 194 195 /* 196 * DDR Setup 197 */ 198 #define CONFIG_VERY_BIG_RAM 199 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 200 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 201 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 202 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 203 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 204 #define CONFIG_DDR_SPD 205 #define CONFIG_FSL_DDR_INTERACTIVE 206 #define CONFIG_SYS_SPD_BUS_NUM 0 207 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 208 #define SPD_EEPROM_ADDRESS1 0x51 209 #define SPD_EEPROM_ADDRESS2 0x52 210 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 211 #define CTRL_INTLV_PREFERED cacheline 212 213 /* 214 * IFC Definitions 215 */ 216 #define CONFIG_SYS_FLASH_BASE 0xe0000000 217 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 218 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 219 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 220 + 0x8000000) | \ 221 CSPR_PORT_SIZE_16 | \ 222 CSPR_MSEL_NOR | \ 223 CSPR_V) 224 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 225 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 226 CSPR_PORT_SIZE_16 | \ 227 CSPR_MSEL_NOR | \ 228 CSPR_V) 229 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 230 /* NOR Flash Timing Params */ 231 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 232 233 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 234 FTIM0_NOR_TEADC(0x5) | \ 235 FTIM0_NOR_TEAHC(0x5)) 236 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 237 FTIM1_NOR_TRAD_NOR(0x1A) |\ 238 FTIM1_NOR_TSEQRAD_NOR(0x13)) 239 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 240 FTIM2_NOR_TCH(0x4) | \ 241 FTIM2_NOR_TWPH(0x0E) | \ 242 FTIM2_NOR_TWP(0x1c)) 243 #define CONFIG_SYS_NOR_FTIM3 0x0 244 245 #define CONFIG_SYS_FLASH_QUIET_TEST 246 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 247 248 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 249 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 250 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 251 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 252 253 #define CONFIG_SYS_FLASH_EMPTY_INFO 254 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 255 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 256 257 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 258 #define QIXIS_BASE 0xffdf0000 259 #define QIXIS_LBMAP_SWITCH 6 260 #define QIXIS_LBMAP_MASK 0x0f 261 #define QIXIS_LBMAP_SHIFT 0 262 #define QIXIS_LBMAP_DFLTBANK 0x00 263 #define QIXIS_LBMAP_ALTBANK 0x04 264 #define QIXIS_LBMAP_NAND 0x09 265 #define QIXIS_LBMAP_SD 0x00 266 #define QIXIS_RCW_SRC_NAND 0x104 267 #define QIXIS_RCW_SRC_SD 0x040 268 #define QIXIS_RST_CTL_RESET 0x83 269 #define QIXIS_RST_FORCE_MEM 0x1 270 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 271 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 272 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 273 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 274 275 #define CONFIG_SYS_CSPR3_EXT (0xf) 276 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 277 | CSPR_PORT_SIZE_8 \ 278 | CSPR_MSEL_GPCM \ 279 | CSPR_V) 280 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 281 #define CONFIG_SYS_CSOR3 0x0 282 /* QIXIS Timing parameters for IFC CS3 */ 283 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 284 FTIM0_GPCM_TEADC(0x0e) | \ 285 FTIM0_GPCM_TEAHC(0x0e)) 286 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 287 FTIM1_GPCM_TRAD(0x3f)) 288 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 289 FTIM2_GPCM_TCH(0x8) | \ 290 FTIM2_GPCM_TWP(0x1f)) 291 #define CONFIG_SYS_CS3_FTIM3 0x0 292 293 /* NAND Flash on IFC */ 294 #define CONFIG_NAND_FSL_IFC 295 #define CONFIG_SYS_NAND_BASE 0xff800000 296 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 297 298 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 299 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 300 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 301 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 302 | CSPR_V) 303 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 304 305 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 306 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 307 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 308 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 309 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 310 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 311 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 312 313 #define CONFIG_SYS_NAND_ONFI_DETECTION 314 315 /* ONFI NAND Flash mode0 Timing Params */ 316 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 317 FTIM0_NAND_TWP(0x18) | \ 318 FTIM0_NAND_TWCHT(0x07) | \ 319 FTIM0_NAND_TWH(0x0a)) 320 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 321 FTIM1_NAND_TWBE(0x39) | \ 322 FTIM1_NAND_TRR(0x0e) | \ 323 FTIM1_NAND_TRP(0x18)) 324 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 325 FTIM2_NAND_TREH(0x0a) | \ 326 FTIM2_NAND_TWHRE(0x1e)) 327 #define CONFIG_SYS_NAND_FTIM3 0x0 328 329 #define CONFIG_SYS_NAND_DDR_LAW 11 330 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 331 #define CONFIG_SYS_MAX_NAND_DEVICE 1 332 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 333 334 #if defined(CONFIG_NAND) 335 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 336 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 337 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 338 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 339 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 340 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 341 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 342 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 343 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 344 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 345 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 352 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 353 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 354 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 355 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 356 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 357 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 358 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 359 #else 360 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 361 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 362 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 363 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 364 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 365 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 366 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 367 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 368 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 369 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 370 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 371 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 372 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 373 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 374 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 375 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 376 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 377 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 378 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 379 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 380 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 381 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 382 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 383 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 384 #endif 385 386 #if defined(CONFIG_RAMBOOT_PBL) 387 #define CONFIG_SYS_RAMBOOT 388 #endif 389 390 #ifdef CONFIG_SPL_BUILD 391 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 392 #else 393 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 394 #endif 395 396 #define CONFIG_MISC_INIT_R 397 #define CONFIG_HWCONFIG 398 399 /* define to use L1 as initial stack */ 400 #define CONFIG_L1_INIT_RAM 401 #define CONFIG_SYS_INIT_RAM_LOCK 402 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 403 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 404 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 405 /* The assembler doesn't like typecast */ 406 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 407 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 408 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 409 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 410 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 411 GENERATED_GBL_DATA_SIZE) 412 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 413 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 414 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 415 416 /* 417 * Serial Port 418 */ 419 #define CONFIG_SYS_NS16550_SERIAL 420 #define CONFIG_SYS_NS16550_REG_SIZE 1 421 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 422 #define CONFIG_SYS_BAUDRATE_TABLE \ 423 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 424 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 425 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 426 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 427 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 428 429 /* 430 * I2C 431 */ 432 #define CONFIG_SYS_I2C 433 #define CONFIG_SYS_I2C_FSL 434 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 435 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 437 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 438 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 439 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 440 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 441 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 442 #define CONFIG_SYS_FSL_I2C_SPEED 100000 443 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 444 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 445 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 446 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 447 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 448 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 449 #define I2C_MUX_CH_DEFAULT 0x8 450 451 #define I2C_MUX_CH_VOL_MONITOR 0xa 452 453 /* Voltage monitor on channel 2*/ 454 #define I2C_VOL_MONITOR_ADDR 0x40 455 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 456 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 457 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 458 459 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 460 #ifndef CONFIG_SPL_BUILD 461 #define CONFIG_VID 462 #endif 463 #define CONFIG_VOL_MONITOR_IR36021_SET 464 #define CONFIG_VOL_MONITOR_IR36021_READ 465 /* The lowest and highest voltage allowed for T208xQDS */ 466 #define VDD_MV_MIN 819 467 #define VDD_MV_MAX 1212 468 469 /* 470 * RapidIO 471 */ 472 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 473 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 474 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 475 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 476 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 477 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 478 /* 479 * for slave u-boot IMAGE instored in master memory space, 480 * PHYS must be aligned based on the SIZE 481 */ 482 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 483 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 484 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 485 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 486 /* 487 * for slave UCODE and ENV instored in master memory space, 488 * PHYS must be aligned based on the SIZE 489 */ 490 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 491 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 492 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 493 494 /* slave core release by master*/ 495 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 496 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 497 498 /* 499 * SRIO_PCIE_BOOT - SLAVE 500 */ 501 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 502 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 503 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 504 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 505 #endif 506 507 /* 508 * eSPI - Enhanced SPI 509 */ 510 #ifdef CONFIG_SPI_FLASH 511 512 #define CONFIG_SPI_FLASH_BAR 513 #define CONFIG_SF_DEFAULT_SPEED 10000000 514 #define CONFIG_SF_DEFAULT_MODE 0 515 #endif 516 517 /* 518 * General PCI 519 * Memory space is mapped 1-1, but I/O space must start from 0. 520 */ 521 #define CONFIG_PCIE1 /* PCIE controller 1 */ 522 #define CONFIG_PCIE2 /* PCIE controller 2 */ 523 #define CONFIG_PCIE3 /* PCIE controller 3 */ 524 #define CONFIG_PCIE4 /* PCIE controller 4 */ 525 #define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/ 526 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 527 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 528 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 529 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 530 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 531 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 532 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 533 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 534 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 535 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 536 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 537 538 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 539 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 540 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 541 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 542 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 543 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 544 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 545 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 546 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 547 548 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 549 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 550 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 551 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 552 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 553 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 554 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 555 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 556 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 557 558 /* controller 4, Base address 203000 */ 559 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 560 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 561 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 562 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 563 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 564 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 565 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 566 567 #ifdef CONFIG_PCI 568 #define CONFIG_PCI_INDIRECT_BRIDGE 569 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 570 #endif 571 572 /* Qman/Bman */ 573 #ifndef CONFIG_NOBQFMAN 574 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 575 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 576 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 577 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 578 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 579 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 580 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 581 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 582 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 583 CONFIG_SYS_BMAN_CENA_SIZE) 584 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 585 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 586 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 587 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 588 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 589 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 590 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 591 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 592 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 593 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 594 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 595 CONFIG_SYS_QMAN_CENA_SIZE) 596 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 597 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 598 599 #define CONFIG_SYS_DPAA_FMAN 600 #define CONFIG_SYS_DPAA_PME 601 #define CONFIG_SYS_PMAN 602 #define CONFIG_SYS_DPAA_DCE 603 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 604 #define CONFIG_SYS_INTERLAKEN 605 606 /* Default address of microcode for the Linux Fman driver */ 607 #if defined(CONFIG_SPIFLASH) 608 /* 609 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 610 * env, so we got 0x110000. 611 */ 612 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 613 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 614 #elif defined(CONFIG_SDCARD) 615 /* 616 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 617 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 618 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 619 */ 620 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 621 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 622 #elif defined(CONFIG_NAND) 623 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 624 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 625 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 626 /* 627 * Slave has no ucode locally, it can fetch this from remote. When implementing 628 * in two corenet boards, slave's ucode could be stored in master's memory 629 * space, the address can be mapped from slave TLB->slave LAW-> 630 * slave SRIO or PCIE outbound window->master inbound window-> 631 * master LAW->the ucode address in master's memory space. 632 */ 633 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 634 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 635 #else 636 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 637 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 638 #endif 639 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 640 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 641 #endif /* CONFIG_NOBQFMAN */ 642 643 #ifdef CONFIG_SYS_DPAA_FMAN 644 #define CONFIG_FMAN_ENET 645 #define CONFIG_PHYLIB_10G 646 #define CONFIG_PHY_VITESSE 647 #define CONFIG_PHY_REALTEK 648 #define CONFIG_PHY_TERANETICS 649 #define RGMII_PHY1_ADDR 0x1 650 #define RGMII_PHY2_ADDR 0x2 651 #define FM1_10GEC1_PHY_ADDR 0x3 652 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 653 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 654 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 655 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 656 #endif 657 658 #ifdef CONFIG_FMAN_ENET 659 #define CONFIG_MII /* MII PHY management */ 660 #define CONFIG_ETHPRIME "FM1@DTSEC3" 661 #endif 662 663 /* 664 * SATA 665 */ 666 #ifdef CONFIG_FSL_SATA_V2 667 #define CONFIG_SYS_SATA_MAX_DEVICE 2 668 #define CONFIG_SATA1 669 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 670 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 671 #define CONFIG_SATA2 672 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 673 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 674 #define CONFIG_LBA48 675 #endif 676 677 /* 678 * USB 679 */ 680 #ifdef CONFIG_USB_EHCI_HCD 681 #define CONFIG_USB_EHCI_FSL 682 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 683 #define CONFIG_HAS_FSL_DR_USB 684 #endif 685 686 /* 687 * SDHC 688 */ 689 #ifdef CONFIG_MMC 690 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 691 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 692 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 693 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 694 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 695 #endif 696 697 /* 698 * Dynamic MTD Partition support with mtdparts 699 */ 700 #ifdef CONFIG_MTD_NOR_FLASH 701 #define CONFIG_FLASH_CFI_MTD 702 #endif 703 704 /* 705 * Environment 706 */ 707 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 708 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 709 710 /* 711 * Miscellaneous configurable options 712 */ 713 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 714 715 /* 716 * For booting Linux, the board info and command line data 717 * have to be in the first 64 MB of memory, since this is 718 * the maximum mapped by the Linux kernel during initialization. 719 */ 720 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 721 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 722 723 #ifdef CONFIG_CMD_KGDB 724 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 725 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 726 #endif 727 728 /* 729 * Environment Configuration 730 */ 731 #define CONFIG_ROOTPATH "/opt/nfsroot" 732 #define CONFIG_BOOTFILE "uImage" 733 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 734 735 /* default location for tftp and bootm */ 736 #define CONFIG_LOADADDR 1000000 737 #define __USB_PHY_TYPE utmi 738 739 #define CONFIG_EXTRA_ENV_SETTINGS \ 740 "hwconfig=fsl_ddr:" \ 741 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 742 "bank_intlv=auto;" \ 743 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 744 "netdev=eth0\0" \ 745 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 746 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 747 "tftpflash=tftpboot $loadaddr $uboot && " \ 748 "protect off $ubootaddr +$filesize && " \ 749 "erase $ubootaddr +$filesize && " \ 750 "cp.b $loadaddr $ubootaddr $filesize && " \ 751 "protect on $ubootaddr +$filesize && " \ 752 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 753 "consoledev=ttyS0\0" \ 754 "ramdiskaddr=2000000\0" \ 755 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 756 "fdtaddr=1e00000\0" \ 757 "fdtfile=t2080qds/t2080qds.dtb\0" \ 758 "bdev=sda3\0" 759 760 /* 761 * For emulation this causes u-boot to jump to the start of the 762 * proof point app code automatically 763 */ 764 #define CONFIG_PROOF_POINTS \ 765 "setenv bootargs root=/dev/$bdev rw " \ 766 "console=$consoledev,$baudrate $othbootargs;" \ 767 "cpu 1 release 0x29000000 - - -;" \ 768 "cpu 2 release 0x29000000 - - -;" \ 769 "cpu 3 release 0x29000000 - - -;" \ 770 "cpu 4 release 0x29000000 - - -;" \ 771 "cpu 5 release 0x29000000 - - -;" \ 772 "cpu 6 release 0x29000000 - - -;" \ 773 "cpu 7 release 0x29000000 - - -;" \ 774 "go 0x29000000" 775 776 #define CONFIG_HVBOOT \ 777 "setenv bootargs config-addr=0x60000000; " \ 778 "bootm 0x01000000 - 0x00f00000" 779 780 #define CONFIG_ALU \ 781 "setenv bootargs root=/dev/$bdev rw " \ 782 "console=$consoledev,$baudrate $othbootargs;" \ 783 "cpu 1 release 0x01000000 - - -;" \ 784 "cpu 2 release 0x01000000 - - -;" \ 785 "cpu 3 release 0x01000000 - - -;" \ 786 "cpu 4 release 0x01000000 - - -;" \ 787 "cpu 5 release 0x01000000 - - -;" \ 788 "cpu 6 release 0x01000000 - - -;" \ 789 "cpu 7 release 0x01000000 - - -;" \ 790 "go 0x01000000" 791 792 #define CONFIG_LINUX \ 793 "setenv bootargs root=/dev/ram rw " \ 794 "console=$consoledev,$baudrate $othbootargs;" \ 795 "setenv ramdiskaddr 0x02000000;" \ 796 "setenv fdtaddr 0x00c00000;" \ 797 "setenv loadaddr 0x1000000;" \ 798 "bootm $loadaddr $ramdiskaddr $fdtaddr" 799 800 #define CONFIG_HDBOOT \ 801 "setenv bootargs root=/dev/$bdev rw " \ 802 "console=$consoledev,$baudrate $othbootargs;" \ 803 "tftp $loadaddr $bootfile;" \ 804 "tftp $fdtaddr $fdtfile;" \ 805 "bootm $loadaddr - $fdtaddr" 806 807 #define CONFIG_NFSBOOTCOMMAND \ 808 "setenv bootargs root=/dev/nfs rw " \ 809 "nfsroot=$serverip:$rootpath " \ 810 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 811 "console=$consoledev,$baudrate $othbootargs;" \ 812 "tftp $loadaddr $bootfile;" \ 813 "tftp $fdtaddr $fdtfile;" \ 814 "bootm $loadaddr - $fdtaddr" 815 816 #define CONFIG_RAMBOOTCOMMAND \ 817 "setenv bootargs root=/dev/ram rw " \ 818 "console=$consoledev,$baudrate $othbootargs;" \ 819 "tftp $ramdiskaddr $ramdiskfile;" \ 820 "tftp $loadaddr $bootfile;" \ 821 "tftp $fdtaddr $fdtfile;" \ 822 "bootm $loadaddr $ramdiskaddr $fdtaddr" 823 824 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 825 826 #include <asm/fsl_secure_boot.h> 827 828 #endif /* __T208xQDS_H */ 829