1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T2080/T2081 QDS board configuration file 8 */ 9 10 #ifndef __T208xQDS_H 11 #define __T208xQDS_H 12 13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 14 #if defined(CONFIG_ARCH_T2080) 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 17 #define CONFIG_SRIO1 /* SRIO port 1 */ 18 #define CONFIG_SRIO2 /* SRIO port 2 */ 19 #elif defined(CONFIG_ARCH_T2081) 20 #endif 21 22 /* High Level Configuration Options */ 23 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 24 #define CONFIG_ENABLE_36BIT_PHYS 25 26 #ifdef CONFIG_PHYS_64BIT 27 #define CONFIG_ADDR_MAP 1 28 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 29 #endif 30 31 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 32 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 33 #define CONFIG_ENV_OVERWRITE 34 35 #ifdef CONFIG_RAMBOOT_PBL 36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 37 38 #define CONFIG_SPL_FLUSH_IMAGE 39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 40 #define CONFIG_SPL_PAD_TO 0x40000 41 #define CONFIG_SPL_MAX_SIZE 0x28000 42 #define RESET_VECTOR_OFFSET 0x27FFC 43 #define BOOT_PAGE_OFFSET 0x27000 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #endif 49 50 #ifdef CONFIG_NAND 51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 54 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 56 #if defined(CONFIG_ARCH_T2080) 57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 58 #elif defined(CONFIG_ARCH_T2081) 59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 60 #endif 61 #define CONFIG_SPL_NAND_BOOT 62 #endif 63 64 #ifdef CONFIG_SPIFLASH 65 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 66 #define CONFIG_SPL_SPI_FLASH_MINIMAL 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 71 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 72 #ifndef CONFIG_SPL_BUILD 73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 74 #endif 75 #if defined(CONFIG_ARCH_T2080) 76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 77 #elif defined(CONFIG_ARCH_T2081) 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 79 #endif 80 #define CONFIG_SPL_SPI_BOOT 81 #endif 82 83 #ifdef CONFIG_SDCARD 84 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 85 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 86 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 87 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 88 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 90 #ifndef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #endif 93 #if defined(CONFIG_ARCH_T2080) 94 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 95 #elif defined(CONFIG_ARCH_T2081) 96 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 97 #endif 98 #define CONFIG_SPL_MMC_BOOT 99 #endif 100 101 #endif /* CONFIG_RAMBOOT_PBL */ 102 103 #define CONFIG_SRIO_PCIE_BOOT_MASTER 104 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 105 /* Set 1M boot space */ 106 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 107 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 108 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 109 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 110 #endif 111 112 #ifndef CONFIG_RESET_VECTOR_ADDRESS 113 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 114 #endif 115 116 /* 117 * These can be toggled for performance analysis, otherwise use default. 118 */ 119 #define CONFIG_SYS_CACHE_STASHING 120 #define CONFIG_BTB /* toggle branch predition */ 121 #define CONFIG_DDR_ECC 122 #ifdef CONFIG_DDR_ECC 123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 124 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 125 #endif 126 127 #ifdef CONFIG_MTD_NOR_FLASH 128 #define CONFIG_FLASH_CFI_DRIVER 129 #define CONFIG_SYS_FLASH_CFI 130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 131 #endif 132 133 #if defined(CONFIG_SPIFLASH) 134 #define CONFIG_SYS_EXTRA_ENV_RELOC 135 #define CONFIG_ENV_SPI_BUS 0 136 #define CONFIG_ENV_SPI_CS 0 137 #define CONFIG_ENV_SPI_MAX_HZ 10000000 138 #define CONFIG_ENV_SPI_MODE 0 139 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 140 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 141 #define CONFIG_ENV_SECT_SIZE 0x10000 142 #elif defined(CONFIG_SDCARD) 143 #define CONFIG_SYS_EXTRA_ENV_RELOC 144 #define CONFIG_SYS_MMC_ENV_DEV 0 145 #define CONFIG_ENV_SIZE 0x2000 146 #define CONFIG_ENV_OFFSET (512 * 0x800) 147 #elif defined(CONFIG_NAND) 148 #define CONFIG_SYS_EXTRA_ENV_RELOC 149 #define CONFIG_ENV_SIZE 0x2000 150 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 151 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 152 #define CONFIG_ENV_ADDR 0xffe20000 153 #define CONFIG_ENV_SIZE 0x2000 154 #elif defined(CONFIG_ENV_IS_NOWHERE) 155 #define CONFIG_ENV_SIZE 0x2000 156 #else 157 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 158 #define CONFIG_ENV_SIZE 0x2000 159 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 160 #endif 161 162 #ifndef __ASSEMBLY__ 163 unsigned long get_board_sys_clk(void); 164 unsigned long get_board_ddr_clk(void); 165 #endif 166 167 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 168 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 169 170 /* 171 * Config the L3 Cache as L3 SRAM 172 */ 173 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 174 #define CONFIG_SYS_L3_SIZE (512 << 10) 175 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 176 #ifdef CONFIG_RAMBOOT_PBL 177 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 178 #endif 179 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 180 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 181 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 182 183 #define CONFIG_SYS_DCSRBAR 0xf0000000 184 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 185 186 /* EEPROM */ 187 #define CONFIG_ID_EEPROM 188 #define CONFIG_SYS_I2C_EEPROM_NXID 189 #define CONFIG_SYS_EEPROM_BUS_NUM 0 190 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 191 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 192 193 /* 194 * DDR Setup 195 */ 196 #define CONFIG_VERY_BIG_RAM 197 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 198 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 199 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 200 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 201 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 202 #define CONFIG_DDR_SPD 203 #define CONFIG_FSL_DDR_INTERACTIVE 204 #define CONFIG_SYS_SPD_BUS_NUM 0 205 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 206 #define SPD_EEPROM_ADDRESS1 0x51 207 #define SPD_EEPROM_ADDRESS2 0x52 208 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 209 #define CTRL_INTLV_PREFERED cacheline 210 211 /* 212 * IFC Definitions 213 */ 214 #define CONFIG_SYS_FLASH_BASE 0xe0000000 215 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 216 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 217 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 218 + 0x8000000) | \ 219 CSPR_PORT_SIZE_16 | \ 220 CSPR_MSEL_NOR | \ 221 CSPR_V) 222 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 223 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 224 CSPR_PORT_SIZE_16 | \ 225 CSPR_MSEL_NOR | \ 226 CSPR_V) 227 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 228 /* NOR Flash Timing Params */ 229 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 230 231 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 232 FTIM0_NOR_TEADC(0x5) | \ 233 FTIM0_NOR_TEAHC(0x5)) 234 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 235 FTIM1_NOR_TRAD_NOR(0x1A) |\ 236 FTIM1_NOR_TSEQRAD_NOR(0x13)) 237 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 238 FTIM2_NOR_TCH(0x4) | \ 239 FTIM2_NOR_TWPH(0x0E) | \ 240 FTIM2_NOR_TWP(0x1c)) 241 #define CONFIG_SYS_NOR_FTIM3 0x0 242 243 #define CONFIG_SYS_FLASH_QUIET_TEST 244 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 245 246 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 247 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 248 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 249 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 250 251 #define CONFIG_SYS_FLASH_EMPTY_INFO 252 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 253 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 254 255 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 256 #define QIXIS_BASE 0xffdf0000 257 #define QIXIS_LBMAP_SWITCH 6 258 #define QIXIS_LBMAP_MASK 0x0f 259 #define QIXIS_LBMAP_SHIFT 0 260 #define QIXIS_LBMAP_DFLTBANK 0x00 261 #define QIXIS_LBMAP_ALTBANK 0x04 262 #define QIXIS_LBMAP_NAND 0x09 263 #define QIXIS_LBMAP_SD 0x00 264 #define QIXIS_RCW_SRC_NAND 0x104 265 #define QIXIS_RCW_SRC_SD 0x040 266 #define QIXIS_RST_CTL_RESET 0x83 267 #define QIXIS_RST_FORCE_MEM 0x1 268 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 269 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 270 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 271 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 272 273 #define CONFIG_SYS_CSPR3_EXT (0xf) 274 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 275 | CSPR_PORT_SIZE_8 \ 276 | CSPR_MSEL_GPCM \ 277 | CSPR_V) 278 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 279 #define CONFIG_SYS_CSOR3 0x0 280 /* QIXIS Timing parameters for IFC CS3 */ 281 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 282 FTIM0_GPCM_TEADC(0x0e) | \ 283 FTIM0_GPCM_TEAHC(0x0e)) 284 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 285 FTIM1_GPCM_TRAD(0x3f)) 286 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 287 FTIM2_GPCM_TCH(0x8) | \ 288 FTIM2_GPCM_TWP(0x1f)) 289 #define CONFIG_SYS_CS3_FTIM3 0x0 290 291 /* NAND Flash on IFC */ 292 #define CONFIG_NAND_FSL_IFC 293 #define CONFIG_SYS_NAND_BASE 0xff800000 294 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 295 296 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 297 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 298 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 299 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 300 | CSPR_V) 301 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 302 303 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 304 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 305 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 306 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 307 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 308 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 309 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 310 311 #define CONFIG_SYS_NAND_ONFI_DETECTION 312 313 /* ONFI NAND Flash mode0 Timing Params */ 314 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 315 FTIM0_NAND_TWP(0x18) | \ 316 FTIM0_NAND_TWCHT(0x07) | \ 317 FTIM0_NAND_TWH(0x0a)) 318 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 319 FTIM1_NAND_TWBE(0x39) | \ 320 FTIM1_NAND_TRR(0x0e) | \ 321 FTIM1_NAND_TRP(0x18)) 322 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 323 FTIM2_NAND_TREH(0x0a) | \ 324 FTIM2_NAND_TWHRE(0x1e)) 325 #define CONFIG_SYS_NAND_FTIM3 0x0 326 327 #define CONFIG_SYS_NAND_DDR_LAW 11 328 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 329 #define CONFIG_SYS_MAX_NAND_DEVICE 1 330 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 331 332 #if defined(CONFIG_NAND) 333 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 334 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 335 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 336 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 337 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 338 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 339 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 340 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 341 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 342 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 343 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 344 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 345 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 346 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 347 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 348 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 349 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 350 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 351 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 352 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 353 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 354 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 355 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 356 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 357 #else 358 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 359 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 360 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 361 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 362 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 363 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 364 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 365 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 366 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 367 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 368 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 369 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 370 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 371 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 372 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 373 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 374 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 375 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 376 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 377 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 378 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 379 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 380 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 381 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 382 #endif 383 384 #if defined(CONFIG_RAMBOOT_PBL) 385 #define CONFIG_SYS_RAMBOOT 386 #endif 387 388 #ifdef CONFIG_SPL_BUILD 389 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 390 #else 391 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 392 #endif 393 394 #define CONFIG_MISC_INIT_R 395 #define CONFIG_HWCONFIG 396 397 /* define to use L1 as initial stack */ 398 #define CONFIG_L1_INIT_RAM 399 #define CONFIG_SYS_INIT_RAM_LOCK 400 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 401 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 403 /* The assembler doesn't like typecast */ 404 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 405 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 406 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 407 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 408 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 409 GENERATED_GBL_DATA_SIZE) 410 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 411 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 412 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 413 414 /* 415 * Serial Port 416 */ 417 #define CONFIG_SYS_NS16550_SERIAL 418 #define CONFIG_SYS_NS16550_REG_SIZE 1 419 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 420 #define CONFIG_SYS_BAUDRATE_TABLE \ 421 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 422 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 423 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 424 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 425 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 426 427 /* 428 * I2C 429 */ 430 #define CONFIG_SYS_I2C 431 #define CONFIG_SYS_I2C_FSL 432 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 433 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 434 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 435 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 437 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 438 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 439 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 440 #define CONFIG_SYS_FSL_I2C_SPEED 100000 441 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 442 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 443 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 444 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 445 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 446 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 447 #define I2C_MUX_CH_DEFAULT 0x8 448 449 #define I2C_MUX_CH_VOL_MONITOR 0xa 450 451 /* Voltage monitor on channel 2*/ 452 #define I2C_VOL_MONITOR_ADDR 0x40 453 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 454 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 455 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 456 457 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 458 #ifndef CONFIG_SPL_BUILD 459 #define CONFIG_VID 460 #endif 461 #define CONFIG_VOL_MONITOR_IR36021_SET 462 #define CONFIG_VOL_MONITOR_IR36021_READ 463 /* The lowest and highest voltage allowed for T208xQDS */ 464 #define VDD_MV_MIN 819 465 #define VDD_MV_MAX 1212 466 467 /* 468 * RapidIO 469 */ 470 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 471 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 472 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 473 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 474 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 475 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 476 /* 477 * for slave u-boot IMAGE instored in master memory space, 478 * PHYS must be aligned based on the SIZE 479 */ 480 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 481 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 482 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 483 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 484 /* 485 * for slave UCODE and ENV instored in master memory space, 486 * PHYS must be aligned based on the SIZE 487 */ 488 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 489 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 490 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 491 492 /* slave core release by master*/ 493 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 494 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 495 496 /* 497 * SRIO_PCIE_BOOT - SLAVE 498 */ 499 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 500 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 501 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 502 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 503 #endif 504 505 /* 506 * eSPI - Enhanced SPI 507 */ 508 #ifdef CONFIG_SPI_FLASH 509 510 #define CONFIG_SPI_FLASH_BAR 511 #define CONFIG_SF_DEFAULT_SPEED 10000000 512 #define CONFIG_SF_DEFAULT_MODE 0 513 #endif 514 515 /* 516 * General PCI 517 * Memory space is mapped 1-1, but I/O space must start from 0. 518 */ 519 #define CONFIG_PCIE1 /* PCIE controller 1 */ 520 #define CONFIG_PCIE2 /* PCIE controller 2 */ 521 #define CONFIG_PCIE3 /* PCIE controller 3 */ 522 #define CONFIG_PCIE4 /* PCIE controller 4 */ 523 #define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/ 524 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 525 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 526 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 527 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 528 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 529 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 530 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 531 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 532 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 533 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 534 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 535 536 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 537 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 538 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 539 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 540 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 541 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 542 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 543 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 544 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 545 546 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 547 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 548 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 549 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 550 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 551 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 552 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 553 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 554 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 555 556 /* controller 4, Base address 203000 */ 557 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 558 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 559 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 560 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 561 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 562 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 563 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 564 565 #ifdef CONFIG_PCI 566 #define CONFIG_PCI_INDIRECT_BRIDGE 567 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 568 #endif 569 570 /* Qman/Bman */ 571 #ifndef CONFIG_NOBQFMAN 572 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 573 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 574 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 575 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 576 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 577 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 578 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 579 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 580 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 581 CONFIG_SYS_BMAN_CENA_SIZE) 582 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 583 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 584 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 585 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 586 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 587 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 588 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 589 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 590 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 591 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 592 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 593 CONFIG_SYS_QMAN_CENA_SIZE) 594 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 595 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 596 597 #define CONFIG_SYS_DPAA_FMAN 598 #define CONFIG_SYS_DPAA_PME 599 #define CONFIG_SYS_PMAN 600 #define CONFIG_SYS_DPAA_DCE 601 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 602 #define CONFIG_SYS_INTERLAKEN 603 604 /* Default address of microcode for the Linux Fman driver */ 605 #if defined(CONFIG_SPIFLASH) 606 /* 607 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 608 * env, so we got 0x110000. 609 */ 610 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 611 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 612 #elif defined(CONFIG_SDCARD) 613 /* 614 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 615 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 616 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 617 */ 618 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 619 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 620 #elif defined(CONFIG_NAND) 621 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 622 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 623 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 624 /* 625 * Slave has no ucode locally, it can fetch this from remote. When implementing 626 * in two corenet boards, slave's ucode could be stored in master's memory 627 * space, the address can be mapped from slave TLB->slave LAW-> 628 * slave SRIO or PCIE outbound window->master inbound window-> 629 * master LAW->the ucode address in master's memory space. 630 */ 631 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 632 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 633 #else 634 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 635 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 636 #endif 637 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 638 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 639 #endif /* CONFIG_NOBQFMAN */ 640 641 #ifdef CONFIG_SYS_DPAA_FMAN 642 #define CONFIG_FMAN_ENET 643 #define CONFIG_PHYLIB_10G 644 #define CONFIG_PHY_VITESSE 645 #define CONFIG_PHY_REALTEK 646 #define CONFIG_PHY_TERANETICS 647 #define RGMII_PHY1_ADDR 0x1 648 #define RGMII_PHY2_ADDR 0x2 649 #define FM1_10GEC1_PHY_ADDR 0x3 650 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 651 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 652 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 653 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 654 #endif 655 656 #ifdef CONFIG_FMAN_ENET 657 #define CONFIG_MII /* MII PHY management */ 658 #define CONFIG_ETHPRIME "FM1@DTSEC3" 659 #endif 660 661 /* 662 * SATA 663 */ 664 #ifdef CONFIG_FSL_SATA_V2 665 #define CONFIG_SYS_SATA_MAX_DEVICE 2 666 #define CONFIG_SATA1 667 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 668 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 669 #define CONFIG_SATA2 670 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 671 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 672 #define CONFIG_LBA48 673 #endif 674 675 /* 676 * USB 677 */ 678 #ifdef CONFIG_USB_EHCI_HCD 679 #define CONFIG_USB_EHCI_FSL 680 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 681 #define CONFIG_HAS_FSL_DR_USB 682 #endif 683 684 /* 685 * SDHC 686 */ 687 #ifdef CONFIG_MMC 688 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 689 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 690 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 691 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 692 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 693 #endif 694 695 /* 696 * Dynamic MTD Partition support with mtdparts 697 */ 698 #ifdef CONFIG_MTD_NOR_FLASH 699 #define CONFIG_FLASH_CFI_MTD 700 #endif 701 702 /* 703 * Environment 704 */ 705 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 706 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 707 708 /* 709 * Miscellaneous configurable options 710 */ 711 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 712 713 /* 714 * For booting Linux, the board info and command line data 715 * have to be in the first 64 MB of memory, since this is 716 * the maximum mapped by the Linux kernel during initialization. 717 */ 718 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 719 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 720 721 #ifdef CONFIG_CMD_KGDB 722 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 723 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 724 #endif 725 726 /* 727 * Environment Configuration 728 */ 729 #define CONFIG_ROOTPATH "/opt/nfsroot" 730 #define CONFIG_BOOTFILE "uImage" 731 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 732 733 /* default location for tftp and bootm */ 734 #define CONFIG_LOADADDR 1000000 735 #define __USB_PHY_TYPE utmi 736 737 #define CONFIG_EXTRA_ENV_SETTINGS \ 738 "hwconfig=fsl_ddr:" \ 739 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 740 "bank_intlv=auto;" \ 741 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 742 "netdev=eth0\0" \ 743 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 744 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 745 "tftpflash=tftpboot $loadaddr $uboot && " \ 746 "protect off $ubootaddr +$filesize && " \ 747 "erase $ubootaddr +$filesize && " \ 748 "cp.b $loadaddr $ubootaddr $filesize && " \ 749 "protect on $ubootaddr +$filesize && " \ 750 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 751 "consoledev=ttyS0\0" \ 752 "ramdiskaddr=2000000\0" \ 753 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 754 "fdtaddr=1e00000\0" \ 755 "fdtfile=t2080qds/t2080qds.dtb\0" \ 756 "bdev=sda3\0" 757 758 /* 759 * For emulation this causes u-boot to jump to the start of the 760 * proof point app code automatically 761 */ 762 #define CONFIG_PROOF_POINTS \ 763 "setenv bootargs root=/dev/$bdev rw " \ 764 "console=$consoledev,$baudrate $othbootargs;" \ 765 "cpu 1 release 0x29000000 - - -;" \ 766 "cpu 2 release 0x29000000 - - -;" \ 767 "cpu 3 release 0x29000000 - - -;" \ 768 "cpu 4 release 0x29000000 - - -;" \ 769 "cpu 5 release 0x29000000 - - -;" \ 770 "cpu 6 release 0x29000000 - - -;" \ 771 "cpu 7 release 0x29000000 - - -;" \ 772 "go 0x29000000" 773 774 #define CONFIG_HVBOOT \ 775 "setenv bootargs config-addr=0x60000000; " \ 776 "bootm 0x01000000 - 0x00f00000" 777 778 #define CONFIG_ALU \ 779 "setenv bootargs root=/dev/$bdev rw " \ 780 "console=$consoledev,$baudrate $othbootargs;" \ 781 "cpu 1 release 0x01000000 - - -;" \ 782 "cpu 2 release 0x01000000 - - -;" \ 783 "cpu 3 release 0x01000000 - - -;" \ 784 "cpu 4 release 0x01000000 - - -;" \ 785 "cpu 5 release 0x01000000 - - -;" \ 786 "cpu 6 release 0x01000000 - - -;" \ 787 "cpu 7 release 0x01000000 - - -;" \ 788 "go 0x01000000" 789 790 #define CONFIG_LINUX \ 791 "setenv bootargs root=/dev/ram rw " \ 792 "console=$consoledev,$baudrate $othbootargs;" \ 793 "setenv ramdiskaddr 0x02000000;" \ 794 "setenv fdtaddr 0x00c00000;" \ 795 "setenv loadaddr 0x1000000;" \ 796 "bootm $loadaddr $ramdiskaddr $fdtaddr" 797 798 #define CONFIG_HDBOOT \ 799 "setenv bootargs root=/dev/$bdev rw " \ 800 "console=$consoledev,$baudrate $othbootargs;" \ 801 "tftp $loadaddr $bootfile;" \ 802 "tftp $fdtaddr $fdtfile;" \ 803 "bootm $loadaddr - $fdtaddr" 804 805 #define CONFIG_NFSBOOTCOMMAND \ 806 "setenv bootargs root=/dev/nfs rw " \ 807 "nfsroot=$serverip:$rootpath " \ 808 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 809 "console=$consoledev,$baudrate $othbootargs;" \ 810 "tftp $loadaddr $bootfile;" \ 811 "tftp $fdtaddr $fdtfile;" \ 812 "bootm $loadaddr - $fdtaddr" 813 814 #define CONFIG_RAMBOOTCOMMAND \ 815 "setenv bootargs root=/dev/ram rw " \ 816 "console=$consoledev,$baudrate $othbootargs;" \ 817 "tftp $ramdiskaddr $ramdiskfile;" \ 818 "tftp $loadaddr $bootfile;" \ 819 "tftp $fdtaddr $fdtfile;" \ 820 "bootm $loadaddr $ramdiskaddr $fdtaddr" 821 822 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 823 824 #include <asm/fsl_secure_boot.h> 825 826 #endif /* __T208xQDS_H */ 827