1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 #define CONFIG_MMC 17 #define CONFIG_USB_EHCI 18 #if defined(CONFIG_PPC_T2080) 19 #define CONFIG_T2080QDS 20 #define CONFIG_FSL_SATA_V2 21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 #define CONFIG_SRIO2 /* SRIO port 2 */ 24 #elif defined(CONFIG_PPC_T2081) 25 #define CONFIG_T2081QDS 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_BOOKE 30 #define CONFIG_E500 /* BOOKE e500 family */ 31 #define CONFIG_E500MC /* BOOKE e500mc family */ 32 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 33 #define CONFIG_MP /* support multiple processors */ 34 #define CONFIG_ENABLE_36BIT_PHYS 35 36 #ifdef CONFIG_PHYS_64BIT 37 #define CONFIG_ADDR_MAP 1 38 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 39 #endif 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 43 #define CONFIG_FSL_IFC /* Enable IFC Support */ 44 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 #define CONFIG_ENV_OVERWRITE 47 48 #ifdef CONFIG_RAMBOOT_PBL 49 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 50 #if defined(CONFIG_PPC_T2080) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg 52 #elif defined(CONFIG_PPC_T2081) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg 54 #endif 55 56 #define CONFIG_SPL_FLUSH_IMAGE 57 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 58 #define CONFIG_FSL_LAW /* Use common FSL init code */ 59 #define CONFIG_SYS_TEXT_BASE 0x00201000 60 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 61 #define CONFIG_SPL_PAD_TO 0x40000 62 #define CONFIG_SPL_MAX_SIZE 0x28000 63 #define RESET_VECTOR_OFFSET 0x27FFC 64 #define BOOT_PAGE_OFFSET 0x27000 65 #ifdef CONFIG_SPL_BUILD 66 #define CONFIG_SPL_SKIP_RELOCATE 67 #define CONFIG_SPL_COMMON_INIT_DDR 68 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 69 #define CONFIG_SYS_NO_FLASH 70 #endif 71 72 #ifdef CONFIG_NAND 73 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 74 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 75 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 77 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 78 #define CONFIG_SPL_NAND_BOOT 79 #endif 80 81 #ifdef CONFIG_SPIFLASH 82 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 83 #define CONFIG_SPL_SPI_FLASH_MINIMAL 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 87 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 88 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 89 #ifndef CONFIG_SPL_BUILD 90 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 91 #endif 92 #define CONFIG_SPL_SPI_BOOT 93 #endif 94 95 #ifdef CONFIG_SDCARD 96 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 97 #define CONFIG_SPL_MMC_MINIMAL 98 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 99 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 100 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 101 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 102 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 103 #ifndef CONFIG_SPL_BUILD 104 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 105 #endif 106 #define CONFIG_SPL_MMC_BOOT 107 #endif 108 109 #endif /* CONFIG_RAMBOOT_PBL */ 110 111 #define CONFIG_SRIO_PCIE_BOOT_MASTER 112 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 113 /* Set 1M boot space */ 114 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 115 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 116 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 117 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 118 #define CONFIG_SYS_NO_FLASH 119 #endif 120 121 #ifndef CONFIG_SYS_TEXT_BASE 122 #define CONFIG_SYS_TEXT_BASE 0xeff40000 123 #endif 124 125 #ifndef CONFIG_RESET_VECTOR_ADDRESS 126 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 127 #endif 128 129 /* 130 * These can be toggled for performance analysis, otherwise use default. 131 */ 132 #define CONFIG_SYS_CACHE_STASHING 133 #define CONFIG_BTB /* toggle branch predition */ 134 #define CONFIG_DDR_ECC 135 #ifdef CONFIG_DDR_ECC 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 137 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 138 #endif 139 140 #ifndef CONFIG_SYS_NO_FLASH 141 #define CONFIG_FLASH_CFI_DRIVER 142 #define CONFIG_SYS_FLASH_CFI 143 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 144 #endif 145 146 #if defined(CONFIG_SPIFLASH) 147 #define CONFIG_SYS_EXTRA_ENV_RELOC 148 #define CONFIG_ENV_IS_IN_SPI_FLASH 149 #define CONFIG_ENV_SPI_BUS 0 150 #define CONFIG_ENV_SPI_CS 0 151 #define CONFIG_ENV_SPI_MAX_HZ 10000000 152 #define CONFIG_ENV_SPI_MODE 0 153 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 154 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 155 #define CONFIG_ENV_SECT_SIZE 0x10000 156 #elif defined(CONFIG_SDCARD) 157 #define CONFIG_SYS_EXTRA_ENV_RELOC 158 #define CONFIG_ENV_IS_IN_MMC 159 #define CONFIG_SYS_MMC_ENV_DEV 0 160 #define CONFIG_ENV_SIZE 0x2000 161 #define CONFIG_ENV_OFFSET (512 * 0x800) 162 #elif defined(CONFIG_NAND) 163 #define CONFIG_SYS_EXTRA_ENV_RELOC 164 #define CONFIG_ENV_IS_IN_NAND 165 #define CONFIG_ENV_SIZE 0x2000 166 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 167 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 168 #define CONFIG_ENV_IS_IN_REMOTE 169 #define CONFIG_ENV_ADDR 0xffe20000 170 #define CONFIG_ENV_SIZE 0x2000 171 #elif defined(CONFIG_ENV_IS_NOWHERE) 172 #define CONFIG_ENV_SIZE 0x2000 173 #else 174 #define CONFIG_ENV_IS_IN_FLASH 175 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 176 #define CONFIG_ENV_SIZE 0x2000 177 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 178 #endif 179 180 #ifndef __ASSEMBLY__ 181 unsigned long get_board_sys_clk(void); 182 unsigned long get_board_ddr_clk(void); 183 #endif 184 185 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 186 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 187 188 /* 189 * Config the L3 Cache as L3 SRAM 190 */ 191 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 192 #define CONFIG_SYS_L3_SIZE (512 << 10) 193 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 194 #ifdef CONFIG_RAMBOOT_PBL 195 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 196 #endif 197 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 198 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 199 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 200 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 201 202 #define CONFIG_SYS_DCSRBAR 0xf0000000 203 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 204 205 /* EEPROM */ 206 #define CONFIG_ID_EEPROM 207 #define CONFIG_SYS_I2C_EEPROM_NXID 208 #define CONFIG_SYS_EEPROM_BUS_NUM 0 209 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 210 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 211 212 /* 213 * DDR Setup 214 */ 215 #define CONFIG_VERY_BIG_RAM 216 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 217 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 218 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 219 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 220 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 221 #define CONFIG_DDR_SPD 222 #define CONFIG_SYS_FSL_DDR3 223 #define CONFIG_FSL_DDR_INTERACTIVE 224 #define CONFIG_SYS_SPD_BUS_NUM 0 225 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 226 #define SPD_EEPROM_ADDRESS1 0x51 227 #define SPD_EEPROM_ADDRESS2 0x52 228 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 229 #define CTRL_INTLV_PREFERED cacheline 230 231 /* 232 * IFC Definitions 233 */ 234 #define CONFIG_SYS_FLASH_BASE 0xe0000000 235 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 236 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 237 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 238 + 0x8000000) | \ 239 CSPR_PORT_SIZE_16 | \ 240 CSPR_MSEL_NOR | \ 241 CSPR_V) 242 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 243 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 244 CSPR_PORT_SIZE_16 | \ 245 CSPR_MSEL_NOR | \ 246 CSPR_V) 247 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 248 /* NOR Flash Timing Params */ 249 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 250 251 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 252 FTIM0_NOR_TEADC(0x5) | \ 253 FTIM0_NOR_TEAHC(0x5)) 254 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 255 FTIM1_NOR_TRAD_NOR(0x1A) |\ 256 FTIM1_NOR_TSEQRAD_NOR(0x13)) 257 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 258 FTIM2_NOR_TCH(0x4) | \ 259 FTIM2_NOR_TWPH(0x0E) | \ 260 FTIM2_NOR_TWP(0x1c)) 261 #define CONFIG_SYS_NOR_FTIM3 0x0 262 263 #define CONFIG_SYS_FLASH_QUIET_TEST 264 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 265 266 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 267 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 268 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 269 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 270 271 #define CONFIG_SYS_FLASH_EMPTY_INFO 272 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 273 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 274 275 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 276 #define QIXIS_BASE 0xffdf0000 277 #define QIXIS_LBMAP_SWITCH 6 278 #define QIXIS_LBMAP_MASK 0x0f 279 #define QIXIS_LBMAP_SHIFT 0 280 #define QIXIS_LBMAP_DFLTBANK 0x00 281 #define QIXIS_LBMAP_ALTBANK 0x04 282 #define QIXIS_LBMAP_NAND 0x09 283 #define QIXIS_LBMAP_SD 0x00 284 #define QIXIS_RCW_SRC_NAND 0x104 285 #define QIXIS_RCW_SRC_SD 0x040 286 #define QIXIS_RST_CTL_RESET 0x83 287 #define QIXIS_RST_FORCE_MEM 0x1 288 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 289 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 290 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 291 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 292 293 #define CONFIG_SYS_CSPR3_EXT (0xf) 294 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 295 | CSPR_PORT_SIZE_8 \ 296 | CSPR_MSEL_GPCM \ 297 | CSPR_V) 298 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 299 #define CONFIG_SYS_CSOR3 0x0 300 /* QIXIS Timing parameters for IFC CS3 */ 301 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 302 FTIM0_GPCM_TEADC(0x0e) | \ 303 FTIM0_GPCM_TEAHC(0x0e)) 304 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 305 FTIM1_GPCM_TRAD(0x3f)) 306 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 307 FTIM2_GPCM_TCH(0x8) | \ 308 FTIM2_GPCM_TWP(0x1f)) 309 #define CONFIG_SYS_CS3_FTIM3 0x0 310 311 /* NAND Flash on IFC */ 312 #define CONFIG_NAND_FSL_IFC 313 #define CONFIG_SYS_NAND_BASE 0xff800000 314 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 315 316 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 317 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 318 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 319 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 320 | CSPR_V) 321 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 322 323 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 324 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 325 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 326 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 327 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 328 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 329 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 330 331 #define CONFIG_SYS_NAND_ONFI_DETECTION 332 333 /* ONFI NAND Flash mode0 Timing Params */ 334 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 335 FTIM0_NAND_TWP(0x18) | \ 336 FTIM0_NAND_TWCHT(0x07) | \ 337 FTIM0_NAND_TWH(0x0a)) 338 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 339 FTIM1_NAND_TWBE(0x39) | \ 340 FTIM1_NAND_TRR(0x0e) | \ 341 FTIM1_NAND_TRP(0x18)) 342 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 343 FTIM2_NAND_TREH(0x0a) | \ 344 FTIM2_NAND_TWHRE(0x1e)) 345 #define CONFIG_SYS_NAND_FTIM3 0x0 346 347 #define CONFIG_SYS_NAND_DDR_LAW 11 348 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 349 #define CONFIG_SYS_MAX_NAND_DEVICE 1 350 #define CONFIG_CMD_NAND 351 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 352 353 #if defined(CONFIG_NAND) 354 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 355 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 356 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 357 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 358 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 359 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 360 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 361 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 362 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 363 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 364 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 365 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 366 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 367 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 368 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 369 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 370 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 371 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 372 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 373 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 374 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 375 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 376 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 377 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 378 #else 379 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 380 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 381 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 382 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 383 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 384 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 385 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 386 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 387 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 388 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 389 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 390 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 391 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 392 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 393 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 394 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 395 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 396 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 397 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 398 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 399 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 400 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 401 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 402 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 403 #endif 404 405 #if defined(CONFIG_RAMBOOT_PBL) 406 #define CONFIG_SYS_RAMBOOT 407 #endif 408 409 #ifdef CONFIG_SPL_BUILD 410 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 411 #else 412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 413 #endif 414 415 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 416 #define CONFIG_MISC_INIT_R 417 #define CONFIG_HWCONFIG 418 419 /* define to use L1 as initial stack */ 420 #define CONFIG_L1_INIT_RAM 421 #define CONFIG_SYS_INIT_RAM_LOCK 422 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 425 /* The assembler doesn't like typecast */ 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 427 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 428 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 429 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 430 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 431 GENERATED_GBL_DATA_SIZE) 432 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 433 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 434 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 435 436 /* 437 * Serial Port 438 */ 439 #define CONFIG_CONS_INDEX 1 440 #define CONFIG_SYS_NS16550_SERIAL 441 #define CONFIG_SYS_NS16550_REG_SIZE 1 442 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 443 #define CONFIG_SYS_BAUDRATE_TABLE \ 444 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 445 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 446 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 447 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 448 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 449 450 /* 451 * I2C 452 */ 453 #define CONFIG_SYS_I2C 454 #define CONFIG_SYS_I2C_FSL 455 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 456 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 457 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 458 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 459 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 460 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 461 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 462 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 463 #define CONFIG_SYS_FSL_I2C_SPEED 100000 464 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 465 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 466 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 467 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 468 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 469 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 470 #define I2C_MUX_CH_DEFAULT 0x8 471 472 #define I2C_MUX_CH_VOL_MONITOR 0xa 473 474 /* Voltage monitor on channel 2*/ 475 #define I2C_VOL_MONITOR_ADDR 0x40 476 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 477 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 478 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 479 480 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 481 #ifndef CONFIG_SPL_BUILD 482 #define CONFIG_VID 483 #endif 484 #define CONFIG_VOL_MONITOR_IR36021_SET 485 #define CONFIG_VOL_MONITOR_IR36021_READ 486 /* The lowest and highest voltage allowed for T208xQDS */ 487 #define VDD_MV_MIN 819 488 #define VDD_MV_MAX 1212 489 490 /* 491 * RapidIO 492 */ 493 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 494 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 495 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 496 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 497 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 498 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 499 /* 500 * for slave u-boot IMAGE instored in master memory space, 501 * PHYS must be aligned based on the SIZE 502 */ 503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 504 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 505 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 506 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 507 /* 508 * for slave UCODE and ENV instored in master memory space, 509 * PHYS must be aligned based on the SIZE 510 */ 511 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 512 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 513 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 514 515 /* slave core release by master*/ 516 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 517 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 518 519 /* 520 * SRIO_PCIE_BOOT - SLAVE 521 */ 522 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 523 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 524 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 525 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 526 #endif 527 528 /* 529 * eSPI - Enhanced SPI 530 */ 531 #ifdef CONFIG_SPI_FLASH 532 #ifndef CONFIG_SPL_BUILD 533 #endif 534 535 #define CONFIG_SPI_FLASH_BAR 536 #define CONFIG_SF_DEFAULT_SPEED 10000000 537 #define CONFIG_SF_DEFAULT_MODE 0 538 #endif 539 540 /* 541 * General PCI 542 * Memory space is mapped 1-1, but I/O space must start from 0. 543 */ 544 #define CONFIG_PCI /* Enable PCI/PCIE */ 545 #define CONFIG_PCIE1 /* PCIE controller 1 */ 546 #define CONFIG_PCIE2 /* PCIE controller 2 */ 547 #define CONFIG_PCIE3 /* PCIE controller 3 */ 548 #define CONFIG_PCIE4 /* PCIE controller 4 */ 549 #define CONFIG_FSL_PCIE_RESET 550 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 551 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 552 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 553 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 554 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 555 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 556 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 557 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 558 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 559 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 560 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 561 562 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 563 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 564 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 565 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 566 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 567 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 568 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 569 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 570 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 571 572 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 573 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 574 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 575 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 576 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 577 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 578 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 579 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 580 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 581 582 /* controller 4, Base address 203000 */ 583 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 584 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 585 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 586 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 587 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 588 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 589 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 590 591 #ifdef CONFIG_PCI 592 #define CONFIG_PCI_INDIRECT_BRIDGE 593 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 594 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 595 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 596 #define CONFIG_DOS_PARTITION 597 #endif 598 599 /* Qman/Bman */ 600 #ifndef CONFIG_NOBQFMAN 601 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 602 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 603 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 604 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 605 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 606 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 607 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 608 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 609 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 610 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 611 CONFIG_SYS_BMAN_CENA_SIZE) 612 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 613 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 614 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 615 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 616 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 617 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 618 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 619 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 620 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 621 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 622 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 623 CONFIG_SYS_QMAN_CENA_SIZE) 624 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 625 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 626 627 #define CONFIG_SYS_DPAA_FMAN 628 #define CONFIG_SYS_DPAA_PME 629 #define CONFIG_SYS_PMAN 630 #define CONFIG_SYS_DPAA_DCE 631 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 632 #define CONFIG_SYS_INTERLAKEN 633 634 /* Default address of microcode for the Linux Fman driver */ 635 #if defined(CONFIG_SPIFLASH) 636 /* 637 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 638 * env, so we got 0x110000. 639 */ 640 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 641 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 642 #elif defined(CONFIG_SDCARD) 643 /* 644 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 645 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 646 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 647 */ 648 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 649 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 650 #elif defined(CONFIG_NAND) 651 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 652 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 653 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 654 /* 655 * Slave has no ucode locally, it can fetch this from remote. When implementing 656 * in two corenet boards, slave's ucode could be stored in master's memory 657 * space, the address can be mapped from slave TLB->slave LAW-> 658 * slave SRIO or PCIE outbound window->master inbound window-> 659 * master LAW->the ucode address in master's memory space. 660 */ 661 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 662 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 663 #else 664 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 665 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 666 #endif 667 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 668 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 669 #endif /* CONFIG_NOBQFMAN */ 670 671 #ifdef CONFIG_SYS_DPAA_FMAN 672 #define CONFIG_FMAN_ENET 673 #define CONFIG_PHYLIB_10G 674 #define CONFIG_PHY_VITESSE 675 #define CONFIG_PHY_REALTEK 676 #define CONFIG_PHY_TERANETICS 677 #define RGMII_PHY1_ADDR 0x1 678 #define RGMII_PHY2_ADDR 0x2 679 #define FM1_10GEC1_PHY_ADDR 0x3 680 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 681 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 682 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 683 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 684 #endif 685 686 #ifdef CONFIG_FMAN_ENET 687 #define CONFIG_MII /* MII PHY management */ 688 #define CONFIG_ETHPRIME "FM1@DTSEC3" 689 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 690 #endif 691 692 /* 693 * SATA 694 */ 695 #ifdef CONFIG_FSL_SATA_V2 696 #define CONFIG_LIBATA 697 #define CONFIG_FSL_SATA 698 #define CONFIG_SYS_SATA_MAX_DEVICE 2 699 #define CONFIG_SATA1 700 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 701 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 702 #define CONFIG_SATA2 703 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 704 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 705 #define CONFIG_LBA48 706 #define CONFIG_CMD_SATA 707 #define CONFIG_DOS_PARTITION 708 #endif 709 710 /* 711 * USB 712 */ 713 #ifdef CONFIG_USB_EHCI 714 #define CONFIG_USB_EHCI_FSL 715 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 716 #define CONFIG_HAS_FSL_DR_USB 717 #endif 718 719 /* 720 * SDHC 721 */ 722 #ifdef CONFIG_MMC 723 #define CONFIG_FSL_ESDHC 724 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 725 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 726 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 727 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 728 #define CONFIG_GENERIC_MMC 729 #define CONFIG_DOS_PARTITION 730 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 731 #endif 732 733 /* 734 * Dynamic MTD Partition support with mtdparts 735 */ 736 #ifndef CONFIG_SYS_NO_FLASH 737 #define CONFIG_MTD_DEVICE 738 #define CONFIG_MTD_PARTITIONS 739 #define CONFIG_CMD_MTDPARTS 740 #define CONFIG_FLASH_CFI_MTD 741 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 742 "spi0=spife110000.0" 743 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 744 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 745 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 746 "1m(uboot),5m(kernel),128k(dtb),-(user)" 747 #endif 748 749 /* 750 * Environment 751 */ 752 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 753 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 754 755 /* 756 * Command line configuration. 757 */ 758 #define CONFIG_CMD_ERRATA 759 #define CONFIG_CMD_IRQ 760 #define CONFIG_CMD_REGINFO 761 762 #ifdef CONFIG_PCI 763 #define CONFIG_CMD_PCI 764 #endif 765 766 /* Hash command with SHA acceleration supported in hardware */ 767 #ifdef CONFIG_FSL_CAAM 768 #define CONFIG_CMD_HASH 769 #define CONFIG_SHA_HW_ACCEL 770 #endif 771 772 /* 773 * Miscellaneous configurable options 774 */ 775 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 776 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 777 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 778 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 779 #ifdef CONFIG_CMD_KGDB 780 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 781 #else 782 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 783 #endif 784 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 785 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 786 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 787 788 /* 789 * For booting Linux, the board info and command line data 790 * have to be in the first 64 MB of memory, since this is 791 * the maximum mapped by the Linux kernel during initialization. 792 */ 793 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 794 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 795 796 #ifdef CONFIG_CMD_KGDB 797 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 798 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 799 #endif 800 801 /* 802 * Environment Configuration 803 */ 804 #define CONFIG_ROOTPATH "/opt/nfsroot" 805 #define CONFIG_BOOTFILE "uImage" 806 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 807 808 /* default location for tftp and bootm */ 809 #define CONFIG_LOADADDR 1000000 810 #define CONFIG_BAUDRATE 115200 811 #define __USB_PHY_TYPE utmi 812 813 #define CONFIG_EXTRA_ENV_SETTINGS \ 814 "hwconfig=fsl_ddr:" \ 815 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 816 "bank_intlv=auto;" \ 817 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 818 "netdev=eth0\0" \ 819 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 820 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 821 "tftpflash=tftpboot $loadaddr $uboot && " \ 822 "protect off $ubootaddr +$filesize && " \ 823 "erase $ubootaddr +$filesize && " \ 824 "cp.b $loadaddr $ubootaddr $filesize && " \ 825 "protect on $ubootaddr +$filesize && " \ 826 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 827 "consoledev=ttyS0\0" \ 828 "ramdiskaddr=2000000\0" \ 829 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 830 "fdtaddr=1e00000\0" \ 831 "fdtfile=t2080qds/t2080qds.dtb\0" \ 832 "bdev=sda3\0" 833 834 /* 835 * For emulation this causes u-boot to jump to the start of the 836 * proof point app code automatically 837 */ 838 #define CONFIG_PROOF_POINTS \ 839 "setenv bootargs root=/dev/$bdev rw " \ 840 "console=$consoledev,$baudrate $othbootargs;" \ 841 "cpu 1 release 0x29000000 - - -;" \ 842 "cpu 2 release 0x29000000 - - -;" \ 843 "cpu 3 release 0x29000000 - - -;" \ 844 "cpu 4 release 0x29000000 - - -;" \ 845 "cpu 5 release 0x29000000 - - -;" \ 846 "cpu 6 release 0x29000000 - - -;" \ 847 "cpu 7 release 0x29000000 - - -;" \ 848 "go 0x29000000" 849 850 #define CONFIG_HVBOOT \ 851 "setenv bootargs config-addr=0x60000000; " \ 852 "bootm 0x01000000 - 0x00f00000" 853 854 #define CONFIG_ALU \ 855 "setenv bootargs root=/dev/$bdev rw " \ 856 "console=$consoledev,$baudrate $othbootargs;" \ 857 "cpu 1 release 0x01000000 - - -;" \ 858 "cpu 2 release 0x01000000 - - -;" \ 859 "cpu 3 release 0x01000000 - - -;" \ 860 "cpu 4 release 0x01000000 - - -;" \ 861 "cpu 5 release 0x01000000 - - -;" \ 862 "cpu 6 release 0x01000000 - - -;" \ 863 "cpu 7 release 0x01000000 - - -;" \ 864 "go 0x01000000" 865 866 #define CONFIG_LINUX \ 867 "setenv bootargs root=/dev/ram rw " \ 868 "console=$consoledev,$baudrate $othbootargs;" \ 869 "setenv ramdiskaddr 0x02000000;" \ 870 "setenv fdtaddr 0x00c00000;" \ 871 "setenv loadaddr 0x1000000;" \ 872 "bootm $loadaddr $ramdiskaddr $fdtaddr" 873 874 #define CONFIG_HDBOOT \ 875 "setenv bootargs root=/dev/$bdev rw " \ 876 "console=$consoledev,$baudrate $othbootargs;" \ 877 "tftp $loadaddr $bootfile;" \ 878 "tftp $fdtaddr $fdtfile;" \ 879 "bootm $loadaddr - $fdtaddr" 880 881 #define CONFIG_NFSBOOTCOMMAND \ 882 "setenv bootargs root=/dev/nfs rw " \ 883 "nfsroot=$serverip:$rootpath " \ 884 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 885 "console=$consoledev,$baudrate $othbootargs;" \ 886 "tftp $loadaddr $bootfile;" \ 887 "tftp $fdtaddr $fdtfile;" \ 888 "bootm $loadaddr - $fdtaddr" 889 890 #define CONFIG_RAMBOOTCOMMAND \ 891 "setenv bootargs root=/dev/ram rw " \ 892 "console=$consoledev,$baudrate $othbootargs;" \ 893 "tftp $ramdiskaddr $ramdiskfile;" \ 894 "tftp $loadaddr $bootfile;" \ 895 "tftp $fdtaddr $fdtfile;" \ 896 "bootm $loadaddr $ramdiskaddr $fdtaddr" 897 898 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 899 900 #include <asm/fsl_secure_boot.h> 901 902 #endif /* __T208xQDS_H */ 903