1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_USB_EHCI 16 #if defined(CONFIG_ARCH_T2080) 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 19 #define CONFIG_SRIO1 /* SRIO port 1 */ 20 #define CONFIG_SRIO2 /* SRIO port 2 */ 21 #elif defined(CONFIG_ARCH_T2081) 22 #endif 23 24 /* High Level Configuration Options */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 36 #define CONFIG_FSL_IFC /* Enable IFC Support */ 37 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 38 #define CONFIG_ENV_OVERWRITE 39 40 #ifdef CONFIG_RAMBOOT_PBL 41 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 42 43 #define CONFIG_SPL_FLUSH_IMAGE 44 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 45 #define CONFIG_SYS_TEXT_BASE 0x00201000 46 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 47 #define CONFIG_SPL_PAD_TO 0x40000 48 #define CONFIG_SPL_MAX_SIZE 0x28000 49 #define RESET_VECTOR_OFFSET 0x27FFC 50 #define BOOT_PAGE_OFFSET 0x27000 51 #ifdef CONFIG_SPL_BUILD 52 #define CONFIG_SPL_SKIP_RELOCATE 53 #define CONFIG_SPL_COMMON_INIT_DDR 54 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 55 #define CONFIG_SYS_NO_FLASH 56 #endif 57 58 #ifdef CONFIG_NAND 59 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 60 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 61 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 62 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 63 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 64 #if defined(CONFIG_ARCH_T2080) 65 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 66 #elif defined(CONFIG_ARCH_T2081) 67 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 68 #endif 69 #define CONFIG_SPL_NAND_BOOT 70 #endif 71 72 #ifdef CONFIG_SPIFLASH 73 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 74 #define CONFIG_SPL_SPI_FLASH_MINIMAL 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 79 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 80 #ifndef CONFIG_SPL_BUILD 81 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 82 #endif 83 #if defined(CONFIG_ARCH_T2080) 84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 85 #elif defined(CONFIG_ARCH_T2081) 86 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 87 #endif 88 #define CONFIG_SPL_SPI_BOOT 89 #endif 90 91 #ifdef CONFIG_SDCARD 92 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 93 #define CONFIG_SPL_MMC_MINIMAL 94 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 95 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 96 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 97 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 98 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 99 #ifndef CONFIG_SPL_BUILD 100 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 101 #endif 102 #if defined(CONFIG_ARCH_T2080) 103 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 104 #elif defined(CONFIG_ARCH_T2081) 105 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 106 #endif 107 #define CONFIG_SPL_MMC_BOOT 108 #endif 109 110 #endif /* CONFIG_RAMBOOT_PBL */ 111 112 #define CONFIG_SRIO_PCIE_BOOT_MASTER 113 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 114 /* Set 1M boot space */ 115 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 116 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 117 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 118 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 119 #define CONFIG_SYS_NO_FLASH 120 #endif 121 122 #ifndef CONFIG_SYS_TEXT_BASE 123 #define CONFIG_SYS_TEXT_BASE 0xeff40000 124 #endif 125 126 #ifndef CONFIG_RESET_VECTOR_ADDRESS 127 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 128 #endif 129 130 /* 131 * These can be toggled for performance analysis, otherwise use default. 132 */ 133 #define CONFIG_SYS_CACHE_STASHING 134 #define CONFIG_BTB /* toggle branch predition */ 135 #define CONFIG_DDR_ECC 136 #ifdef CONFIG_DDR_ECC 137 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 138 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 139 #endif 140 141 #ifndef CONFIG_SYS_NO_FLASH 142 #define CONFIG_FLASH_CFI_DRIVER 143 #define CONFIG_SYS_FLASH_CFI 144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 145 #endif 146 147 #if defined(CONFIG_SPIFLASH) 148 #define CONFIG_SYS_EXTRA_ENV_RELOC 149 #define CONFIG_ENV_IS_IN_SPI_FLASH 150 #define CONFIG_ENV_SPI_BUS 0 151 #define CONFIG_ENV_SPI_CS 0 152 #define CONFIG_ENV_SPI_MAX_HZ 10000000 153 #define CONFIG_ENV_SPI_MODE 0 154 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 155 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 156 #define CONFIG_ENV_SECT_SIZE 0x10000 157 #elif defined(CONFIG_SDCARD) 158 #define CONFIG_SYS_EXTRA_ENV_RELOC 159 #define CONFIG_ENV_IS_IN_MMC 160 #define CONFIG_SYS_MMC_ENV_DEV 0 161 #define CONFIG_ENV_SIZE 0x2000 162 #define CONFIG_ENV_OFFSET (512 * 0x800) 163 #elif defined(CONFIG_NAND) 164 #define CONFIG_SYS_EXTRA_ENV_RELOC 165 #define CONFIG_ENV_IS_IN_NAND 166 #define CONFIG_ENV_SIZE 0x2000 167 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 168 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 169 #define CONFIG_ENV_IS_IN_REMOTE 170 #define CONFIG_ENV_ADDR 0xffe20000 171 #define CONFIG_ENV_SIZE 0x2000 172 #elif defined(CONFIG_ENV_IS_NOWHERE) 173 #define CONFIG_ENV_SIZE 0x2000 174 #else 175 #define CONFIG_ENV_IS_IN_FLASH 176 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 177 #define CONFIG_ENV_SIZE 0x2000 178 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 179 #endif 180 181 #ifndef __ASSEMBLY__ 182 unsigned long get_board_sys_clk(void); 183 unsigned long get_board_ddr_clk(void); 184 #endif 185 186 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 187 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 188 189 /* 190 * Config the L3 Cache as L3 SRAM 191 */ 192 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 193 #define CONFIG_SYS_L3_SIZE (512 << 10) 194 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 195 #ifdef CONFIG_RAMBOOT_PBL 196 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 197 #endif 198 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 199 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 200 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 201 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 202 203 #define CONFIG_SYS_DCSRBAR 0xf0000000 204 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 205 206 /* EEPROM */ 207 #define CONFIG_ID_EEPROM 208 #define CONFIG_SYS_I2C_EEPROM_NXID 209 #define CONFIG_SYS_EEPROM_BUS_NUM 0 210 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 211 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 212 213 /* 214 * DDR Setup 215 */ 216 #define CONFIG_VERY_BIG_RAM 217 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 218 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 219 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 220 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 221 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 222 #define CONFIG_DDR_SPD 223 #define CONFIG_FSL_DDR_INTERACTIVE 224 #define CONFIG_SYS_SPD_BUS_NUM 0 225 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 226 #define SPD_EEPROM_ADDRESS1 0x51 227 #define SPD_EEPROM_ADDRESS2 0x52 228 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 229 #define CTRL_INTLV_PREFERED cacheline 230 231 /* 232 * IFC Definitions 233 */ 234 #define CONFIG_SYS_FLASH_BASE 0xe0000000 235 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 236 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 237 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 238 + 0x8000000) | \ 239 CSPR_PORT_SIZE_16 | \ 240 CSPR_MSEL_NOR | \ 241 CSPR_V) 242 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 243 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 244 CSPR_PORT_SIZE_16 | \ 245 CSPR_MSEL_NOR | \ 246 CSPR_V) 247 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 248 /* NOR Flash Timing Params */ 249 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 250 251 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 252 FTIM0_NOR_TEADC(0x5) | \ 253 FTIM0_NOR_TEAHC(0x5)) 254 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 255 FTIM1_NOR_TRAD_NOR(0x1A) |\ 256 FTIM1_NOR_TSEQRAD_NOR(0x13)) 257 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 258 FTIM2_NOR_TCH(0x4) | \ 259 FTIM2_NOR_TWPH(0x0E) | \ 260 FTIM2_NOR_TWP(0x1c)) 261 #define CONFIG_SYS_NOR_FTIM3 0x0 262 263 #define CONFIG_SYS_FLASH_QUIET_TEST 264 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 265 266 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 267 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 268 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 269 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 270 271 #define CONFIG_SYS_FLASH_EMPTY_INFO 272 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 273 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 274 275 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 276 #define QIXIS_BASE 0xffdf0000 277 #define QIXIS_LBMAP_SWITCH 6 278 #define QIXIS_LBMAP_MASK 0x0f 279 #define QIXIS_LBMAP_SHIFT 0 280 #define QIXIS_LBMAP_DFLTBANK 0x00 281 #define QIXIS_LBMAP_ALTBANK 0x04 282 #define QIXIS_LBMAP_NAND 0x09 283 #define QIXIS_LBMAP_SD 0x00 284 #define QIXIS_RCW_SRC_NAND 0x104 285 #define QIXIS_RCW_SRC_SD 0x040 286 #define QIXIS_RST_CTL_RESET 0x83 287 #define QIXIS_RST_FORCE_MEM 0x1 288 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 289 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 290 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 291 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 292 293 #define CONFIG_SYS_CSPR3_EXT (0xf) 294 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 295 | CSPR_PORT_SIZE_8 \ 296 | CSPR_MSEL_GPCM \ 297 | CSPR_V) 298 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 299 #define CONFIG_SYS_CSOR3 0x0 300 /* QIXIS Timing parameters for IFC CS3 */ 301 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 302 FTIM0_GPCM_TEADC(0x0e) | \ 303 FTIM0_GPCM_TEAHC(0x0e)) 304 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 305 FTIM1_GPCM_TRAD(0x3f)) 306 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 307 FTIM2_GPCM_TCH(0x8) | \ 308 FTIM2_GPCM_TWP(0x1f)) 309 #define CONFIG_SYS_CS3_FTIM3 0x0 310 311 /* NAND Flash on IFC */ 312 #define CONFIG_NAND_FSL_IFC 313 #define CONFIG_SYS_NAND_BASE 0xff800000 314 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 315 316 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 317 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 318 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 319 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 320 | CSPR_V) 321 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 322 323 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 324 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 325 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 326 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 327 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 328 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 329 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 330 331 #define CONFIG_SYS_NAND_ONFI_DETECTION 332 333 /* ONFI NAND Flash mode0 Timing Params */ 334 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 335 FTIM0_NAND_TWP(0x18) | \ 336 FTIM0_NAND_TWCHT(0x07) | \ 337 FTIM0_NAND_TWH(0x0a)) 338 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 339 FTIM1_NAND_TWBE(0x39) | \ 340 FTIM1_NAND_TRR(0x0e) | \ 341 FTIM1_NAND_TRP(0x18)) 342 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 343 FTIM2_NAND_TREH(0x0a) | \ 344 FTIM2_NAND_TWHRE(0x1e)) 345 #define CONFIG_SYS_NAND_FTIM3 0x0 346 347 #define CONFIG_SYS_NAND_DDR_LAW 11 348 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 349 #define CONFIG_SYS_MAX_NAND_DEVICE 1 350 #define CONFIG_CMD_NAND 351 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 352 353 #if defined(CONFIG_NAND) 354 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 355 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 356 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 357 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 358 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 359 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 360 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 361 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 362 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 363 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 364 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 365 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 366 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 367 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 368 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 369 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 370 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 371 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 372 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 373 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 374 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 375 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 376 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 377 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 378 #else 379 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 380 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 381 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 382 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 383 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 384 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 385 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 386 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 387 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 388 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 389 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 390 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 391 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 392 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 393 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 394 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 395 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 396 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 397 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 398 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 399 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 400 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 401 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 402 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 403 #endif 404 405 #if defined(CONFIG_RAMBOOT_PBL) 406 #define CONFIG_SYS_RAMBOOT 407 #endif 408 409 #ifdef CONFIG_SPL_BUILD 410 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 411 #else 412 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 413 #endif 414 415 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 416 #define CONFIG_MISC_INIT_R 417 #define CONFIG_HWCONFIG 418 419 /* define to use L1 as initial stack */ 420 #define CONFIG_L1_INIT_RAM 421 #define CONFIG_SYS_INIT_RAM_LOCK 422 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 425 /* The assembler doesn't like typecast */ 426 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 427 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 428 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 429 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 430 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 431 GENERATED_GBL_DATA_SIZE) 432 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 433 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 434 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 435 436 /* 437 * Serial Port 438 */ 439 #define CONFIG_CONS_INDEX 1 440 #define CONFIG_SYS_NS16550_SERIAL 441 #define CONFIG_SYS_NS16550_REG_SIZE 1 442 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 443 #define CONFIG_SYS_BAUDRATE_TABLE \ 444 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 445 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 446 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 447 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 448 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 449 450 /* 451 * I2C 452 */ 453 #define CONFIG_SYS_I2C 454 #define CONFIG_SYS_I2C_FSL 455 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 456 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 457 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 458 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 459 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 460 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 461 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 462 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 463 #define CONFIG_SYS_FSL_I2C_SPEED 100000 464 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 465 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 466 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 467 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 468 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 469 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 470 #define I2C_MUX_CH_DEFAULT 0x8 471 472 #define I2C_MUX_CH_VOL_MONITOR 0xa 473 474 /* Voltage monitor on channel 2*/ 475 #define I2C_VOL_MONITOR_ADDR 0x40 476 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 477 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 478 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 479 480 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 481 #ifndef CONFIG_SPL_BUILD 482 #define CONFIG_VID 483 #endif 484 #define CONFIG_VOL_MONITOR_IR36021_SET 485 #define CONFIG_VOL_MONITOR_IR36021_READ 486 /* The lowest and highest voltage allowed for T208xQDS */ 487 #define VDD_MV_MIN 819 488 #define VDD_MV_MAX 1212 489 490 /* 491 * RapidIO 492 */ 493 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 494 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 495 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 496 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 497 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 498 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 499 /* 500 * for slave u-boot IMAGE instored in master memory space, 501 * PHYS must be aligned based on the SIZE 502 */ 503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 504 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 505 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 506 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 507 /* 508 * for slave UCODE and ENV instored in master memory space, 509 * PHYS must be aligned based on the SIZE 510 */ 511 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 512 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 513 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 514 515 /* slave core release by master*/ 516 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 517 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 518 519 /* 520 * SRIO_PCIE_BOOT - SLAVE 521 */ 522 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 523 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 524 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 525 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 526 #endif 527 528 /* 529 * eSPI - Enhanced SPI 530 */ 531 #ifdef CONFIG_SPI_FLASH 532 #ifndef CONFIG_SPL_BUILD 533 #endif 534 535 #define CONFIG_SPI_FLASH_BAR 536 #define CONFIG_SF_DEFAULT_SPEED 10000000 537 #define CONFIG_SF_DEFAULT_MODE 0 538 #endif 539 540 /* 541 * General PCI 542 * Memory space is mapped 1-1, but I/O space must start from 0. 543 */ 544 #define CONFIG_PCIE1 /* PCIE controller 1 */ 545 #define CONFIG_PCIE2 /* PCIE controller 2 */ 546 #define CONFIG_PCIE3 /* PCIE controller 3 */ 547 #define CONFIG_PCIE4 /* PCIE controller 4 */ 548 #define CONFIG_FSL_PCIE_RESET 549 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 550 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 551 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 552 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 553 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 554 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 555 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 556 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 557 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 558 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 559 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 560 561 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 562 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 563 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 564 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 565 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 566 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 567 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 568 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 569 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 570 571 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 572 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 573 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 574 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 575 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 576 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 577 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 578 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 579 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 580 581 /* controller 4, Base address 203000 */ 582 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 583 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 584 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 585 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 586 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 587 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 588 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 589 590 #ifdef CONFIG_PCI 591 #define CONFIG_PCI_INDIRECT_BRIDGE 592 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 593 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 594 #endif 595 596 /* Qman/Bman */ 597 #ifndef CONFIG_NOBQFMAN 598 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 599 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 600 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 601 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 602 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 603 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 604 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 605 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 606 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 607 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 608 CONFIG_SYS_BMAN_CENA_SIZE) 609 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 610 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 611 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 612 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 613 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 614 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 615 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 616 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 617 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 618 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 619 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 620 CONFIG_SYS_QMAN_CENA_SIZE) 621 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 622 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 623 624 #define CONFIG_SYS_DPAA_FMAN 625 #define CONFIG_SYS_DPAA_PME 626 #define CONFIG_SYS_PMAN 627 #define CONFIG_SYS_DPAA_DCE 628 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 629 #define CONFIG_SYS_INTERLAKEN 630 631 /* Default address of microcode for the Linux Fman driver */ 632 #if defined(CONFIG_SPIFLASH) 633 /* 634 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 635 * env, so we got 0x110000. 636 */ 637 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 638 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 639 #elif defined(CONFIG_SDCARD) 640 /* 641 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 642 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 643 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 644 */ 645 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 646 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 647 #elif defined(CONFIG_NAND) 648 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 649 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 650 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 651 /* 652 * Slave has no ucode locally, it can fetch this from remote. When implementing 653 * in two corenet boards, slave's ucode could be stored in master's memory 654 * space, the address can be mapped from slave TLB->slave LAW-> 655 * slave SRIO or PCIE outbound window->master inbound window-> 656 * master LAW->the ucode address in master's memory space. 657 */ 658 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 659 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 660 #else 661 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 662 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 663 #endif 664 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 665 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 666 #endif /* CONFIG_NOBQFMAN */ 667 668 #ifdef CONFIG_SYS_DPAA_FMAN 669 #define CONFIG_FMAN_ENET 670 #define CONFIG_PHYLIB_10G 671 #define CONFIG_PHY_VITESSE 672 #define CONFIG_PHY_REALTEK 673 #define CONFIG_PHY_TERANETICS 674 #define RGMII_PHY1_ADDR 0x1 675 #define RGMII_PHY2_ADDR 0x2 676 #define FM1_10GEC1_PHY_ADDR 0x3 677 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 678 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 679 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 680 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 681 #endif 682 683 #ifdef CONFIG_FMAN_ENET 684 #define CONFIG_MII /* MII PHY management */ 685 #define CONFIG_ETHPRIME "FM1@DTSEC3" 686 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 687 #endif 688 689 /* 690 * SATA 691 */ 692 #ifdef CONFIG_FSL_SATA_V2 693 #define CONFIG_LIBATA 694 #define CONFIG_FSL_SATA 695 #define CONFIG_SYS_SATA_MAX_DEVICE 2 696 #define CONFIG_SATA1 697 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 698 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 699 #define CONFIG_SATA2 700 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 701 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 702 #define CONFIG_LBA48 703 #define CONFIG_CMD_SATA 704 #endif 705 706 /* 707 * USB 708 */ 709 #ifdef CONFIG_USB_EHCI 710 #define CONFIG_USB_EHCI_FSL 711 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 712 #define CONFIG_HAS_FSL_DR_USB 713 #endif 714 715 /* 716 * SDHC 717 */ 718 #ifdef CONFIG_MMC 719 #define CONFIG_FSL_ESDHC 720 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 721 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 722 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 723 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 724 #define CONFIG_GENERIC_MMC 725 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 726 #endif 727 728 /* 729 * Dynamic MTD Partition support with mtdparts 730 */ 731 #ifndef CONFIG_SYS_NO_FLASH 732 #define CONFIG_MTD_DEVICE 733 #define CONFIG_MTD_PARTITIONS 734 #define CONFIG_CMD_MTDPARTS 735 #define CONFIG_FLASH_CFI_MTD 736 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 737 "spi0=spife110000.0" 738 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 739 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 740 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 741 "1m(uboot),5m(kernel),128k(dtb),-(user)" 742 #endif 743 744 /* 745 * Environment 746 */ 747 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 748 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 749 750 /* 751 * Command line configuration. 752 */ 753 #define CONFIG_CMD_ERRATA 754 #define CONFIG_CMD_IRQ 755 #define CONFIG_CMD_REGINFO 756 757 #ifdef CONFIG_PCI 758 #define CONFIG_CMD_PCI 759 #endif 760 761 /* Hash command with SHA acceleration supported in hardware */ 762 #ifdef CONFIG_FSL_CAAM 763 #define CONFIG_CMD_HASH 764 #define CONFIG_SHA_HW_ACCEL 765 #endif 766 767 /* 768 * Miscellaneous configurable options 769 */ 770 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 771 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 772 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 773 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 774 #ifdef CONFIG_CMD_KGDB 775 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 776 #else 777 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 778 #endif 779 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 780 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 781 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 782 783 /* 784 * For booting Linux, the board info and command line data 785 * have to be in the first 64 MB of memory, since this is 786 * the maximum mapped by the Linux kernel during initialization. 787 */ 788 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 789 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 790 791 #ifdef CONFIG_CMD_KGDB 792 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 793 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 794 #endif 795 796 /* 797 * Environment Configuration 798 */ 799 #define CONFIG_ROOTPATH "/opt/nfsroot" 800 #define CONFIG_BOOTFILE "uImage" 801 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 802 803 /* default location for tftp and bootm */ 804 #define CONFIG_LOADADDR 1000000 805 #define CONFIG_BAUDRATE 115200 806 #define __USB_PHY_TYPE utmi 807 808 #define CONFIG_EXTRA_ENV_SETTINGS \ 809 "hwconfig=fsl_ddr:" \ 810 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 811 "bank_intlv=auto;" \ 812 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 813 "netdev=eth0\0" \ 814 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 815 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 816 "tftpflash=tftpboot $loadaddr $uboot && " \ 817 "protect off $ubootaddr +$filesize && " \ 818 "erase $ubootaddr +$filesize && " \ 819 "cp.b $loadaddr $ubootaddr $filesize && " \ 820 "protect on $ubootaddr +$filesize && " \ 821 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 822 "consoledev=ttyS0\0" \ 823 "ramdiskaddr=2000000\0" \ 824 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 825 "fdtaddr=1e00000\0" \ 826 "fdtfile=t2080qds/t2080qds.dtb\0" \ 827 "bdev=sda3\0" 828 829 /* 830 * For emulation this causes u-boot to jump to the start of the 831 * proof point app code automatically 832 */ 833 #define CONFIG_PROOF_POINTS \ 834 "setenv bootargs root=/dev/$bdev rw " \ 835 "console=$consoledev,$baudrate $othbootargs;" \ 836 "cpu 1 release 0x29000000 - - -;" \ 837 "cpu 2 release 0x29000000 - - -;" \ 838 "cpu 3 release 0x29000000 - - -;" \ 839 "cpu 4 release 0x29000000 - - -;" \ 840 "cpu 5 release 0x29000000 - - -;" \ 841 "cpu 6 release 0x29000000 - - -;" \ 842 "cpu 7 release 0x29000000 - - -;" \ 843 "go 0x29000000" 844 845 #define CONFIG_HVBOOT \ 846 "setenv bootargs config-addr=0x60000000; " \ 847 "bootm 0x01000000 - 0x00f00000" 848 849 #define CONFIG_ALU \ 850 "setenv bootargs root=/dev/$bdev rw " \ 851 "console=$consoledev,$baudrate $othbootargs;" \ 852 "cpu 1 release 0x01000000 - - -;" \ 853 "cpu 2 release 0x01000000 - - -;" \ 854 "cpu 3 release 0x01000000 - - -;" \ 855 "cpu 4 release 0x01000000 - - -;" \ 856 "cpu 5 release 0x01000000 - - -;" \ 857 "cpu 6 release 0x01000000 - - -;" \ 858 "cpu 7 release 0x01000000 - - -;" \ 859 "go 0x01000000" 860 861 #define CONFIG_LINUX \ 862 "setenv bootargs root=/dev/ram rw " \ 863 "console=$consoledev,$baudrate $othbootargs;" \ 864 "setenv ramdiskaddr 0x02000000;" \ 865 "setenv fdtaddr 0x00c00000;" \ 866 "setenv loadaddr 0x1000000;" \ 867 "bootm $loadaddr $ramdiskaddr $fdtaddr" 868 869 #define CONFIG_HDBOOT \ 870 "setenv bootargs root=/dev/$bdev rw " \ 871 "console=$consoledev,$baudrate $othbootargs;" \ 872 "tftp $loadaddr $bootfile;" \ 873 "tftp $fdtaddr $fdtfile;" \ 874 "bootm $loadaddr - $fdtaddr" 875 876 #define CONFIG_NFSBOOTCOMMAND \ 877 "setenv bootargs root=/dev/nfs rw " \ 878 "nfsroot=$serverip:$rootpath " \ 879 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 880 "console=$consoledev,$baudrate $othbootargs;" \ 881 "tftp $loadaddr $bootfile;" \ 882 "tftp $fdtaddr $fdtfile;" \ 883 "bootm $loadaddr - $fdtaddr" 884 885 #define CONFIG_RAMBOOTCOMMAND \ 886 "setenv bootargs root=/dev/ram rw " \ 887 "console=$consoledev,$baudrate $othbootargs;" \ 888 "tftp $ramdiskaddr $ramdiskfile;" \ 889 "tftp $loadaddr $bootfile;" \ 890 "tftp $fdtaddr $fdtfile;" \ 891 "bootm $loadaddr $ramdiskaddr $fdtaddr" 892 893 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 894 895 #include <asm/fsl_secure_boot.h> 896 897 #endif /* __T208xQDS_H */ 898