1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_USB_EHCI 16 #if defined(CONFIG_ARCH_T2080) 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 19 #define CONFIG_SRIO1 /* SRIO port 1 */ 20 #define CONFIG_SRIO2 /* SRIO port 2 */ 21 #elif defined(CONFIG_ARCH_T2081) 22 #endif 23 24 /* High Level Configuration Options */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 36 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 37 #define CONFIG_ENV_OVERWRITE 38 39 #ifdef CONFIG_RAMBOOT_PBL 40 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 41 42 #define CONFIG_SPL_FLUSH_IMAGE 43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 44 #define CONFIG_SYS_TEXT_BASE 0x00201000 45 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 46 #define CONFIG_SPL_PAD_TO 0x40000 47 #define CONFIG_SPL_MAX_SIZE 0x28000 48 #define RESET_VECTOR_OFFSET 0x27FFC 49 #define BOOT_PAGE_OFFSET 0x27000 50 #ifdef CONFIG_SPL_BUILD 51 #define CONFIG_SPL_SKIP_RELOCATE 52 #define CONFIG_SPL_COMMON_INIT_DDR 53 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 54 #define CONFIG_SYS_NO_FLASH 55 #endif 56 57 #ifdef CONFIG_NAND 58 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 59 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 60 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 61 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 62 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 63 #if defined(CONFIG_ARCH_T2080) 64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 65 #elif defined(CONFIG_ARCH_T2081) 66 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 67 #endif 68 #define CONFIG_SPL_NAND_BOOT 69 #endif 70 71 #ifdef CONFIG_SPIFLASH 72 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 73 #define CONFIG_SPL_SPI_FLASH_MINIMAL 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 76 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 78 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 79 #ifndef CONFIG_SPL_BUILD 80 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 81 #endif 82 #if defined(CONFIG_ARCH_T2080) 83 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 84 #elif defined(CONFIG_ARCH_T2081) 85 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 86 #endif 87 #define CONFIG_SPL_SPI_BOOT 88 #endif 89 90 #ifdef CONFIG_SDCARD 91 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 92 #define CONFIG_SPL_MMC_MINIMAL 93 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 94 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 95 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 96 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 97 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 98 #ifndef CONFIG_SPL_BUILD 99 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 100 #endif 101 #if defined(CONFIG_ARCH_T2080) 102 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 103 #elif defined(CONFIG_ARCH_T2081) 104 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 105 #endif 106 #define CONFIG_SPL_MMC_BOOT 107 #endif 108 109 #endif /* CONFIG_RAMBOOT_PBL */ 110 111 #define CONFIG_SRIO_PCIE_BOOT_MASTER 112 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 113 /* Set 1M boot space */ 114 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 115 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 116 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 117 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 118 #define CONFIG_SYS_NO_FLASH 119 #endif 120 121 #ifndef CONFIG_SYS_TEXT_BASE 122 #define CONFIG_SYS_TEXT_BASE 0xeff40000 123 #endif 124 125 #ifndef CONFIG_RESET_VECTOR_ADDRESS 126 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 127 #endif 128 129 /* 130 * These can be toggled for performance analysis, otherwise use default. 131 */ 132 #define CONFIG_SYS_CACHE_STASHING 133 #define CONFIG_BTB /* toggle branch predition */ 134 #define CONFIG_DDR_ECC 135 #ifdef CONFIG_DDR_ECC 136 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 137 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 138 #endif 139 140 #ifndef CONFIG_SYS_NO_FLASH 141 #define CONFIG_FLASH_CFI_DRIVER 142 #define CONFIG_SYS_FLASH_CFI 143 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 144 #endif 145 146 #if defined(CONFIG_SPIFLASH) 147 #define CONFIG_SYS_EXTRA_ENV_RELOC 148 #define CONFIG_ENV_IS_IN_SPI_FLASH 149 #define CONFIG_ENV_SPI_BUS 0 150 #define CONFIG_ENV_SPI_CS 0 151 #define CONFIG_ENV_SPI_MAX_HZ 10000000 152 #define CONFIG_ENV_SPI_MODE 0 153 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 154 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 155 #define CONFIG_ENV_SECT_SIZE 0x10000 156 #elif defined(CONFIG_SDCARD) 157 #define CONFIG_SYS_EXTRA_ENV_RELOC 158 #define CONFIG_ENV_IS_IN_MMC 159 #define CONFIG_SYS_MMC_ENV_DEV 0 160 #define CONFIG_ENV_SIZE 0x2000 161 #define CONFIG_ENV_OFFSET (512 * 0x800) 162 #elif defined(CONFIG_NAND) 163 #define CONFIG_SYS_EXTRA_ENV_RELOC 164 #define CONFIG_ENV_IS_IN_NAND 165 #define CONFIG_ENV_SIZE 0x2000 166 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 167 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 168 #define CONFIG_ENV_IS_IN_REMOTE 169 #define CONFIG_ENV_ADDR 0xffe20000 170 #define CONFIG_ENV_SIZE 0x2000 171 #elif defined(CONFIG_ENV_IS_NOWHERE) 172 #define CONFIG_ENV_SIZE 0x2000 173 #else 174 #define CONFIG_ENV_IS_IN_FLASH 175 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 176 #define CONFIG_ENV_SIZE 0x2000 177 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 178 #endif 179 180 #ifndef __ASSEMBLY__ 181 unsigned long get_board_sys_clk(void); 182 unsigned long get_board_ddr_clk(void); 183 #endif 184 185 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 186 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 187 188 /* 189 * Config the L3 Cache as L3 SRAM 190 */ 191 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 192 #define CONFIG_SYS_L3_SIZE (512 << 10) 193 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 194 #ifdef CONFIG_RAMBOOT_PBL 195 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 196 #endif 197 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 198 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 199 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 200 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 201 202 #define CONFIG_SYS_DCSRBAR 0xf0000000 203 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 204 205 /* EEPROM */ 206 #define CONFIG_ID_EEPROM 207 #define CONFIG_SYS_I2C_EEPROM_NXID 208 #define CONFIG_SYS_EEPROM_BUS_NUM 0 209 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 210 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 211 212 /* 213 * DDR Setup 214 */ 215 #define CONFIG_VERY_BIG_RAM 216 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 217 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 218 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 219 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 220 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 221 #define CONFIG_DDR_SPD 222 #define CONFIG_FSL_DDR_INTERACTIVE 223 #define CONFIG_SYS_SPD_BUS_NUM 0 224 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 225 #define SPD_EEPROM_ADDRESS1 0x51 226 #define SPD_EEPROM_ADDRESS2 0x52 227 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 228 #define CTRL_INTLV_PREFERED cacheline 229 230 /* 231 * IFC Definitions 232 */ 233 #define CONFIG_SYS_FLASH_BASE 0xe0000000 234 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 235 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 236 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 237 + 0x8000000) | \ 238 CSPR_PORT_SIZE_16 | \ 239 CSPR_MSEL_NOR | \ 240 CSPR_V) 241 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 242 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 243 CSPR_PORT_SIZE_16 | \ 244 CSPR_MSEL_NOR | \ 245 CSPR_V) 246 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 247 /* NOR Flash Timing Params */ 248 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 249 250 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 251 FTIM0_NOR_TEADC(0x5) | \ 252 FTIM0_NOR_TEAHC(0x5)) 253 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 254 FTIM1_NOR_TRAD_NOR(0x1A) |\ 255 FTIM1_NOR_TSEQRAD_NOR(0x13)) 256 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 257 FTIM2_NOR_TCH(0x4) | \ 258 FTIM2_NOR_TWPH(0x0E) | \ 259 FTIM2_NOR_TWP(0x1c)) 260 #define CONFIG_SYS_NOR_FTIM3 0x0 261 262 #define CONFIG_SYS_FLASH_QUIET_TEST 263 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 264 265 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 266 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 267 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 268 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 269 270 #define CONFIG_SYS_FLASH_EMPTY_INFO 271 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 272 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 273 274 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 275 #define QIXIS_BASE 0xffdf0000 276 #define QIXIS_LBMAP_SWITCH 6 277 #define QIXIS_LBMAP_MASK 0x0f 278 #define QIXIS_LBMAP_SHIFT 0 279 #define QIXIS_LBMAP_DFLTBANK 0x00 280 #define QIXIS_LBMAP_ALTBANK 0x04 281 #define QIXIS_LBMAP_NAND 0x09 282 #define QIXIS_LBMAP_SD 0x00 283 #define QIXIS_RCW_SRC_NAND 0x104 284 #define QIXIS_RCW_SRC_SD 0x040 285 #define QIXIS_RST_CTL_RESET 0x83 286 #define QIXIS_RST_FORCE_MEM 0x1 287 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 288 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 289 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 290 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 291 292 #define CONFIG_SYS_CSPR3_EXT (0xf) 293 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 294 | CSPR_PORT_SIZE_8 \ 295 | CSPR_MSEL_GPCM \ 296 | CSPR_V) 297 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 298 #define CONFIG_SYS_CSOR3 0x0 299 /* QIXIS Timing parameters for IFC CS3 */ 300 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 301 FTIM0_GPCM_TEADC(0x0e) | \ 302 FTIM0_GPCM_TEAHC(0x0e)) 303 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 304 FTIM1_GPCM_TRAD(0x3f)) 305 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 306 FTIM2_GPCM_TCH(0x8) | \ 307 FTIM2_GPCM_TWP(0x1f)) 308 #define CONFIG_SYS_CS3_FTIM3 0x0 309 310 /* NAND Flash on IFC */ 311 #define CONFIG_NAND_FSL_IFC 312 #define CONFIG_SYS_NAND_BASE 0xff800000 313 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 314 315 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 316 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 317 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 318 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 319 | CSPR_V) 320 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 321 322 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 323 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 324 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 325 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 326 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 327 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 328 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 329 330 #define CONFIG_SYS_NAND_ONFI_DETECTION 331 332 /* ONFI NAND Flash mode0 Timing Params */ 333 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 334 FTIM0_NAND_TWP(0x18) | \ 335 FTIM0_NAND_TWCHT(0x07) | \ 336 FTIM0_NAND_TWH(0x0a)) 337 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 338 FTIM1_NAND_TWBE(0x39) | \ 339 FTIM1_NAND_TRR(0x0e) | \ 340 FTIM1_NAND_TRP(0x18)) 341 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 342 FTIM2_NAND_TREH(0x0a) | \ 343 FTIM2_NAND_TWHRE(0x1e)) 344 #define CONFIG_SYS_NAND_FTIM3 0x0 345 346 #define CONFIG_SYS_NAND_DDR_LAW 11 347 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 348 #define CONFIG_SYS_MAX_NAND_DEVICE 1 349 #define CONFIG_CMD_NAND 350 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 351 352 #if defined(CONFIG_NAND) 353 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 354 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 355 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 356 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 357 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 358 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 359 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 360 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 361 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 362 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 363 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 364 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 365 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 366 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 367 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 368 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 369 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 370 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 371 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 372 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 373 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 374 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 375 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 376 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 377 #else 378 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 379 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 380 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 381 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 382 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 383 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 384 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 385 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 386 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 387 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 388 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 389 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 390 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 391 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 392 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 393 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 394 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 395 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 396 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 397 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 398 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 399 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 400 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 401 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 402 #endif 403 404 #if defined(CONFIG_RAMBOOT_PBL) 405 #define CONFIG_SYS_RAMBOOT 406 #endif 407 408 #ifdef CONFIG_SPL_BUILD 409 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 410 #else 411 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 412 #endif 413 414 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 415 #define CONFIG_MISC_INIT_R 416 #define CONFIG_HWCONFIG 417 418 /* define to use L1 as initial stack */ 419 #define CONFIG_L1_INIT_RAM 420 #define CONFIG_SYS_INIT_RAM_LOCK 421 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 424 /* The assembler doesn't like typecast */ 425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 426 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 427 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 428 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 429 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 430 GENERATED_GBL_DATA_SIZE) 431 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 432 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 433 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 434 435 /* 436 * Serial Port 437 */ 438 #define CONFIG_CONS_INDEX 1 439 #define CONFIG_SYS_NS16550_SERIAL 440 #define CONFIG_SYS_NS16550_REG_SIZE 1 441 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 442 #define CONFIG_SYS_BAUDRATE_TABLE \ 443 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 444 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 445 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 446 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 447 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 448 449 /* 450 * I2C 451 */ 452 #define CONFIG_SYS_I2C 453 #define CONFIG_SYS_I2C_FSL 454 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 455 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 456 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 457 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 458 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 459 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 460 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 461 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 462 #define CONFIG_SYS_FSL_I2C_SPEED 100000 463 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 464 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 465 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 466 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 467 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 468 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 469 #define I2C_MUX_CH_DEFAULT 0x8 470 471 #define I2C_MUX_CH_VOL_MONITOR 0xa 472 473 /* Voltage monitor on channel 2*/ 474 #define I2C_VOL_MONITOR_ADDR 0x40 475 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 476 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 477 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 478 479 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 480 #ifndef CONFIG_SPL_BUILD 481 #define CONFIG_VID 482 #endif 483 #define CONFIG_VOL_MONITOR_IR36021_SET 484 #define CONFIG_VOL_MONITOR_IR36021_READ 485 /* The lowest and highest voltage allowed for T208xQDS */ 486 #define VDD_MV_MIN 819 487 #define VDD_MV_MAX 1212 488 489 /* 490 * RapidIO 491 */ 492 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 493 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 494 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 495 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 496 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 497 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 498 /* 499 * for slave u-boot IMAGE instored in master memory space, 500 * PHYS must be aligned based on the SIZE 501 */ 502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 504 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 505 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 506 /* 507 * for slave UCODE and ENV instored in master memory space, 508 * PHYS must be aligned based on the SIZE 509 */ 510 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 511 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 512 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 513 514 /* slave core release by master*/ 515 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 516 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 517 518 /* 519 * SRIO_PCIE_BOOT - SLAVE 520 */ 521 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 522 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 523 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 524 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 525 #endif 526 527 /* 528 * eSPI - Enhanced SPI 529 */ 530 #ifdef CONFIG_SPI_FLASH 531 #ifndef CONFIG_SPL_BUILD 532 #endif 533 534 #define CONFIG_SPI_FLASH_BAR 535 #define CONFIG_SF_DEFAULT_SPEED 10000000 536 #define CONFIG_SF_DEFAULT_MODE 0 537 #endif 538 539 /* 540 * General PCI 541 * Memory space is mapped 1-1, but I/O space must start from 0. 542 */ 543 #define CONFIG_PCIE1 /* PCIE controller 1 */ 544 #define CONFIG_PCIE2 /* PCIE controller 2 */ 545 #define CONFIG_PCIE3 /* PCIE controller 3 */ 546 #define CONFIG_PCIE4 /* PCIE controller 4 */ 547 #define CONFIG_FSL_PCIE_RESET 548 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 549 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 550 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 551 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 552 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 553 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 554 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 555 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 556 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 557 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 558 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 559 560 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 561 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 562 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 563 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 564 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 565 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 566 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 567 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 568 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 569 570 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 571 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 572 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 573 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 574 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 575 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 576 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 577 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 578 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 579 580 /* controller 4, Base address 203000 */ 581 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 582 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 583 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 584 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 585 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 586 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 587 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 588 589 #ifdef CONFIG_PCI 590 #define CONFIG_PCI_INDIRECT_BRIDGE 591 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 592 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 593 #endif 594 595 /* Qman/Bman */ 596 #ifndef CONFIG_NOBQFMAN 597 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 598 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 599 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 600 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 601 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 602 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 603 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 604 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 605 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 606 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 607 CONFIG_SYS_BMAN_CENA_SIZE) 608 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 609 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 610 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 611 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 612 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 613 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 614 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 615 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 616 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 617 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 618 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 619 CONFIG_SYS_QMAN_CENA_SIZE) 620 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 621 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 622 623 #define CONFIG_SYS_DPAA_FMAN 624 #define CONFIG_SYS_DPAA_PME 625 #define CONFIG_SYS_PMAN 626 #define CONFIG_SYS_DPAA_DCE 627 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 628 #define CONFIG_SYS_INTERLAKEN 629 630 /* Default address of microcode for the Linux Fman driver */ 631 #if defined(CONFIG_SPIFLASH) 632 /* 633 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 634 * env, so we got 0x110000. 635 */ 636 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 637 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 638 #elif defined(CONFIG_SDCARD) 639 /* 640 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 641 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 642 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 643 */ 644 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 645 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 646 #elif defined(CONFIG_NAND) 647 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 648 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 649 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 650 /* 651 * Slave has no ucode locally, it can fetch this from remote. When implementing 652 * in two corenet boards, slave's ucode could be stored in master's memory 653 * space, the address can be mapped from slave TLB->slave LAW-> 654 * slave SRIO or PCIE outbound window->master inbound window-> 655 * master LAW->the ucode address in master's memory space. 656 */ 657 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 658 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 659 #else 660 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 661 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 662 #endif 663 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 664 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 665 #endif /* CONFIG_NOBQFMAN */ 666 667 #ifdef CONFIG_SYS_DPAA_FMAN 668 #define CONFIG_FMAN_ENET 669 #define CONFIG_PHYLIB_10G 670 #define CONFIG_PHY_VITESSE 671 #define CONFIG_PHY_REALTEK 672 #define CONFIG_PHY_TERANETICS 673 #define RGMII_PHY1_ADDR 0x1 674 #define RGMII_PHY2_ADDR 0x2 675 #define FM1_10GEC1_PHY_ADDR 0x3 676 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 677 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 678 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 679 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 680 #endif 681 682 #ifdef CONFIG_FMAN_ENET 683 #define CONFIG_MII /* MII PHY management */ 684 #define CONFIG_ETHPRIME "FM1@DTSEC3" 685 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 686 #endif 687 688 /* 689 * SATA 690 */ 691 #ifdef CONFIG_FSL_SATA_V2 692 #define CONFIG_LIBATA 693 #define CONFIG_FSL_SATA 694 #define CONFIG_SYS_SATA_MAX_DEVICE 2 695 #define CONFIG_SATA1 696 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 697 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 698 #define CONFIG_SATA2 699 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 700 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 701 #define CONFIG_LBA48 702 #define CONFIG_CMD_SATA 703 #endif 704 705 /* 706 * USB 707 */ 708 #ifdef CONFIG_USB_EHCI 709 #define CONFIG_USB_EHCI_FSL 710 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 711 #define CONFIG_HAS_FSL_DR_USB 712 #endif 713 714 /* 715 * SDHC 716 */ 717 #ifdef CONFIG_MMC 718 #define CONFIG_FSL_ESDHC 719 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 720 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 721 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 722 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 723 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 724 #endif 725 726 /* 727 * Dynamic MTD Partition support with mtdparts 728 */ 729 #ifndef CONFIG_SYS_NO_FLASH 730 #define CONFIG_MTD_DEVICE 731 #define CONFIG_MTD_PARTITIONS 732 #define CONFIG_CMD_MTDPARTS 733 #define CONFIG_FLASH_CFI_MTD 734 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 735 "spi0=spife110000.0" 736 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 737 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 738 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 739 "1m(uboot),5m(kernel),128k(dtb),-(user)" 740 #endif 741 742 /* 743 * Environment 744 */ 745 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 746 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 747 748 /* 749 * Command line configuration. 750 */ 751 #define CONFIG_CMD_ERRATA 752 #define CONFIG_CMD_IRQ 753 #define CONFIG_CMD_REGINFO 754 755 #ifdef CONFIG_PCI 756 #define CONFIG_CMD_PCI 757 #endif 758 759 /* Hash command with SHA acceleration supported in hardware */ 760 #ifdef CONFIG_FSL_CAAM 761 #define CONFIG_CMD_HASH 762 #define CONFIG_SHA_HW_ACCEL 763 #endif 764 765 /* 766 * Miscellaneous configurable options 767 */ 768 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 769 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 770 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 771 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 772 #ifdef CONFIG_CMD_KGDB 773 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 774 #else 775 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 776 #endif 777 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 778 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 779 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 780 781 /* 782 * For booting Linux, the board info and command line data 783 * have to be in the first 64 MB of memory, since this is 784 * the maximum mapped by the Linux kernel during initialization. 785 */ 786 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 787 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 788 789 #ifdef CONFIG_CMD_KGDB 790 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 791 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 792 #endif 793 794 /* 795 * Environment Configuration 796 */ 797 #define CONFIG_ROOTPATH "/opt/nfsroot" 798 #define CONFIG_BOOTFILE "uImage" 799 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 800 801 /* default location for tftp and bootm */ 802 #define CONFIG_LOADADDR 1000000 803 #define CONFIG_BAUDRATE 115200 804 #define __USB_PHY_TYPE utmi 805 806 #define CONFIG_EXTRA_ENV_SETTINGS \ 807 "hwconfig=fsl_ddr:" \ 808 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 809 "bank_intlv=auto;" \ 810 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 811 "netdev=eth0\0" \ 812 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 813 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 814 "tftpflash=tftpboot $loadaddr $uboot && " \ 815 "protect off $ubootaddr +$filesize && " \ 816 "erase $ubootaddr +$filesize && " \ 817 "cp.b $loadaddr $ubootaddr $filesize && " \ 818 "protect on $ubootaddr +$filesize && " \ 819 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 820 "consoledev=ttyS0\0" \ 821 "ramdiskaddr=2000000\0" \ 822 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 823 "fdtaddr=1e00000\0" \ 824 "fdtfile=t2080qds/t2080qds.dtb\0" \ 825 "bdev=sda3\0" 826 827 /* 828 * For emulation this causes u-boot to jump to the start of the 829 * proof point app code automatically 830 */ 831 #define CONFIG_PROOF_POINTS \ 832 "setenv bootargs root=/dev/$bdev rw " \ 833 "console=$consoledev,$baudrate $othbootargs;" \ 834 "cpu 1 release 0x29000000 - - -;" \ 835 "cpu 2 release 0x29000000 - - -;" \ 836 "cpu 3 release 0x29000000 - - -;" \ 837 "cpu 4 release 0x29000000 - - -;" \ 838 "cpu 5 release 0x29000000 - - -;" \ 839 "cpu 6 release 0x29000000 - - -;" \ 840 "cpu 7 release 0x29000000 - - -;" \ 841 "go 0x29000000" 842 843 #define CONFIG_HVBOOT \ 844 "setenv bootargs config-addr=0x60000000; " \ 845 "bootm 0x01000000 - 0x00f00000" 846 847 #define CONFIG_ALU \ 848 "setenv bootargs root=/dev/$bdev rw " \ 849 "console=$consoledev,$baudrate $othbootargs;" \ 850 "cpu 1 release 0x01000000 - - -;" \ 851 "cpu 2 release 0x01000000 - - -;" \ 852 "cpu 3 release 0x01000000 - - -;" \ 853 "cpu 4 release 0x01000000 - - -;" \ 854 "cpu 5 release 0x01000000 - - -;" \ 855 "cpu 6 release 0x01000000 - - -;" \ 856 "cpu 7 release 0x01000000 - - -;" \ 857 "go 0x01000000" 858 859 #define CONFIG_LINUX \ 860 "setenv bootargs root=/dev/ram rw " \ 861 "console=$consoledev,$baudrate $othbootargs;" \ 862 "setenv ramdiskaddr 0x02000000;" \ 863 "setenv fdtaddr 0x00c00000;" \ 864 "setenv loadaddr 0x1000000;" \ 865 "bootm $loadaddr $ramdiskaddr $fdtaddr" 866 867 #define CONFIG_HDBOOT \ 868 "setenv bootargs root=/dev/$bdev rw " \ 869 "console=$consoledev,$baudrate $othbootargs;" \ 870 "tftp $loadaddr $bootfile;" \ 871 "tftp $fdtaddr $fdtfile;" \ 872 "bootm $loadaddr - $fdtaddr" 873 874 #define CONFIG_NFSBOOTCOMMAND \ 875 "setenv bootargs root=/dev/nfs rw " \ 876 "nfsroot=$serverip:$rootpath " \ 877 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 878 "console=$consoledev,$baudrate $othbootargs;" \ 879 "tftp $loadaddr $bootfile;" \ 880 "tftp $fdtaddr $fdtfile;" \ 881 "bootm $loadaddr - $fdtaddr" 882 883 #define CONFIG_RAMBOOTCOMMAND \ 884 "setenv bootargs root=/dev/ram rw " \ 885 "console=$consoledev,$baudrate $othbootargs;" \ 886 "tftp $ramdiskaddr $ramdiskfile;" \ 887 "tftp $loadaddr $bootfile;" \ 888 "tftp $fdtaddr $fdtfile;" \ 889 "bootm $loadaddr $ramdiskaddr $fdtaddr" 890 891 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 892 893 #include <asm/fsl_secure_boot.h> 894 895 #endif /* __T208xQDS_H */ 896