xref: /openbmc/u-boot/include/configs/T208xQDS.h (revision 9f074e67)
1 /*
2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 /*
8  * T2080/T2081 QDS board configuration file
9  */
10 
11 #ifndef __T208xQDS_H
12 #define __T208xQDS_H
13 
14 #define CONFIG_SYS_GENERIC_BOARD
15 #define CONFIG_DISPLAY_BOARDINFO
16 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
17 #define CONFIG_MMC
18 #define CONFIG_SPI_FLASH
19 #define CONFIG_USB_EHCI
20 #if defined(CONFIG_PPC_T2080)
21 #define CONFIG_T2080QDS
22 #define CONFIG_FSL_SATA_V2
23 #define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
24 #define CONFIG_SRIO1		/* SRIO port 1 */
25 #define CONFIG_SRIO2		/* SRIO port 2 */
26 #elif defined(CONFIG_PPC_T2081)
27 #define CONFIG_T2081QDS
28 #endif
29 
30 /* High Level Configuration Options */
31 #define CONFIG_PHYS_64BIT
32 #define CONFIG_BOOKE
33 #define CONFIG_E500		/* BOOKE e500 family */
34 #define CONFIG_E500MC		/* BOOKE e500mc family */
35 #define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
36 #define CONFIG_MP		/* support multiple processors */
37 #define CONFIG_ENABLE_36BIT_PHYS
38 
39 #ifdef CONFIG_PHYS_64BIT
40 #define CONFIG_ADDR_MAP 1
41 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
42 #endif
43 
44 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
45 #define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
46 #define CONFIG_FSL_IFC		/* Enable IFC Support */
47 #define CONFIG_FSL_CAAM		/* Enable SEC/CAAM */
48 #define CONFIG_FSL_LAW		/* Use common FSL init code */
49 #define CONFIG_ENV_OVERWRITE
50 
51 #ifdef CONFIG_RAMBOOT_PBL
52 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
53 #if defined(CONFIG_PPC_T2080)
54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
55 #elif defined(CONFIG_PPC_T2081)
56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
57 #endif
58 
59 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
60 #define CONFIG_SPL_ENV_SUPPORT
61 #define CONFIG_SPL_SERIAL_SUPPORT
62 #define CONFIG_SPL_FLUSH_IMAGE
63 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
64 #define CONFIG_SPL_LIBGENERIC_SUPPORT
65 #define CONFIG_SPL_LIBCOMMON_SUPPORT
66 #define CONFIG_SPL_I2C_SUPPORT
67 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
68 #define CONFIG_FSL_LAW			/* Use common FSL init code */
69 #define CONFIG_SYS_TEXT_BASE		0x00201000
70 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
71 #define CONFIG_SPL_PAD_TO		0x40000
72 #define CONFIG_SPL_MAX_SIZE		0x28000
73 #define RESET_VECTOR_OFFSET		0x27FFC
74 #define BOOT_PAGE_OFFSET		0x27000
75 #ifdef CONFIG_SPL_BUILD
76 #define CONFIG_SPL_SKIP_RELOCATE
77 #define CONFIG_SPL_COMMON_INIT_DDR
78 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
79 #define CONFIG_SYS_NO_FLASH
80 #endif
81 
82 #ifdef CONFIG_NAND
83 #define CONFIG_SPL_NAND_SUPPORT
84 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
85 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
86 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
87 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
88 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
89 #define CONFIG_SPL_NAND_BOOT
90 #endif
91 
92 #ifdef CONFIG_SPIFLASH
93 #define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
94 #define CONFIG_SPL_SPI_SUPPORT
95 #define CONFIG_SPL_SPI_FLASH_SUPPORT
96 #define CONFIG_SPL_SPI_FLASH_MINIMAL
97 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
98 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
99 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
100 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
101 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
102 #ifndef CONFIG_SPL_BUILD
103 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
104 #endif
105 #define CONFIG_SPL_SPI_BOOT
106 #endif
107 
108 #ifdef CONFIG_SDCARD
109 #define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
110 #define CONFIG_SPL_MMC_SUPPORT
111 #define CONFIG_SPL_MMC_MINIMAL
112 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
113 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
114 #define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
115 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
116 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
117 #ifndef CONFIG_SPL_BUILD
118 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
119 #endif
120 #define CONFIG_SPL_MMC_BOOT
121 #endif
122 
123 #endif /* CONFIG_RAMBOOT_PBL */
124 
125 #define CONFIG_SRIO_PCIE_BOOT_MASTER
126 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
127 /* Set 1M boot space */
128 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
129 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
130 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
131 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
132 #define CONFIG_SYS_NO_FLASH
133 #endif
134 
135 #ifndef CONFIG_SYS_TEXT_BASE
136 #define CONFIG_SYS_TEXT_BASE	0xeff40000
137 #endif
138 
139 #ifndef CONFIG_RESET_VECTOR_ADDRESS
140 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
141 #endif
142 
143 /*
144  * These can be toggled for performance analysis, otherwise use default.
145  */
146 #define CONFIG_SYS_CACHE_STASHING
147 #define CONFIG_BTB		/* toggle branch predition */
148 #define CONFIG_DDR_ECC
149 #ifdef CONFIG_DDR_ECC
150 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
151 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
152 #endif
153 
154 #ifndef CONFIG_SYS_NO_FLASH
155 #define CONFIG_FLASH_CFI_DRIVER
156 #define CONFIG_SYS_FLASH_CFI
157 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
158 #endif
159 
160 #if defined(CONFIG_SPIFLASH)
161 #define CONFIG_SYS_EXTRA_ENV_RELOC
162 #define CONFIG_ENV_IS_IN_SPI_FLASH
163 #define CONFIG_ENV_SPI_BUS	0
164 #define CONFIG_ENV_SPI_CS	0
165 #define CONFIG_ENV_SPI_MAX_HZ	10000000
166 #define CONFIG_ENV_SPI_MODE	0
167 #define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
168 #define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
169 #define CONFIG_ENV_SECT_SIZE	0x10000
170 #elif defined(CONFIG_SDCARD)
171 #define CONFIG_SYS_EXTRA_ENV_RELOC
172 #define CONFIG_ENV_IS_IN_MMC
173 #define CONFIG_SYS_MMC_ENV_DEV	0
174 #define CONFIG_ENV_SIZE		0x2000
175 #define CONFIG_ENV_OFFSET	(512 * 0x800)
176 #elif defined(CONFIG_NAND)
177 #define CONFIG_SYS_EXTRA_ENV_RELOC
178 #define CONFIG_ENV_IS_IN_NAND
179 #define CONFIG_ENV_SIZE		0x2000
180 #define CONFIG_ENV_OFFSET	(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
181 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
182 #define CONFIG_ENV_IS_IN_REMOTE
183 #define CONFIG_ENV_ADDR		0xffe20000
184 #define CONFIG_ENV_SIZE		0x2000
185 #elif defined(CONFIG_ENV_IS_NOWHERE)
186 #define CONFIG_ENV_SIZE		0x2000
187 #else
188 #define CONFIG_ENV_IS_IN_FLASH
189 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
190 #define CONFIG_ENV_SIZE		0x2000
191 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
192 #endif
193 
194 #ifndef __ASSEMBLY__
195 unsigned long get_board_sys_clk(void);
196 unsigned long get_board_ddr_clk(void);
197 #endif
198 
199 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
200 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
201 
202 /*
203  * Config the L3 Cache as L3 SRAM
204  */
205 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
206 #define CONFIG_SYS_L3_SIZE		(512 << 10)
207 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
208 #ifdef CONFIG_RAMBOOT_PBL
209 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
210 #endif
211 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
212 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
213 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
214 #define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
215 
216 #define CONFIG_SYS_DCSRBAR	0xf0000000
217 #define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
218 
219 /* EEPROM */
220 #define CONFIG_ID_EEPROM
221 #define CONFIG_SYS_I2C_EEPROM_NXID
222 #define CONFIG_SYS_EEPROM_BUS_NUM	0
223 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
224 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
225 
226 /*
227  * DDR Setup
228  */
229 #define CONFIG_VERY_BIG_RAM
230 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
231 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
232 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
233 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
234 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
235 #define CONFIG_DDR_SPD
236 #define CONFIG_SYS_FSL_DDR3
237 #define CONFIG_FSL_DDR_INTERACTIVE
238 #define CONFIG_SYS_SPD_BUS_NUM	0
239 #define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
240 #define SPD_EEPROM_ADDRESS1	0x51
241 #define SPD_EEPROM_ADDRESS2	0x52
242 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
243 #define CTRL_INTLV_PREFERED	cacheline
244 
245 /*
246  * IFC Definitions
247  */
248 #define CONFIG_SYS_FLASH_BASE		0xe0000000
249 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
250 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
251 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
252 				+ 0x8000000) | \
253 				CSPR_PORT_SIZE_16 | \
254 				CSPR_MSEL_NOR | \
255 				CSPR_V)
256 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
257 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
258 				CSPR_PORT_SIZE_16 | \
259 				CSPR_MSEL_NOR | \
260 				CSPR_V)
261 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
262 /* NOR Flash Timing Params */
263 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
264 
265 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
266 				FTIM0_NOR_TEADC(0x5) | \
267 				FTIM0_NOR_TEAHC(0x5))
268 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
269 				FTIM1_NOR_TRAD_NOR(0x1A) |\
270 				FTIM1_NOR_TSEQRAD_NOR(0x13))
271 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
272 				FTIM2_NOR_TCH(0x4) | \
273 				FTIM2_NOR_TWPH(0x0E) | \
274 				FTIM2_NOR_TWP(0x1c))
275 #define CONFIG_SYS_NOR_FTIM3	0x0
276 
277 #define CONFIG_SYS_FLASH_QUIET_TEST
278 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
279 
280 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
281 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
282 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
283 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
284 
285 #define CONFIG_SYS_FLASH_EMPTY_INFO
286 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
287 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
288 
289 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
290 #define QIXIS_BASE			0xffdf0000
291 #define QIXIS_LBMAP_SWITCH		6
292 #define QIXIS_LBMAP_MASK		0x0f
293 #define QIXIS_LBMAP_SHIFT		0
294 #define QIXIS_LBMAP_DFLTBANK		0x00
295 #define QIXIS_LBMAP_ALTBANK		0x04
296 #define QIXIS_RST_CTL_RESET		0x83
297 #define QIXIS_RST_FORCE_MEM		0x1
298 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
299 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
300 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
301 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
302 
303 #define CONFIG_SYS_CSPR3_EXT	(0xf)
304 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
305 				| CSPR_PORT_SIZE_8 \
306 				| CSPR_MSEL_GPCM \
307 				| CSPR_V)
308 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
309 #define CONFIG_SYS_CSOR3	0x0
310 /* QIXIS Timing parameters for IFC CS3 */
311 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
312 					FTIM0_GPCM_TEADC(0x0e) | \
313 					FTIM0_GPCM_TEAHC(0x0e))
314 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
315 					FTIM1_GPCM_TRAD(0x3f))
316 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
317 					FTIM2_GPCM_TCH(0x8) | \
318 					FTIM2_GPCM_TWP(0x1f))
319 #define CONFIG_SYS_CS3_FTIM3		0x0
320 
321 /* NAND Flash on IFC */
322 #define CONFIG_NAND_FSL_IFC
323 #define CONFIG_SYS_NAND_BASE		0xff800000
324 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
325 
326 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
327 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
328 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
329 				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
330 				| CSPR_V)
331 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
332 
333 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
334 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
335 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
336 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
337 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
338 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
339 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
340 
341 #define CONFIG_SYS_NAND_ONFI_DETECTION
342 
343 /* ONFI NAND Flash mode0 Timing Params */
344 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
345 					FTIM0_NAND_TWP(0x18)    | \
346 					FTIM0_NAND_TWCHT(0x07)  | \
347 					FTIM0_NAND_TWH(0x0a))
348 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
349 					FTIM1_NAND_TWBE(0x39)   | \
350 					FTIM1_NAND_TRR(0x0e)    | \
351 					FTIM1_NAND_TRP(0x18))
352 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
353 					FTIM2_NAND_TREH(0x0a)   | \
354 					FTIM2_NAND_TWHRE(0x1e))
355 #define CONFIG_SYS_NAND_FTIM3		0x0
356 
357 #define CONFIG_SYS_NAND_DDR_LAW		11
358 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
359 #define CONFIG_SYS_MAX_NAND_DEVICE	1
360 #define CONFIG_MTD_NAND_VERIFY_WRITE
361 #define CONFIG_CMD_NAND
362 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
363 
364 #if defined(CONFIG_NAND)
365 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
366 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
367 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
368 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
369 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
370 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
371 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
372 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
373 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
374 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
375 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
376 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
377 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
378 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
379 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
380 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
381 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
382 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
383 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
384 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
385 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
386 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
387 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
388 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
389 #else
390 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
391 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
392 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
393 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
394 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
395 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
396 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
397 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
398 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
399 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
400 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
401 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
402 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
403 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
404 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
405 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
406 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
407 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
408 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
409 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
410 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
411 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
412 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
413 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
414 #endif
415 
416 #if defined(CONFIG_RAMBOOT_PBL)
417 #define CONFIG_SYS_RAMBOOT
418 #endif
419 
420 #ifdef CONFIG_SPL_BUILD
421 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
422 #else
423 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
424 #endif
425 
426 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
427 #define CONFIG_MISC_INIT_R
428 #define CONFIG_HWCONFIG
429 
430 /* define to use L1 as initial stack */
431 #define CONFIG_L1_INIT_RAM
432 #define CONFIG_SYS_INIT_RAM_LOCK
433 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
436 /* The assembler doesn't like typecast */
437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
438 			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
439 			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
440 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
441 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
442 						GENERATED_GBL_DATA_SIZE)
443 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
444 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
445 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
446 
447 /*
448  * Serial Port
449  */
450 #define CONFIG_CONS_INDEX		1
451 #define CONFIG_SYS_NS16550
452 #define CONFIG_SYS_NS16550_SERIAL
453 #define CONFIG_SYS_NS16550_REG_SIZE	1
454 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
455 #define CONFIG_SYS_BAUDRATE_TABLE	\
456 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
457 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
458 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
459 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
460 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
461 
462 /* Use the HUSH parser */
463 #define CONFIG_SYS_HUSH_PARSER
464 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
465 
466 /* pass open firmware flat tree */
467 #define CONFIG_OF_LIBFDT
468 #define CONFIG_OF_BOARD_SETUP
469 #define CONFIG_OF_STDOUT_VIA_ALIAS
470 
471 /* new uImage format support */
472 #define CONFIG_FIT
473 #define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
474 
475 /*
476  * I2C
477  */
478 #define CONFIG_SYS_I2C
479 #define CONFIG_SYS_I2C_FSL
480 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
481 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
482 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
483 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
484 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
485 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
486 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
487 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
488 #define CONFIG_SYS_FSL_I2C_SPEED   100000
489 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
490 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
491 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
492 #define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
493 #define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
494 #define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
495 #define I2C_MUX_CH_DEFAULT	0x8
496 
497 
498 /*
499  * RapidIO
500  */
501 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
502 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
503 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
504 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
505 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
506 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
507 /*
508  * for slave u-boot IMAGE instored in master memory space,
509  * PHYS must be aligned based on the SIZE
510  */
511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
512 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
513 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
514 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
515 /*
516  * for slave UCODE and ENV instored in master memory space,
517  * PHYS must be aligned based on the SIZE
518  */
519 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
520 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
521 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
522 
523 /* slave core release by master*/
524 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
525 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
526 
527 /*
528  * SRIO_PCIE_BOOT - SLAVE
529  */
530 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
531 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
532 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
533 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
534 #endif
535 
536 /*
537  * eSPI - Enhanced SPI
538  */
539 #ifdef CONFIG_SPI_FLASH
540 #define CONFIG_FSL_ESPI
541 #define CONFIG_SPI_FLASH_STMICRO
542 #ifndef CONFIG_SPL_BUILD
543 #define CONFIG_SPI_FLASH_SST
544 #define CONFIG_SPI_FLASH_EON
545 #endif
546 
547 #define CONFIG_CMD_SF
548 #define CONFIG_SPI_FLASH_BAR
549 #define CONFIG_SF_DEFAULT_SPEED	 10000000
550 #define CONFIG_SF_DEFAULT_MODE	  0
551 #endif
552 
553 /*
554  * General PCI
555  * Memory space is mapped 1-1, but I/O space must start from 0.
556  */
557 #define CONFIG_PCI		/* Enable PCI/PCIE */
558 #define CONFIG_PCIE1		/* PCIE controler 1 */
559 #define CONFIG_PCIE2		/* PCIE controler 2 */
560 #define CONFIG_PCIE3		/* PCIE controler 3 */
561 #define CONFIG_PCIE4		/* PCIE controler 4 */
562 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
563 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
564 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
565 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
566 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
567 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
568 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
569 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
570 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
571 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
572 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
573 
574 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
575 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
576 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
577 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
578 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
579 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
580 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
581 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
582 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
583 
584 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
585 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
586 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
587 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
588 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
589 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
590 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
591 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
592 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
593 
594 /* controller 4, Base address 203000 */
595 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
596 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
597 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
598 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
599 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
600 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
601 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
602 
603 #ifdef CONFIG_PCI
604 #define CONFIG_PCI_INDIRECT_BRIDGE
605 #define CONFIG_FSL_PCIE_RESET	   /* need PCIe reset errata */
606 #define CONFIG_NET_MULTI
607 #define CONFIG_E1000
608 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
609 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
610 #define CONFIG_DOS_PARTITION
611 #endif
612 
613 /* Qman/Bman */
614 #ifndef CONFIG_NOBQFMAN
615 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
616 #define CONFIG_SYS_BMAN_NUM_PORTALS	18
617 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
618 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
619 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
620 #define CONFIG_SYS_QMAN_NUM_PORTALS	18
621 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
622 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
623 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
624 
625 #define CONFIG_SYS_DPAA_FMAN
626 #define CONFIG_SYS_DPAA_PME
627 #define CONFIG_SYS_PMAN
628 #define CONFIG_SYS_DPAA_DCE
629 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
630 #define CONFIG_SYS_INTERLAKEN
631 
632 /* Default address of microcode for the Linux Fman driver */
633 #if defined(CONFIG_SPIFLASH)
634 /*
635  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
636  * env, so we got 0x110000.
637  */
638 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
639 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
640 #elif defined(CONFIG_SDCARD)
641 /*
642  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
643  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
644  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
645  */
646 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
647 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
648 #elif defined(CONFIG_NAND)
649 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
650 #define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
651 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
652 /*
653  * Slave has no ucode locally, it can fetch this from remote. When implementing
654  * in two corenet boards, slave's ucode could be stored in master's memory
655  * space, the address can be mapped from slave TLB->slave LAW->
656  * slave SRIO or PCIE outbound window->master inbound window->
657  * master LAW->the ucode address in master's memory space.
658  */
659 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
660 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
661 #else
662 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
663 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
664 #endif
665 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
666 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
667 #endif /* CONFIG_NOBQFMAN */
668 
669 #ifdef CONFIG_SYS_DPAA_FMAN
670 #define CONFIG_FMAN_ENET
671 #define CONFIG_PHYLIB_10G
672 #define CONFIG_PHY_VITESSE
673 #define CONFIG_PHY_REALTEK
674 #define CONFIG_PHY_TERANETICS
675 #define RGMII_PHY1_ADDR	0x1
676 #define RGMII_PHY2_ADDR	0x2
677 #define FM1_10GEC1_PHY_ADDR	  0x3
678 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
679 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
680 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
681 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
682 #endif
683 
684 #ifdef CONFIG_FMAN_ENET
685 #define CONFIG_MII		/* MII PHY management */
686 #define CONFIG_ETHPRIME		"FM1@DTSEC3"
687 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
688 #endif
689 
690 /*
691  * SATA
692  */
693 #ifdef CONFIG_FSL_SATA_V2
694 #define CONFIG_LIBATA
695 #define CONFIG_FSL_SATA
696 #define CONFIG_SYS_SATA_MAX_DEVICE	2
697 #define CONFIG_SATA1
698 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
699 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
700 #define CONFIG_SATA2
701 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
702 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
703 #define CONFIG_LBA48
704 #define CONFIG_CMD_SATA
705 #define CONFIG_DOS_PARTITION
706 #define CONFIG_CMD_EXT2
707 #endif
708 
709 /*
710  * USB
711  */
712 #ifdef CONFIG_USB_EHCI
713 #define CONFIG_CMD_USB
714 #define CONFIG_USB_STORAGE
715 #define CONFIG_USB_EHCI_FSL
716 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
717 #define CONFIG_CMD_EXT2
718 #define CONFIG_HAS_FSL_DR_USB
719 #endif
720 
721 /*
722  * SDHC
723  */
724 #ifdef CONFIG_MMC
725 #define CONFIG_CMD_MMC
726 #define CONFIG_FSL_ESDHC
727 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
728 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
729 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
730 #define CONFIG_GENERIC_MMC
731 #define CONFIG_CMD_EXT2
732 #define CONFIG_CMD_FAT
733 #define CONFIG_DOS_PARTITION
734 #endif
735 
736 
737 /*
738  * Dynamic MTD Partition support with mtdparts
739  */
740 #ifndef CONFIG_SYS_NO_FLASH
741 #define CONFIG_MTD_DEVICE
742 #define CONFIG_MTD_PARTITIONS
743 #define CONFIG_CMD_MTDPARTS
744 #define CONFIG_FLASH_CFI_MTD
745 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
746 			"spi0=spife110000.0"
747 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
748 			"128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
749 			"5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
750 			"1m(uboot),5m(kernel),128k(dtb),-(user)"
751 #endif
752 
753 /*
754  * Environment
755  */
756 #define CONFIG_LOADS_ECHO	/* echo on for serial download */
757 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
758 
759 /*
760  * Command line configuration.
761  */
762 #include <config_cmd_default.h>
763 
764 #define CONFIG_CMD_DHCP
765 #define CONFIG_CMD_ELF
766 #define CONFIG_CMD_ERRATA
767 #define CONFIG_CMD_GREPENV
768 #define CONFIG_CMD_IRQ
769 #define CONFIG_CMD_I2C
770 #define CONFIG_CMD_MII
771 #define CONFIG_CMD_PING
772 #define CONFIG_CMD_SETEXPR
773 #define CONFIG_CMD_REGINFO
774 #define CONFIG_CMD_BDI
775 
776 #ifdef CONFIG_PCI
777 #define CONFIG_CMD_PCI
778 #define CONFIG_CMD_NET
779 #endif
780 
781 /* Hash command with SHA acceleration supported in hardware */
782 #ifdef CONFIG_FSL_CAAM
783 #define CONFIG_CMD_HASH
784 #define CONFIG_SHA_HW_ACCEL
785 #endif
786 
787 /*
788  * Miscellaneous configurable options
789  */
790 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
791 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
792 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
793 #define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
794 #ifdef CONFIG_CMD_KGDB
795 #define CONFIG_SYS_CBSIZE	1024	  /* Console I/O Buffer Size */
796 #else
797 #define CONFIG_SYS_CBSIZE	256	  /* Console I/O Buffer Size */
798 #endif
799 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
800 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
801 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
802 
803 /*
804  * For booting Linux, the board info and command line data
805  * have to be in the first 64 MB of memory, since this is
806  * the maximum mapped by the Linux kernel during initialization.
807  */
808 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
809 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
810 
811 #ifdef CONFIG_CMD_KGDB
812 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
813 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
814 #endif
815 
816 /*
817  * Environment Configuration
818  */
819 #define CONFIG_ROOTPATH	 "/opt/nfsroot"
820 #define CONFIG_BOOTFILE	 "uImage"
821 #define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
822 
823 /* default location for tftp and bootm */
824 #define CONFIG_LOADADDR		1000000
825 #define CONFIG_BAUDRATE		115200
826 #define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
827 #define __USB_PHY_TYPE		utmi
828 
829 #define	CONFIG_EXTRA_ENV_SETTINGS				\
830 	"hwconfig=fsl_ddr:"					\
831 	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
832 	"bank_intlv=auto;"					\
833 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
834 	"netdev=eth0\0"						\
835 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
836 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
837 	"tftpflash=tftpboot $loadaddr $uboot && "		\
838 	"protect off $ubootaddr +$filesize && "			\
839 	"erase $ubootaddr +$filesize && "			\
840 	"cp.b $loadaddr $ubootaddr $filesize && "		\
841 	"protect on $ubootaddr +$filesize && "			\
842 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
843 	"consoledev=ttyS0\0"					\
844 	"ramdiskaddr=2000000\0"					\
845 	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
846 	"fdtaddr=c00000\0"					\
847 	"fdtfile=t2080qds/t2080qds.dtb\0"			\
848 	"bdev=sda3\0"
849 
850 /*
851  * For emulation this causes u-boot to jump to the start of the
852  * proof point app code automatically
853  */
854 #define CONFIG_PROOF_POINTS				\
855 	"setenv bootargs root=/dev/$bdev rw "		\
856 	"console=$consoledev,$baudrate $othbootargs;"	\
857 	"cpu 1 release 0x29000000 - - -;"		\
858 	"cpu 2 release 0x29000000 - - -;"		\
859 	"cpu 3 release 0x29000000 - - -;"		\
860 	"cpu 4 release 0x29000000 - - -;"		\
861 	"cpu 5 release 0x29000000 - - -;"		\
862 	"cpu 6 release 0x29000000 - - -;"		\
863 	"cpu 7 release 0x29000000 - - -;"		\
864 	"go 0x29000000"
865 
866 #define CONFIG_HVBOOT				\
867 	"setenv bootargs config-addr=0x60000000; "	\
868 	"bootm 0x01000000 - 0x00f00000"
869 
870 #define CONFIG_ALU				\
871 	"setenv bootargs root=/dev/$bdev rw "		\
872 	"console=$consoledev,$baudrate $othbootargs;"	\
873 	"cpu 1 release 0x01000000 - - -;"		\
874 	"cpu 2 release 0x01000000 - - -;"		\
875 	"cpu 3 release 0x01000000 - - -;"		\
876 	"cpu 4 release 0x01000000 - - -;"		\
877 	"cpu 5 release 0x01000000 - - -;"		\
878 	"cpu 6 release 0x01000000 - - -;"		\
879 	"cpu 7 release 0x01000000 - - -;"		\
880 	"go 0x01000000"
881 
882 #define CONFIG_LINUX				\
883 	"setenv bootargs root=/dev/ram rw "		\
884 	"console=$consoledev,$baudrate $othbootargs;"	\
885 	"setenv ramdiskaddr 0x02000000;"		\
886 	"setenv fdtaddr 0x00c00000;"			\
887 	"setenv loadaddr 0x1000000;"			\
888 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
889 
890 #define CONFIG_HDBOOT					\
891 	"setenv bootargs root=/dev/$bdev rw "		\
892 	"console=$consoledev,$baudrate $othbootargs;"	\
893 	"tftp $loadaddr $bootfile;"			\
894 	"tftp $fdtaddr $fdtfile;"			\
895 	"bootm $loadaddr - $fdtaddr"
896 
897 #define CONFIG_NFSBOOTCOMMAND			\
898 	"setenv bootargs root=/dev/nfs rw "	\
899 	"nfsroot=$serverip:$rootpath "		\
900 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
901 	"console=$consoledev,$baudrate $othbootargs;"	\
902 	"tftp $loadaddr $bootfile;"		\
903 	"tftp $fdtaddr $fdtfile;"		\
904 	"bootm $loadaddr - $fdtaddr"
905 
906 #define CONFIG_RAMBOOTCOMMAND				\
907 	"setenv bootargs root=/dev/ram rw "		\
908 	"console=$consoledev,$baudrate $othbootargs;"	\
909 	"tftp $ramdiskaddr $ramdiskfile;"		\
910 	"tftp $loadaddr $bootfile;"			\
911 	"tftp $fdtaddr $fdtfile;"			\
912 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
913 
914 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
915 
916 #ifdef CONFIG_SECURE_BOOT
917 #include <asm/fsl_secure_boot.h>
918 #define CONFIG_CMD_BLOB
919 #undef CONFIG_CMD_USB
920 #endif
921 
922 #endif	/* __T208xQDS_H */
923