1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 16 #define CONFIG_MMC 17 #define CONFIG_USB_EHCI 18 #if defined(CONFIG_PPC_T2080) 19 #define CONFIG_T2080QDS 20 #define CONFIG_FSL_SATA_V2 21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 #define CONFIG_SRIO2 /* SRIO port 2 */ 24 #elif defined(CONFIG_PPC_T2081) 25 #define CONFIG_T2081QDS 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_BOOKE 30 #define CONFIG_E500 /* BOOKE e500 family */ 31 #define CONFIG_E500MC /* BOOKE e500mc family */ 32 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 33 #define CONFIG_MP /* support multiple processors */ 34 #define CONFIG_ENABLE_36BIT_PHYS 35 36 #ifdef CONFIG_PHYS_64BIT 37 #define CONFIG_ADDR_MAP 1 38 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 39 #endif 40 41 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 43 #define CONFIG_FSL_IFC /* Enable IFC Support */ 44 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 #define CONFIG_ENV_OVERWRITE 47 48 #ifdef CONFIG_RAMBOOT_PBL 49 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 50 #if defined(CONFIG_PPC_T2080) 51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg 52 #elif defined(CONFIG_PPC_T2081) 53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg 54 #endif 55 56 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 57 #define CONFIG_SPL_ENV_SUPPORT 58 #define CONFIG_SPL_SERIAL_SUPPORT 59 #define CONFIG_SPL_FLUSH_IMAGE 60 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 61 #define CONFIG_SPL_LIBGENERIC_SUPPORT 62 #define CONFIG_SPL_LIBCOMMON_SUPPORT 63 #define CONFIG_SPL_I2C_SUPPORT 64 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 65 #define CONFIG_FSL_LAW /* Use common FSL init code */ 66 #define CONFIG_SYS_TEXT_BASE 0x00201000 67 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 68 #define CONFIG_SPL_PAD_TO 0x40000 69 #define CONFIG_SPL_MAX_SIZE 0x28000 70 #define RESET_VECTOR_OFFSET 0x27FFC 71 #define BOOT_PAGE_OFFSET 0x27000 72 #ifdef CONFIG_SPL_BUILD 73 #define CONFIG_SPL_SKIP_RELOCATE 74 #define CONFIG_SPL_COMMON_INIT_DDR 75 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 76 #define CONFIG_SYS_NO_FLASH 77 #endif 78 79 #ifdef CONFIG_NAND 80 #define CONFIG_SPL_NAND_SUPPORT 81 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 83 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 84 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 86 #define CONFIG_SPL_NAND_BOOT 87 #endif 88 89 #ifdef CONFIG_SPIFLASH 90 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 91 #define CONFIG_SPL_SPI_SUPPORT 92 #define CONFIG_SPL_SPI_FLASH_SUPPORT 93 #define CONFIG_SPL_SPI_FLASH_MINIMAL 94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 96 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 97 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 98 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 99 #ifndef CONFIG_SPL_BUILD 100 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 101 #endif 102 #define CONFIG_SPL_SPI_BOOT 103 #endif 104 105 #ifdef CONFIG_SDCARD 106 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 107 #define CONFIG_SPL_MMC_SUPPORT 108 #define CONFIG_SPL_MMC_MINIMAL 109 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 110 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 111 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 112 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 113 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 114 #ifndef CONFIG_SPL_BUILD 115 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 116 #endif 117 #define CONFIG_SPL_MMC_BOOT 118 #endif 119 120 #endif /* CONFIG_RAMBOOT_PBL */ 121 122 #define CONFIG_SRIO_PCIE_BOOT_MASTER 123 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 124 /* Set 1M boot space */ 125 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 126 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 127 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 128 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 129 #define CONFIG_SYS_NO_FLASH 130 #endif 131 132 #ifndef CONFIG_SYS_TEXT_BASE 133 #define CONFIG_SYS_TEXT_BASE 0xeff40000 134 #endif 135 136 #ifndef CONFIG_RESET_VECTOR_ADDRESS 137 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 138 #endif 139 140 /* 141 * These can be toggled for performance analysis, otherwise use default. 142 */ 143 #define CONFIG_SYS_CACHE_STASHING 144 #define CONFIG_BTB /* toggle branch predition */ 145 #define CONFIG_DDR_ECC 146 #ifdef CONFIG_DDR_ECC 147 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 148 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 149 #endif 150 151 #ifndef CONFIG_SYS_NO_FLASH 152 #define CONFIG_FLASH_CFI_DRIVER 153 #define CONFIG_SYS_FLASH_CFI 154 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 155 #endif 156 157 #if defined(CONFIG_SPIFLASH) 158 #define CONFIG_SYS_EXTRA_ENV_RELOC 159 #define CONFIG_ENV_IS_IN_SPI_FLASH 160 #define CONFIG_ENV_SPI_BUS 0 161 #define CONFIG_ENV_SPI_CS 0 162 #define CONFIG_ENV_SPI_MAX_HZ 10000000 163 #define CONFIG_ENV_SPI_MODE 0 164 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 165 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 166 #define CONFIG_ENV_SECT_SIZE 0x10000 167 #elif defined(CONFIG_SDCARD) 168 #define CONFIG_SYS_EXTRA_ENV_RELOC 169 #define CONFIG_ENV_IS_IN_MMC 170 #define CONFIG_SYS_MMC_ENV_DEV 0 171 #define CONFIG_ENV_SIZE 0x2000 172 #define CONFIG_ENV_OFFSET (512 * 0x800) 173 #elif defined(CONFIG_NAND) 174 #define CONFIG_SYS_EXTRA_ENV_RELOC 175 #define CONFIG_ENV_IS_IN_NAND 176 #define CONFIG_ENV_SIZE 0x2000 177 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 178 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 179 #define CONFIG_ENV_IS_IN_REMOTE 180 #define CONFIG_ENV_ADDR 0xffe20000 181 #define CONFIG_ENV_SIZE 0x2000 182 #elif defined(CONFIG_ENV_IS_NOWHERE) 183 #define CONFIG_ENV_SIZE 0x2000 184 #else 185 #define CONFIG_ENV_IS_IN_FLASH 186 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 187 #define CONFIG_ENV_SIZE 0x2000 188 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 189 #endif 190 191 #ifndef __ASSEMBLY__ 192 unsigned long get_board_sys_clk(void); 193 unsigned long get_board_ddr_clk(void); 194 #endif 195 196 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 197 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 198 199 /* 200 * Config the L3 Cache as L3 SRAM 201 */ 202 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 203 #define CONFIG_SYS_L3_SIZE (512 << 10) 204 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 205 #ifdef CONFIG_RAMBOOT_PBL 206 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 207 #endif 208 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 209 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 210 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 211 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 212 213 #define CONFIG_SYS_DCSRBAR 0xf0000000 214 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 215 216 /* EEPROM */ 217 #define CONFIG_ID_EEPROM 218 #define CONFIG_SYS_I2C_EEPROM_NXID 219 #define CONFIG_SYS_EEPROM_BUS_NUM 0 220 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 221 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 222 223 /* 224 * DDR Setup 225 */ 226 #define CONFIG_VERY_BIG_RAM 227 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 228 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 229 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 230 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 231 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 232 #define CONFIG_DDR_SPD 233 #define CONFIG_SYS_FSL_DDR3 234 #define CONFIG_FSL_DDR_INTERACTIVE 235 #define CONFIG_SYS_SPD_BUS_NUM 0 236 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 237 #define SPD_EEPROM_ADDRESS1 0x51 238 #define SPD_EEPROM_ADDRESS2 0x52 239 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 240 #define CTRL_INTLV_PREFERED cacheline 241 242 /* 243 * IFC Definitions 244 */ 245 #define CONFIG_SYS_FLASH_BASE 0xe0000000 246 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 247 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 248 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 249 + 0x8000000) | \ 250 CSPR_PORT_SIZE_16 | \ 251 CSPR_MSEL_NOR | \ 252 CSPR_V) 253 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 254 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 255 CSPR_PORT_SIZE_16 | \ 256 CSPR_MSEL_NOR | \ 257 CSPR_V) 258 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 259 /* NOR Flash Timing Params */ 260 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 261 262 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 263 FTIM0_NOR_TEADC(0x5) | \ 264 FTIM0_NOR_TEAHC(0x5)) 265 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 266 FTIM1_NOR_TRAD_NOR(0x1A) |\ 267 FTIM1_NOR_TSEQRAD_NOR(0x13)) 268 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 269 FTIM2_NOR_TCH(0x4) | \ 270 FTIM2_NOR_TWPH(0x0E) | \ 271 FTIM2_NOR_TWP(0x1c)) 272 #define CONFIG_SYS_NOR_FTIM3 0x0 273 274 #define CONFIG_SYS_FLASH_QUIET_TEST 275 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 276 277 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 278 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 279 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 280 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 281 282 #define CONFIG_SYS_FLASH_EMPTY_INFO 283 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 284 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 285 286 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 287 #define QIXIS_BASE 0xffdf0000 288 #define QIXIS_LBMAP_SWITCH 6 289 #define QIXIS_LBMAP_MASK 0x0f 290 #define QIXIS_LBMAP_SHIFT 0 291 #define QIXIS_LBMAP_DFLTBANK 0x00 292 #define QIXIS_LBMAP_ALTBANK 0x04 293 #define QIXIS_LBMAP_NAND 0x09 294 #define QIXIS_LBMAP_SD 0x00 295 #define QIXIS_RCW_SRC_NAND 0x104 296 #define QIXIS_RCW_SRC_SD 0x040 297 #define QIXIS_RST_CTL_RESET 0x83 298 #define QIXIS_RST_FORCE_MEM 0x1 299 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 300 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 301 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 302 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 303 304 #define CONFIG_SYS_CSPR3_EXT (0xf) 305 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 306 | CSPR_PORT_SIZE_8 \ 307 | CSPR_MSEL_GPCM \ 308 | CSPR_V) 309 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 310 #define CONFIG_SYS_CSOR3 0x0 311 /* QIXIS Timing parameters for IFC CS3 */ 312 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 313 FTIM0_GPCM_TEADC(0x0e) | \ 314 FTIM0_GPCM_TEAHC(0x0e)) 315 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 316 FTIM1_GPCM_TRAD(0x3f)) 317 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 318 FTIM2_GPCM_TCH(0x8) | \ 319 FTIM2_GPCM_TWP(0x1f)) 320 #define CONFIG_SYS_CS3_FTIM3 0x0 321 322 /* NAND Flash on IFC */ 323 #define CONFIG_NAND_FSL_IFC 324 #define CONFIG_SYS_NAND_BASE 0xff800000 325 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 326 327 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 328 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 329 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 330 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 331 | CSPR_V) 332 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 333 334 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 335 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 336 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 337 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 338 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 339 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 340 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 341 342 #define CONFIG_SYS_NAND_ONFI_DETECTION 343 344 /* ONFI NAND Flash mode0 Timing Params */ 345 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 346 FTIM0_NAND_TWP(0x18) | \ 347 FTIM0_NAND_TWCHT(0x07) | \ 348 FTIM0_NAND_TWH(0x0a)) 349 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 350 FTIM1_NAND_TWBE(0x39) | \ 351 FTIM1_NAND_TRR(0x0e) | \ 352 FTIM1_NAND_TRP(0x18)) 353 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 354 FTIM2_NAND_TREH(0x0a) | \ 355 FTIM2_NAND_TWHRE(0x1e)) 356 #define CONFIG_SYS_NAND_FTIM3 0x0 357 358 #define CONFIG_SYS_NAND_DDR_LAW 11 359 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 360 #define CONFIG_SYS_MAX_NAND_DEVICE 1 361 #define CONFIG_CMD_NAND 362 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 363 364 #if defined(CONFIG_NAND) 365 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 366 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 367 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 368 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 369 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 370 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 371 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 372 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 373 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 374 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 375 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 376 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 377 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 378 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 379 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 380 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 381 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 382 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 383 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 384 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 385 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 386 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 387 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 388 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 389 #else 390 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 391 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 392 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 393 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 394 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 395 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 396 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 397 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 398 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 399 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 400 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 401 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 402 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 403 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 404 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 405 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 406 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 407 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 408 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 409 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 410 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 411 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 412 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 413 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 414 #endif 415 416 #if defined(CONFIG_RAMBOOT_PBL) 417 #define CONFIG_SYS_RAMBOOT 418 #endif 419 420 #ifdef CONFIG_SPL_BUILD 421 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 422 #else 423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 424 #endif 425 426 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 427 #define CONFIG_MISC_INIT_R 428 #define CONFIG_HWCONFIG 429 430 /* define to use L1 as initial stack */ 431 #define CONFIG_L1_INIT_RAM 432 #define CONFIG_SYS_INIT_RAM_LOCK 433 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 435 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 436 /* The assembler doesn't like typecast */ 437 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 438 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 439 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 440 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 441 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 442 GENERATED_GBL_DATA_SIZE) 443 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 444 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 445 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 446 447 /* 448 * Serial Port 449 */ 450 #define CONFIG_CONS_INDEX 1 451 #define CONFIG_SYS_NS16550_SERIAL 452 #define CONFIG_SYS_NS16550_REG_SIZE 1 453 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 454 #define CONFIG_SYS_BAUDRATE_TABLE \ 455 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 456 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 457 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 458 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 459 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 460 461 /* 462 * I2C 463 */ 464 #define CONFIG_SYS_I2C 465 #define CONFIG_SYS_I2C_FSL 466 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 467 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 468 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 469 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 470 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 471 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 472 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 473 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 474 #define CONFIG_SYS_FSL_I2C_SPEED 100000 475 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 476 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 477 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 478 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 479 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 480 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 481 #define I2C_MUX_CH_DEFAULT 0x8 482 483 #define I2C_MUX_CH_VOL_MONITOR 0xa 484 485 /* Voltage monitor on channel 2*/ 486 #define I2C_VOL_MONITOR_ADDR 0x40 487 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 488 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 489 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 490 491 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 492 #ifndef CONFIG_SPL_BUILD 493 #define CONFIG_VID 494 #endif 495 #define CONFIG_VOL_MONITOR_IR36021_SET 496 #define CONFIG_VOL_MONITOR_IR36021_READ 497 /* The lowest and highest voltage allowed for T208xQDS */ 498 #define VDD_MV_MIN 819 499 #define VDD_MV_MAX 1212 500 501 /* 502 * RapidIO 503 */ 504 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 505 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 506 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 507 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 508 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 509 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 510 /* 511 * for slave u-boot IMAGE instored in master memory space, 512 * PHYS must be aligned based on the SIZE 513 */ 514 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 515 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 516 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 517 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 518 /* 519 * for slave UCODE and ENV instored in master memory space, 520 * PHYS must be aligned based on the SIZE 521 */ 522 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 523 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 524 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 525 526 /* slave core release by master*/ 527 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 528 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 529 530 /* 531 * SRIO_PCIE_BOOT - SLAVE 532 */ 533 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 534 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 535 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 536 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 537 #endif 538 539 /* 540 * eSPI - Enhanced SPI 541 */ 542 #ifdef CONFIG_SPI_FLASH 543 #ifndef CONFIG_SPL_BUILD 544 #endif 545 546 #define CONFIG_SPI_FLASH_BAR 547 #define CONFIG_SF_DEFAULT_SPEED 10000000 548 #define CONFIG_SF_DEFAULT_MODE 0 549 #endif 550 551 /* 552 * General PCI 553 * Memory space is mapped 1-1, but I/O space must start from 0. 554 */ 555 #define CONFIG_PCI /* Enable PCI/PCIE */ 556 #define CONFIG_PCIE1 /* PCIE controller 1 */ 557 #define CONFIG_PCIE2 /* PCIE controller 2 */ 558 #define CONFIG_PCIE3 /* PCIE controller 3 */ 559 #define CONFIG_PCIE4 /* PCIE controller 4 */ 560 #define CONFIG_FSL_PCIE_RESET 561 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 562 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 563 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 564 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 565 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 566 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 567 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 568 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 569 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 570 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 571 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 572 573 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 574 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 575 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 576 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 577 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 578 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 579 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 580 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 581 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 582 583 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 584 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 585 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 586 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 587 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 588 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 589 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 590 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 591 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 592 593 /* controller 4, Base address 203000 */ 594 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 595 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 596 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 597 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 598 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 599 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 600 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 601 602 #ifdef CONFIG_PCI 603 #define CONFIG_PCI_INDIRECT_BRIDGE 604 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 605 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 606 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 607 #define CONFIG_DOS_PARTITION 608 #endif 609 610 /* Qman/Bman */ 611 #ifndef CONFIG_NOBQFMAN 612 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 613 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 614 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 615 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 616 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 617 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 618 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 619 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 620 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 621 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 622 CONFIG_SYS_BMAN_CENA_SIZE) 623 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 624 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 625 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 626 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 627 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 628 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 629 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 630 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 631 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 632 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 633 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 634 CONFIG_SYS_QMAN_CENA_SIZE) 635 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 636 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 637 638 #define CONFIG_SYS_DPAA_FMAN 639 #define CONFIG_SYS_DPAA_PME 640 #define CONFIG_SYS_PMAN 641 #define CONFIG_SYS_DPAA_DCE 642 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 643 #define CONFIG_SYS_INTERLAKEN 644 645 /* Default address of microcode for the Linux Fman driver */ 646 #if defined(CONFIG_SPIFLASH) 647 /* 648 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 649 * env, so we got 0x110000. 650 */ 651 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 652 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 653 #elif defined(CONFIG_SDCARD) 654 /* 655 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 656 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 657 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 658 */ 659 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 660 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 661 #elif defined(CONFIG_NAND) 662 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 663 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 664 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 665 /* 666 * Slave has no ucode locally, it can fetch this from remote. When implementing 667 * in two corenet boards, slave's ucode could be stored in master's memory 668 * space, the address can be mapped from slave TLB->slave LAW-> 669 * slave SRIO or PCIE outbound window->master inbound window-> 670 * master LAW->the ucode address in master's memory space. 671 */ 672 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 673 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 674 #else 675 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 676 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 677 #endif 678 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 679 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 680 #endif /* CONFIG_NOBQFMAN */ 681 682 #ifdef CONFIG_SYS_DPAA_FMAN 683 #define CONFIG_FMAN_ENET 684 #define CONFIG_PHYLIB_10G 685 #define CONFIG_PHY_VITESSE 686 #define CONFIG_PHY_REALTEK 687 #define CONFIG_PHY_TERANETICS 688 #define RGMII_PHY1_ADDR 0x1 689 #define RGMII_PHY2_ADDR 0x2 690 #define FM1_10GEC1_PHY_ADDR 0x3 691 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 692 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 693 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 694 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 695 #endif 696 697 #ifdef CONFIG_FMAN_ENET 698 #define CONFIG_MII /* MII PHY management */ 699 #define CONFIG_ETHPRIME "FM1@DTSEC3" 700 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 701 #endif 702 703 /* 704 * SATA 705 */ 706 #ifdef CONFIG_FSL_SATA_V2 707 #define CONFIG_LIBATA 708 #define CONFIG_FSL_SATA 709 #define CONFIG_SYS_SATA_MAX_DEVICE 2 710 #define CONFIG_SATA1 711 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 712 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 713 #define CONFIG_SATA2 714 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 715 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 716 #define CONFIG_LBA48 717 #define CONFIG_CMD_SATA 718 #define CONFIG_DOS_PARTITION 719 #endif 720 721 /* 722 * USB 723 */ 724 #ifdef CONFIG_USB_EHCI 725 #define CONFIG_USB_STORAGE 726 #define CONFIG_USB_EHCI_FSL 727 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 728 #define CONFIG_HAS_FSL_DR_USB 729 #endif 730 731 /* 732 * SDHC 733 */ 734 #ifdef CONFIG_MMC 735 #define CONFIG_FSL_ESDHC 736 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 737 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 738 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 739 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 740 #define CONFIG_GENERIC_MMC 741 #define CONFIG_DOS_PARTITION 742 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 743 #endif 744 745 /* 746 * Dynamic MTD Partition support with mtdparts 747 */ 748 #ifndef CONFIG_SYS_NO_FLASH 749 #define CONFIG_MTD_DEVICE 750 #define CONFIG_MTD_PARTITIONS 751 #define CONFIG_CMD_MTDPARTS 752 #define CONFIG_FLASH_CFI_MTD 753 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 754 "spi0=spife110000.0" 755 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 756 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 757 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 758 "1m(uboot),5m(kernel),128k(dtb),-(user)" 759 #endif 760 761 /* 762 * Environment 763 */ 764 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 765 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 766 767 /* 768 * Command line configuration. 769 */ 770 #define CONFIG_CMD_ERRATA 771 #define CONFIG_CMD_IRQ 772 #define CONFIG_CMD_REGINFO 773 774 #ifdef CONFIG_PCI 775 #define CONFIG_CMD_PCI 776 #endif 777 778 /* Hash command with SHA acceleration supported in hardware */ 779 #ifdef CONFIG_FSL_CAAM 780 #define CONFIG_CMD_HASH 781 #define CONFIG_SHA_HW_ACCEL 782 #endif 783 784 /* 785 * Miscellaneous configurable options 786 */ 787 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 788 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 789 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 790 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 791 #ifdef CONFIG_CMD_KGDB 792 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 793 #else 794 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 795 #endif 796 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 797 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 798 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 799 800 /* 801 * For booting Linux, the board info and command line data 802 * have to be in the first 64 MB of memory, since this is 803 * the maximum mapped by the Linux kernel during initialization. 804 */ 805 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 806 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 807 808 #ifdef CONFIG_CMD_KGDB 809 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 810 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 811 #endif 812 813 /* 814 * Environment Configuration 815 */ 816 #define CONFIG_ROOTPATH "/opt/nfsroot" 817 #define CONFIG_BOOTFILE "uImage" 818 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 819 820 /* default location for tftp and bootm */ 821 #define CONFIG_LOADADDR 1000000 822 #define CONFIG_BAUDRATE 115200 823 #define __USB_PHY_TYPE utmi 824 825 #define CONFIG_EXTRA_ENV_SETTINGS \ 826 "hwconfig=fsl_ddr:" \ 827 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 828 "bank_intlv=auto;" \ 829 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 830 "netdev=eth0\0" \ 831 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 832 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 833 "tftpflash=tftpboot $loadaddr $uboot && " \ 834 "protect off $ubootaddr +$filesize && " \ 835 "erase $ubootaddr +$filesize && " \ 836 "cp.b $loadaddr $ubootaddr $filesize && " \ 837 "protect on $ubootaddr +$filesize && " \ 838 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 839 "consoledev=ttyS0\0" \ 840 "ramdiskaddr=2000000\0" \ 841 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 842 "fdtaddr=1e00000\0" \ 843 "fdtfile=t2080qds/t2080qds.dtb\0" \ 844 "bdev=sda3\0" 845 846 /* 847 * For emulation this causes u-boot to jump to the start of the 848 * proof point app code automatically 849 */ 850 #define CONFIG_PROOF_POINTS \ 851 "setenv bootargs root=/dev/$bdev rw " \ 852 "console=$consoledev,$baudrate $othbootargs;" \ 853 "cpu 1 release 0x29000000 - - -;" \ 854 "cpu 2 release 0x29000000 - - -;" \ 855 "cpu 3 release 0x29000000 - - -;" \ 856 "cpu 4 release 0x29000000 - - -;" \ 857 "cpu 5 release 0x29000000 - - -;" \ 858 "cpu 6 release 0x29000000 - - -;" \ 859 "cpu 7 release 0x29000000 - - -;" \ 860 "go 0x29000000" 861 862 #define CONFIG_HVBOOT \ 863 "setenv bootargs config-addr=0x60000000; " \ 864 "bootm 0x01000000 - 0x00f00000" 865 866 #define CONFIG_ALU \ 867 "setenv bootargs root=/dev/$bdev rw " \ 868 "console=$consoledev,$baudrate $othbootargs;" \ 869 "cpu 1 release 0x01000000 - - -;" \ 870 "cpu 2 release 0x01000000 - - -;" \ 871 "cpu 3 release 0x01000000 - - -;" \ 872 "cpu 4 release 0x01000000 - - -;" \ 873 "cpu 5 release 0x01000000 - - -;" \ 874 "cpu 6 release 0x01000000 - - -;" \ 875 "cpu 7 release 0x01000000 - - -;" \ 876 "go 0x01000000" 877 878 #define CONFIG_LINUX \ 879 "setenv bootargs root=/dev/ram rw " \ 880 "console=$consoledev,$baudrate $othbootargs;" \ 881 "setenv ramdiskaddr 0x02000000;" \ 882 "setenv fdtaddr 0x00c00000;" \ 883 "setenv loadaddr 0x1000000;" \ 884 "bootm $loadaddr $ramdiskaddr $fdtaddr" 885 886 #define CONFIG_HDBOOT \ 887 "setenv bootargs root=/dev/$bdev rw " \ 888 "console=$consoledev,$baudrate $othbootargs;" \ 889 "tftp $loadaddr $bootfile;" \ 890 "tftp $fdtaddr $fdtfile;" \ 891 "bootm $loadaddr - $fdtaddr" 892 893 #define CONFIG_NFSBOOTCOMMAND \ 894 "setenv bootargs root=/dev/nfs rw " \ 895 "nfsroot=$serverip:$rootpath " \ 896 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 897 "console=$consoledev,$baudrate $othbootargs;" \ 898 "tftp $loadaddr $bootfile;" \ 899 "tftp $fdtaddr $fdtfile;" \ 900 "bootm $loadaddr - $fdtaddr" 901 902 #define CONFIG_RAMBOOTCOMMAND \ 903 "setenv bootargs root=/dev/ram rw " \ 904 "console=$consoledev,$baudrate $othbootargs;" \ 905 "tftp $ramdiskaddr $ramdiskfile;" \ 906 "tftp $loadaddr $bootfile;" \ 907 "tftp $fdtaddr $fdtfile;" \ 908 "bootm $loadaddr $ramdiskaddr $fdtaddr" 909 910 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 911 912 #include <asm/fsl_secure_boot.h> 913 914 #endif /* __T208xQDS_H */ 915