1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #if defined(CONFIG_ARCH_T2080) 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 18 #define CONFIG_SRIO1 /* SRIO port 1 */ 19 #define CONFIG_SRIO2 /* SRIO port 2 */ 20 #elif defined(CONFIG_ARCH_T2081) 21 #endif 22 23 /* High Level Configuration Options */ 24 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 25 #define CONFIG_MP /* support multiple processors */ 26 #define CONFIG_ENABLE_36BIT_PHYS 27 28 #ifdef CONFIG_PHYS_64BIT 29 #define CONFIG_ADDR_MAP 1 30 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 31 #endif 32 33 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 34 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 35 #define CONFIG_ENV_OVERWRITE 36 37 #ifdef CONFIG_RAMBOOT_PBL 38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 39 40 #define CONFIG_SPL_FLUSH_IMAGE 41 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 42 #define CONFIG_SYS_TEXT_BASE 0x00201000 43 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 44 #define CONFIG_SPL_PAD_TO 0x40000 45 #define CONFIG_SPL_MAX_SIZE 0x28000 46 #define RESET_VECTOR_OFFSET 0x27FFC 47 #define BOOT_PAGE_OFFSET 0x27000 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_SKIP_RELOCATE 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 52 #endif 53 54 #ifdef CONFIG_NAND 55 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 56 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 57 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 58 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 59 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 60 #if defined(CONFIG_ARCH_T2080) 61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 62 #elif defined(CONFIG_ARCH_T2081) 63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 64 #endif 65 #define CONFIG_SPL_NAND_BOOT 66 #endif 67 68 #ifdef CONFIG_SPIFLASH 69 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 70 #define CONFIG_SPL_SPI_FLASH_MINIMAL 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 76 #ifndef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 78 #endif 79 #if defined(CONFIG_ARCH_T2080) 80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 81 #elif defined(CONFIG_ARCH_T2081) 82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 83 #endif 84 #define CONFIG_SPL_SPI_BOOT 85 #endif 86 87 #ifdef CONFIG_SDCARD 88 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 89 #define CONFIG_SPL_MMC_MINIMAL 90 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 91 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 92 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 93 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 94 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 95 #ifndef CONFIG_SPL_BUILD 96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 97 #endif 98 #if defined(CONFIG_ARCH_T2080) 99 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 100 #elif defined(CONFIG_ARCH_T2081) 101 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 102 #endif 103 #define CONFIG_SPL_MMC_BOOT 104 #endif 105 106 #endif /* CONFIG_RAMBOOT_PBL */ 107 108 #define CONFIG_SRIO_PCIE_BOOT_MASTER 109 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 110 /* Set 1M boot space */ 111 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 112 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 113 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 114 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 115 #endif 116 117 #ifndef CONFIG_SYS_TEXT_BASE 118 #define CONFIG_SYS_TEXT_BASE 0xeff40000 119 #endif 120 121 #ifndef CONFIG_RESET_VECTOR_ADDRESS 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 123 #endif 124 125 /* 126 * These can be toggled for performance analysis, otherwise use default. 127 */ 128 #define CONFIG_SYS_CACHE_STASHING 129 #define CONFIG_BTB /* toggle branch predition */ 130 #define CONFIG_DDR_ECC 131 #ifdef CONFIG_DDR_ECC 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 133 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 134 #endif 135 136 #ifdef CONFIG_MTD_NOR_FLASH 137 #define CONFIG_FLASH_CFI_DRIVER 138 #define CONFIG_SYS_FLASH_CFI 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 140 #endif 141 142 #if defined(CONFIG_SPIFLASH) 143 #define CONFIG_SYS_EXTRA_ENV_RELOC 144 #define CONFIG_ENV_IS_IN_SPI_FLASH 145 #define CONFIG_ENV_SPI_BUS 0 146 #define CONFIG_ENV_SPI_CS 0 147 #define CONFIG_ENV_SPI_MAX_HZ 10000000 148 #define CONFIG_ENV_SPI_MODE 0 149 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 150 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 151 #define CONFIG_ENV_SECT_SIZE 0x10000 152 #elif defined(CONFIG_SDCARD) 153 #define CONFIG_SYS_EXTRA_ENV_RELOC 154 #define CONFIG_SYS_MMC_ENV_DEV 0 155 #define CONFIG_ENV_SIZE 0x2000 156 #define CONFIG_ENV_OFFSET (512 * 0x800) 157 #elif defined(CONFIG_NAND) 158 #define CONFIG_SYS_EXTRA_ENV_RELOC 159 #define CONFIG_ENV_SIZE 0x2000 160 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 161 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 162 #define CONFIG_ENV_IS_IN_REMOTE 163 #define CONFIG_ENV_ADDR 0xffe20000 164 #define CONFIG_ENV_SIZE 0x2000 165 #elif defined(CONFIG_ENV_IS_NOWHERE) 166 #define CONFIG_ENV_SIZE 0x2000 167 #else 168 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 169 #define CONFIG_ENV_SIZE 0x2000 170 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 171 #endif 172 173 #ifndef __ASSEMBLY__ 174 unsigned long get_board_sys_clk(void); 175 unsigned long get_board_ddr_clk(void); 176 #endif 177 178 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 179 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 180 181 /* 182 * Config the L3 Cache as L3 SRAM 183 */ 184 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 185 #define CONFIG_SYS_L3_SIZE (512 << 10) 186 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 187 #ifdef CONFIG_RAMBOOT_PBL 188 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 189 #endif 190 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 191 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 192 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 193 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 194 195 #define CONFIG_SYS_DCSRBAR 0xf0000000 196 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 197 198 /* EEPROM */ 199 #define CONFIG_ID_EEPROM 200 #define CONFIG_SYS_I2C_EEPROM_NXID 201 #define CONFIG_SYS_EEPROM_BUS_NUM 0 202 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 203 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 204 205 /* 206 * DDR Setup 207 */ 208 #define CONFIG_VERY_BIG_RAM 209 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 210 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 211 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 212 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 213 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 214 #define CONFIG_DDR_SPD 215 #define CONFIG_FSL_DDR_INTERACTIVE 216 #define CONFIG_SYS_SPD_BUS_NUM 0 217 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 218 #define SPD_EEPROM_ADDRESS1 0x51 219 #define SPD_EEPROM_ADDRESS2 0x52 220 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 221 #define CTRL_INTLV_PREFERED cacheline 222 223 /* 224 * IFC Definitions 225 */ 226 #define CONFIG_SYS_FLASH_BASE 0xe0000000 227 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 228 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 229 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 230 + 0x8000000) | \ 231 CSPR_PORT_SIZE_16 | \ 232 CSPR_MSEL_NOR | \ 233 CSPR_V) 234 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 235 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 236 CSPR_PORT_SIZE_16 | \ 237 CSPR_MSEL_NOR | \ 238 CSPR_V) 239 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 240 /* NOR Flash Timing Params */ 241 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 242 243 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 244 FTIM0_NOR_TEADC(0x5) | \ 245 FTIM0_NOR_TEAHC(0x5)) 246 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 247 FTIM1_NOR_TRAD_NOR(0x1A) |\ 248 FTIM1_NOR_TSEQRAD_NOR(0x13)) 249 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 250 FTIM2_NOR_TCH(0x4) | \ 251 FTIM2_NOR_TWPH(0x0E) | \ 252 FTIM2_NOR_TWP(0x1c)) 253 #define CONFIG_SYS_NOR_FTIM3 0x0 254 255 #define CONFIG_SYS_FLASH_QUIET_TEST 256 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 257 258 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 259 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 260 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 261 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 262 263 #define CONFIG_SYS_FLASH_EMPTY_INFO 264 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 265 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 266 267 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 268 #define QIXIS_BASE 0xffdf0000 269 #define QIXIS_LBMAP_SWITCH 6 270 #define QIXIS_LBMAP_MASK 0x0f 271 #define QIXIS_LBMAP_SHIFT 0 272 #define QIXIS_LBMAP_DFLTBANK 0x00 273 #define QIXIS_LBMAP_ALTBANK 0x04 274 #define QIXIS_LBMAP_NAND 0x09 275 #define QIXIS_LBMAP_SD 0x00 276 #define QIXIS_RCW_SRC_NAND 0x104 277 #define QIXIS_RCW_SRC_SD 0x040 278 #define QIXIS_RST_CTL_RESET 0x83 279 #define QIXIS_RST_FORCE_MEM 0x1 280 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 281 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 282 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 283 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 284 285 #define CONFIG_SYS_CSPR3_EXT (0xf) 286 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 287 | CSPR_PORT_SIZE_8 \ 288 | CSPR_MSEL_GPCM \ 289 | CSPR_V) 290 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 291 #define CONFIG_SYS_CSOR3 0x0 292 /* QIXIS Timing parameters for IFC CS3 */ 293 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 294 FTIM0_GPCM_TEADC(0x0e) | \ 295 FTIM0_GPCM_TEAHC(0x0e)) 296 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 297 FTIM1_GPCM_TRAD(0x3f)) 298 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 299 FTIM2_GPCM_TCH(0x8) | \ 300 FTIM2_GPCM_TWP(0x1f)) 301 #define CONFIG_SYS_CS3_FTIM3 0x0 302 303 /* NAND Flash on IFC */ 304 #define CONFIG_NAND_FSL_IFC 305 #define CONFIG_SYS_NAND_BASE 0xff800000 306 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 307 308 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 309 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 310 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 311 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 312 | CSPR_V) 313 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 314 315 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 316 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 317 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 318 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 319 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 320 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 321 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 322 323 #define CONFIG_SYS_NAND_ONFI_DETECTION 324 325 /* ONFI NAND Flash mode0 Timing Params */ 326 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 327 FTIM0_NAND_TWP(0x18) | \ 328 FTIM0_NAND_TWCHT(0x07) | \ 329 FTIM0_NAND_TWH(0x0a)) 330 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 331 FTIM1_NAND_TWBE(0x39) | \ 332 FTIM1_NAND_TRR(0x0e) | \ 333 FTIM1_NAND_TRP(0x18)) 334 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 335 FTIM2_NAND_TREH(0x0a) | \ 336 FTIM2_NAND_TWHRE(0x1e)) 337 #define CONFIG_SYS_NAND_FTIM3 0x0 338 339 #define CONFIG_SYS_NAND_DDR_LAW 11 340 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 341 #define CONFIG_SYS_MAX_NAND_DEVICE 1 342 #define CONFIG_CMD_NAND 343 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 344 345 #if defined(CONFIG_NAND) 346 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 347 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 348 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 349 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 350 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 351 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 352 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 353 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 354 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 355 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 356 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 357 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 358 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 359 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 360 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 361 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 362 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 363 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 364 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 365 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 366 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 367 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 368 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 369 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 370 #else 371 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 372 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 373 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 374 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 375 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 376 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 377 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 378 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 379 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 380 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 381 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 382 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 383 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 384 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 385 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 386 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 387 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 388 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 389 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 390 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 391 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 392 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 393 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 394 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 395 #endif 396 397 #if defined(CONFIG_RAMBOOT_PBL) 398 #define CONFIG_SYS_RAMBOOT 399 #endif 400 401 #ifdef CONFIG_SPL_BUILD 402 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 403 #else 404 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 405 #endif 406 407 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 408 #define CONFIG_MISC_INIT_R 409 #define CONFIG_HWCONFIG 410 411 /* define to use L1 as initial stack */ 412 #define CONFIG_L1_INIT_RAM 413 #define CONFIG_SYS_INIT_RAM_LOCK 414 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 417 /* The assembler doesn't like typecast */ 418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 419 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 420 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 421 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 422 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 423 GENERATED_GBL_DATA_SIZE) 424 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 425 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 426 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 427 428 /* 429 * Serial Port 430 */ 431 #define CONFIG_CONS_INDEX 1 432 #define CONFIG_SYS_NS16550_SERIAL 433 #define CONFIG_SYS_NS16550_REG_SIZE 1 434 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 435 #define CONFIG_SYS_BAUDRATE_TABLE \ 436 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 437 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 438 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 439 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 440 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 441 442 /* 443 * I2C 444 */ 445 #define CONFIG_SYS_I2C 446 #define CONFIG_SYS_I2C_FSL 447 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 448 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 449 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 450 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 451 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 452 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 453 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 454 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 455 #define CONFIG_SYS_FSL_I2C_SPEED 100000 456 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 457 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 458 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 459 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 460 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 461 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 462 #define I2C_MUX_CH_DEFAULT 0x8 463 464 #define I2C_MUX_CH_VOL_MONITOR 0xa 465 466 /* Voltage monitor on channel 2*/ 467 #define I2C_VOL_MONITOR_ADDR 0x40 468 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 469 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 470 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 471 472 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 473 #ifndef CONFIG_SPL_BUILD 474 #define CONFIG_VID 475 #endif 476 #define CONFIG_VOL_MONITOR_IR36021_SET 477 #define CONFIG_VOL_MONITOR_IR36021_READ 478 /* The lowest and highest voltage allowed for T208xQDS */ 479 #define VDD_MV_MIN 819 480 #define VDD_MV_MAX 1212 481 482 /* 483 * RapidIO 484 */ 485 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 486 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 487 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 488 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 489 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 490 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 491 /* 492 * for slave u-boot IMAGE instored in master memory space, 493 * PHYS must be aligned based on the SIZE 494 */ 495 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 496 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 497 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 498 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 499 /* 500 * for slave UCODE and ENV instored in master memory space, 501 * PHYS must be aligned based on the SIZE 502 */ 503 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 504 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 505 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 506 507 /* slave core release by master*/ 508 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 509 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 510 511 /* 512 * SRIO_PCIE_BOOT - SLAVE 513 */ 514 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 515 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 516 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 517 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 518 #endif 519 520 /* 521 * eSPI - Enhanced SPI 522 */ 523 #ifdef CONFIG_SPI_FLASH 524 #ifndef CONFIG_SPL_BUILD 525 #endif 526 527 #define CONFIG_SPI_FLASH_BAR 528 #define CONFIG_SF_DEFAULT_SPEED 10000000 529 #define CONFIG_SF_DEFAULT_MODE 0 530 #endif 531 532 /* 533 * General PCI 534 * Memory space is mapped 1-1, but I/O space must start from 0. 535 */ 536 #define CONFIG_PCIE1 /* PCIE controller 1 */ 537 #define CONFIG_PCIE2 /* PCIE controller 2 */ 538 #define CONFIG_PCIE3 /* PCIE controller 3 */ 539 #define CONFIG_PCIE4 /* PCIE controller 4 */ 540 #define CONFIG_FSL_PCIE_RESET 541 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 542 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 543 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 544 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 545 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 546 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 547 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 548 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 549 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 550 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 551 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 552 553 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 554 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 555 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 556 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 557 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 558 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 559 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 560 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 561 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 562 563 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 564 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 565 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 566 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 567 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 568 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 569 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 570 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 571 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 572 573 /* controller 4, Base address 203000 */ 574 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 575 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 576 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 577 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 578 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 579 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 580 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 581 582 #ifdef CONFIG_PCI 583 #define CONFIG_PCI_INDIRECT_BRIDGE 584 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 585 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 586 #endif 587 588 /* Qman/Bman */ 589 #ifndef CONFIG_NOBQFMAN 590 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 591 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 592 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 593 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 594 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 595 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 596 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 597 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 598 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 599 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 600 CONFIG_SYS_BMAN_CENA_SIZE) 601 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 602 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 603 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 604 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 605 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 606 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 607 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 608 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 609 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 610 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 611 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 612 CONFIG_SYS_QMAN_CENA_SIZE) 613 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 614 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 615 616 #define CONFIG_SYS_DPAA_FMAN 617 #define CONFIG_SYS_DPAA_PME 618 #define CONFIG_SYS_PMAN 619 #define CONFIG_SYS_DPAA_DCE 620 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 621 #define CONFIG_SYS_INTERLAKEN 622 623 /* Default address of microcode for the Linux Fman driver */ 624 #if defined(CONFIG_SPIFLASH) 625 /* 626 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 627 * env, so we got 0x110000. 628 */ 629 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 630 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 631 #elif defined(CONFIG_SDCARD) 632 /* 633 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 634 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 635 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 636 */ 637 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 638 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 639 #elif defined(CONFIG_NAND) 640 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 641 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 642 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 643 /* 644 * Slave has no ucode locally, it can fetch this from remote. When implementing 645 * in two corenet boards, slave's ucode could be stored in master's memory 646 * space, the address can be mapped from slave TLB->slave LAW-> 647 * slave SRIO or PCIE outbound window->master inbound window-> 648 * master LAW->the ucode address in master's memory space. 649 */ 650 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 651 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 652 #else 653 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 654 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 655 #endif 656 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 657 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 658 #endif /* CONFIG_NOBQFMAN */ 659 660 #ifdef CONFIG_SYS_DPAA_FMAN 661 #define CONFIG_FMAN_ENET 662 #define CONFIG_PHYLIB_10G 663 #define CONFIG_PHY_VITESSE 664 #define CONFIG_PHY_REALTEK 665 #define CONFIG_PHY_TERANETICS 666 #define RGMII_PHY1_ADDR 0x1 667 #define RGMII_PHY2_ADDR 0x2 668 #define FM1_10GEC1_PHY_ADDR 0x3 669 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 670 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 671 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 672 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 673 #endif 674 675 #ifdef CONFIG_FMAN_ENET 676 #define CONFIG_MII /* MII PHY management */ 677 #define CONFIG_ETHPRIME "FM1@DTSEC3" 678 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 679 #endif 680 681 /* 682 * SATA 683 */ 684 #ifdef CONFIG_FSL_SATA_V2 685 #define CONFIG_LIBATA 686 #define CONFIG_FSL_SATA 687 #define CONFIG_SYS_SATA_MAX_DEVICE 2 688 #define CONFIG_SATA1 689 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 690 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 691 #define CONFIG_SATA2 692 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 693 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 694 #define CONFIG_LBA48 695 #endif 696 697 /* 698 * USB 699 */ 700 #ifdef CONFIG_USB_EHCI_HCD 701 #define CONFIG_USB_EHCI_FSL 702 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 703 #define CONFIG_HAS_FSL_DR_USB 704 #endif 705 706 /* 707 * SDHC 708 */ 709 #ifdef CONFIG_MMC 710 #define CONFIG_FSL_ESDHC 711 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 712 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 713 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 714 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 715 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 716 #endif 717 718 /* 719 * Dynamic MTD Partition support with mtdparts 720 */ 721 #ifdef CONFIG_MTD_NOR_FLASH 722 #define CONFIG_MTD_DEVICE 723 #define CONFIG_MTD_PARTITIONS 724 #define CONFIG_FLASH_CFI_MTD 725 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 726 "spi0=spife110000.0" 727 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 728 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 729 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 730 "1m(uboot),5m(kernel),128k(dtb),-(user)" 731 #endif 732 733 /* 734 * Environment 735 */ 736 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 737 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 738 739 /* 740 * Command line configuration. 741 */ 742 #define CONFIG_CMD_REGINFO 743 744 #ifdef CONFIG_PCI 745 #define CONFIG_CMD_PCI 746 #endif 747 748 /* 749 * Miscellaneous configurable options 750 */ 751 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 752 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 753 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 754 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 755 #ifdef CONFIG_CMD_KGDB 756 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 757 #else 758 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 759 #endif 760 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 761 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 762 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 763 764 /* 765 * For booting Linux, the board info and command line data 766 * have to be in the first 64 MB of memory, since this is 767 * the maximum mapped by the Linux kernel during initialization. 768 */ 769 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 770 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 771 772 #ifdef CONFIG_CMD_KGDB 773 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 774 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 775 #endif 776 777 /* 778 * Environment Configuration 779 */ 780 #define CONFIG_ROOTPATH "/opt/nfsroot" 781 #define CONFIG_BOOTFILE "uImage" 782 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 783 784 /* default location for tftp and bootm */ 785 #define CONFIG_LOADADDR 1000000 786 #define __USB_PHY_TYPE utmi 787 788 #define CONFIG_EXTRA_ENV_SETTINGS \ 789 "hwconfig=fsl_ddr:" \ 790 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 791 "bank_intlv=auto;" \ 792 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 793 "netdev=eth0\0" \ 794 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 795 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 796 "tftpflash=tftpboot $loadaddr $uboot && " \ 797 "protect off $ubootaddr +$filesize && " \ 798 "erase $ubootaddr +$filesize && " \ 799 "cp.b $loadaddr $ubootaddr $filesize && " \ 800 "protect on $ubootaddr +$filesize && " \ 801 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 802 "consoledev=ttyS0\0" \ 803 "ramdiskaddr=2000000\0" \ 804 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 805 "fdtaddr=1e00000\0" \ 806 "fdtfile=t2080qds/t2080qds.dtb\0" \ 807 "bdev=sda3\0" 808 809 /* 810 * For emulation this causes u-boot to jump to the start of the 811 * proof point app code automatically 812 */ 813 #define CONFIG_PROOF_POINTS \ 814 "setenv bootargs root=/dev/$bdev rw " \ 815 "console=$consoledev,$baudrate $othbootargs;" \ 816 "cpu 1 release 0x29000000 - - -;" \ 817 "cpu 2 release 0x29000000 - - -;" \ 818 "cpu 3 release 0x29000000 - - -;" \ 819 "cpu 4 release 0x29000000 - - -;" \ 820 "cpu 5 release 0x29000000 - - -;" \ 821 "cpu 6 release 0x29000000 - - -;" \ 822 "cpu 7 release 0x29000000 - - -;" \ 823 "go 0x29000000" 824 825 #define CONFIG_HVBOOT \ 826 "setenv bootargs config-addr=0x60000000; " \ 827 "bootm 0x01000000 - 0x00f00000" 828 829 #define CONFIG_ALU \ 830 "setenv bootargs root=/dev/$bdev rw " \ 831 "console=$consoledev,$baudrate $othbootargs;" \ 832 "cpu 1 release 0x01000000 - - -;" \ 833 "cpu 2 release 0x01000000 - - -;" \ 834 "cpu 3 release 0x01000000 - - -;" \ 835 "cpu 4 release 0x01000000 - - -;" \ 836 "cpu 5 release 0x01000000 - - -;" \ 837 "cpu 6 release 0x01000000 - - -;" \ 838 "cpu 7 release 0x01000000 - - -;" \ 839 "go 0x01000000" 840 841 #define CONFIG_LINUX \ 842 "setenv bootargs root=/dev/ram rw " \ 843 "console=$consoledev,$baudrate $othbootargs;" \ 844 "setenv ramdiskaddr 0x02000000;" \ 845 "setenv fdtaddr 0x00c00000;" \ 846 "setenv loadaddr 0x1000000;" \ 847 "bootm $loadaddr $ramdiskaddr $fdtaddr" 848 849 #define CONFIG_HDBOOT \ 850 "setenv bootargs root=/dev/$bdev rw " \ 851 "console=$consoledev,$baudrate $othbootargs;" \ 852 "tftp $loadaddr $bootfile;" \ 853 "tftp $fdtaddr $fdtfile;" \ 854 "bootm $loadaddr - $fdtaddr" 855 856 #define CONFIG_NFSBOOTCOMMAND \ 857 "setenv bootargs root=/dev/nfs rw " \ 858 "nfsroot=$serverip:$rootpath " \ 859 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 860 "console=$consoledev,$baudrate $othbootargs;" \ 861 "tftp $loadaddr $bootfile;" \ 862 "tftp $fdtaddr $fdtfile;" \ 863 "bootm $loadaddr - $fdtaddr" 864 865 #define CONFIG_RAMBOOTCOMMAND \ 866 "setenv bootargs root=/dev/ram rw " \ 867 "console=$consoledev,$baudrate $othbootargs;" \ 868 "tftp $ramdiskaddr $ramdiskfile;" \ 869 "tftp $loadaddr $bootfile;" \ 870 "tftp $fdtaddr $fdtfile;" \ 871 "bootm $loadaddr $ramdiskaddr $fdtaddr" 872 873 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 874 875 #include <asm/fsl_secure_boot.h> 876 877 #endif /* __T208xQDS_H */ 878