xref: /openbmc/u-boot/include/configs/T208xQDS.h (revision 85187b80)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2011-2013 Freescale Semiconductor, Inc.
4  */
5 
6 /*
7  * T2080/T2081 QDS board configuration file
8  */
9 
10 #ifndef __T208xQDS_H
11 #define __T208xQDS_H
12 
13 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
14 #if defined(CONFIG_ARCH_T2080)
15 #define CONFIG_FSL_SATA_V2
16 #define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
17 #define CONFIG_SRIO1		/* SRIO port 1 */
18 #define CONFIG_SRIO2		/* SRIO port 2 */
19 #elif defined(CONFIG_ARCH_T2081)
20 #endif
21 
22 /* High Level Configuration Options */
23 #define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
24 #define CONFIG_MP		/* support multiple processors */
25 #define CONFIG_ENABLE_36BIT_PHYS
26 
27 #ifdef CONFIG_PHYS_64BIT
28 #define CONFIG_ADDR_MAP 1
29 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
30 #endif
31 
32 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
33 #define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
34 #define CONFIG_ENV_OVERWRITE
35 
36 #ifdef CONFIG_RAMBOOT_PBL
37 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
38 
39 #define CONFIG_SPL_FLUSH_IMAGE
40 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
41 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
42 #define CONFIG_SPL_PAD_TO		0x40000
43 #define CONFIG_SPL_MAX_SIZE		0x28000
44 #define RESET_VECTOR_OFFSET		0x27FFC
45 #define BOOT_PAGE_OFFSET		0x27000
46 #ifdef CONFIG_SPL_BUILD
47 #define CONFIG_SPL_SKIP_RELOCATE
48 #define CONFIG_SPL_COMMON_INIT_DDR
49 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
50 #endif
51 
52 #ifdef CONFIG_NAND
53 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
54 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
55 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
56 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
57 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
58 #if defined(CONFIG_ARCH_T2080)
59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
60 #elif defined(CONFIG_ARCH_T2081)
61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
62 #endif
63 #define CONFIG_SPL_NAND_BOOT
64 #endif
65 
66 #ifdef CONFIG_SPIFLASH
67 #define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
68 #define CONFIG_SPL_SPI_FLASH_MINIMAL
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
73 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
74 #ifndef CONFIG_SPL_BUILD
75 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
76 #endif
77 #if defined(CONFIG_ARCH_T2080)
78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
79 #elif defined(CONFIG_ARCH_T2081)
80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
81 #endif
82 #define CONFIG_SPL_SPI_BOOT
83 #endif
84 
85 #ifdef CONFIG_SDCARD
86 #define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
87 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
88 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
89 #define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
90 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
91 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
92 #ifndef CONFIG_SPL_BUILD
93 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
94 #endif
95 #if defined(CONFIG_ARCH_T2080)
96 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
97 #elif defined(CONFIG_ARCH_T2081)
98 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
99 #endif
100 #define CONFIG_SPL_MMC_BOOT
101 #endif
102 
103 #endif /* CONFIG_RAMBOOT_PBL */
104 
105 #define CONFIG_SRIO_PCIE_BOOT_MASTER
106 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
107 /* Set 1M boot space */
108 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
109 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
110 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
111 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
112 #endif
113 
114 #ifndef CONFIG_RESET_VECTOR_ADDRESS
115 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
116 #endif
117 
118 /*
119  * These can be toggled for performance analysis, otherwise use default.
120  */
121 #define CONFIG_SYS_CACHE_STASHING
122 #define CONFIG_BTB		/* toggle branch predition */
123 #define CONFIG_DDR_ECC
124 #ifdef CONFIG_DDR_ECC
125 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
126 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
127 #endif
128 
129 #ifdef CONFIG_MTD_NOR_FLASH
130 #define CONFIG_FLASH_CFI_DRIVER
131 #define CONFIG_SYS_FLASH_CFI
132 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
133 #endif
134 
135 #if defined(CONFIG_SPIFLASH)
136 #define CONFIG_SYS_EXTRA_ENV_RELOC
137 #define CONFIG_ENV_SPI_BUS	0
138 #define CONFIG_ENV_SPI_CS	0
139 #define CONFIG_ENV_SPI_MAX_HZ	10000000
140 #define CONFIG_ENV_SPI_MODE	0
141 #define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
142 #define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
143 #define CONFIG_ENV_SECT_SIZE	0x10000
144 #elif defined(CONFIG_SDCARD)
145 #define CONFIG_SYS_EXTRA_ENV_RELOC
146 #define CONFIG_SYS_MMC_ENV_DEV	0
147 #define CONFIG_ENV_SIZE		0x2000
148 #define CONFIG_ENV_OFFSET	(512 * 0x800)
149 #elif defined(CONFIG_NAND)
150 #define CONFIG_SYS_EXTRA_ENV_RELOC
151 #define CONFIG_ENV_SIZE		0x2000
152 #define CONFIG_ENV_OFFSET	(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
153 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
154 #define CONFIG_ENV_ADDR		0xffe20000
155 #define CONFIG_ENV_SIZE		0x2000
156 #elif defined(CONFIG_ENV_IS_NOWHERE)
157 #define CONFIG_ENV_SIZE		0x2000
158 #else
159 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
160 #define CONFIG_ENV_SIZE		0x2000
161 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
162 #endif
163 
164 #ifndef __ASSEMBLY__
165 unsigned long get_board_sys_clk(void);
166 unsigned long get_board_ddr_clk(void);
167 #endif
168 
169 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
170 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
171 
172 /*
173  * Config the L3 Cache as L3 SRAM
174  */
175 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
176 #define CONFIG_SYS_L3_SIZE		(512 << 10)
177 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
178 #ifdef CONFIG_RAMBOOT_PBL
179 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
180 #endif
181 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
182 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
183 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
184 #define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
185 
186 #define CONFIG_SYS_DCSRBAR	0xf0000000
187 #define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
188 
189 /* EEPROM */
190 #define CONFIG_ID_EEPROM
191 #define CONFIG_SYS_I2C_EEPROM_NXID
192 #define CONFIG_SYS_EEPROM_BUS_NUM	0
193 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
194 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
195 
196 /*
197  * DDR Setup
198  */
199 #define CONFIG_VERY_BIG_RAM
200 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
201 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
202 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
203 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
204 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
205 #define CONFIG_DDR_SPD
206 #define CONFIG_FSL_DDR_INTERACTIVE
207 #define CONFIG_SYS_SPD_BUS_NUM	0
208 #define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
209 #define SPD_EEPROM_ADDRESS1	0x51
210 #define SPD_EEPROM_ADDRESS2	0x52
211 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
212 #define CTRL_INTLV_PREFERED	cacheline
213 
214 /*
215  * IFC Definitions
216  */
217 #define CONFIG_SYS_FLASH_BASE		0xe0000000
218 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
219 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
220 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
221 				+ 0x8000000) | \
222 				CSPR_PORT_SIZE_16 | \
223 				CSPR_MSEL_NOR | \
224 				CSPR_V)
225 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
226 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
227 				CSPR_PORT_SIZE_16 | \
228 				CSPR_MSEL_NOR | \
229 				CSPR_V)
230 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
231 /* NOR Flash Timing Params */
232 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
233 
234 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
235 				FTIM0_NOR_TEADC(0x5) | \
236 				FTIM0_NOR_TEAHC(0x5))
237 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
238 				FTIM1_NOR_TRAD_NOR(0x1A) |\
239 				FTIM1_NOR_TSEQRAD_NOR(0x13))
240 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
241 				FTIM2_NOR_TCH(0x4) | \
242 				FTIM2_NOR_TWPH(0x0E) | \
243 				FTIM2_NOR_TWP(0x1c))
244 #define CONFIG_SYS_NOR_FTIM3	0x0
245 
246 #define CONFIG_SYS_FLASH_QUIET_TEST
247 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
248 
249 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
250 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
251 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
252 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
253 
254 #define CONFIG_SYS_FLASH_EMPTY_INFO
255 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
256 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
257 
258 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
259 #define QIXIS_BASE			0xffdf0000
260 #define QIXIS_LBMAP_SWITCH		6
261 #define QIXIS_LBMAP_MASK		0x0f
262 #define QIXIS_LBMAP_SHIFT		0
263 #define QIXIS_LBMAP_DFLTBANK		0x00
264 #define QIXIS_LBMAP_ALTBANK		0x04
265 #define QIXIS_LBMAP_NAND		0x09
266 #define QIXIS_LBMAP_SD			0x00
267 #define QIXIS_RCW_SRC_NAND		0x104
268 #define QIXIS_RCW_SRC_SD		0x040
269 #define QIXIS_RST_CTL_RESET		0x83
270 #define QIXIS_RST_FORCE_MEM		0x1
271 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
272 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
273 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
274 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
275 
276 #define CONFIG_SYS_CSPR3_EXT	(0xf)
277 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
278 				| CSPR_PORT_SIZE_8 \
279 				| CSPR_MSEL_GPCM \
280 				| CSPR_V)
281 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
282 #define CONFIG_SYS_CSOR3	0x0
283 /* QIXIS Timing parameters for IFC CS3 */
284 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
285 					FTIM0_GPCM_TEADC(0x0e) | \
286 					FTIM0_GPCM_TEAHC(0x0e))
287 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
288 					FTIM1_GPCM_TRAD(0x3f))
289 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
290 					FTIM2_GPCM_TCH(0x8) | \
291 					FTIM2_GPCM_TWP(0x1f))
292 #define CONFIG_SYS_CS3_FTIM3		0x0
293 
294 /* NAND Flash on IFC */
295 #define CONFIG_NAND_FSL_IFC
296 #define CONFIG_SYS_NAND_BASE		0xff800000
297 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
298 
299 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
300 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
301 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
302 				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
303 				| CSPR_V)
304 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
305 
306 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
307 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
308 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
309 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
310 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
311 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
312 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
313 
314 #define CONFIG_SYS_NAND_ONFI_DETECTION
315 
316 /* ONFI NAND Flash mode0 Timing Params */
317 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
318 					FTIM0_NAND_TWP(0x18)    | \
319 					FTIM0_NAND_TWCHT(0x07)  | \
320 					FTIM0_NAND_TWH(0x0a))
321 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
322 					FTIM1_NAND_TWBE(0x39)   | \
323 					FTIM1_NAND_TRR(0x0e)    | \
324 					FTIM1_NAND_TRP(0x18))
325 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
326 					FTIM2_NAND_TREH(0x0a)   | \
327 					FTIM2_NAND_TWHRE(0x1e))
328 #define CONFIG_SYS_NAND_FTIM3		0x0
329 
330 #define CONFIG_SYS_NAND_DDR_LAW		11
331 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
332 #define CONFIG_SYS_MAX_NAND_DEVICE	1
333 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
334 
335 #if defined(CONFIG_NAND)
336 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
337 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
338 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
339 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
340 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
341 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
342 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
343 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
344 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
345 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
346 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
347 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
348 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
349 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
350 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
351 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
352 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
353 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
354 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
355 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
356 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
357 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
358 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
359 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
360 #else
361 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
362 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
363 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
364 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
365 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
366 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
367 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
368 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
369 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
370 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
371 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
372 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
373 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
374 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
375 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
376 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
377 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
378 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
379 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
380 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
381 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
382 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
383 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
384 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
385 #endif
386 
387 #if defined(CONFIG_RAMBOOT_PBL)
388 #define CONFIG_SYS_RAMBOOT
389 #endif
390 
391 #ifdef CONFIG_SPL_BUILD
392 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
393 #else
394 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
395 #endif
396 
397 #define CONFIG_MISC_INIT_R
398 #define CONFIG_HWCONFIG
399 
400 /* define to use L1 as initial stack */
401 #define CONFIG_L1_INIT_RAM
402 #define CONFIG_SYS_INIT_RAM_LOCK
403 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
404 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
405 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
406 /* The assembler doesn't like typecast */
407 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
408 			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
409 			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
410 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
411 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
412 						GENERATED_GBL_DATA_SIZE)
413 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
414 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
415 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
416 
417 /*
418  * Serial Port
419  */
420 #define CONFIG_SYS_NS16550_SERIAL
421 #define CONFIG_SYS_NS16550_REG_SIZE	1
422 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
423 #define CONFIG_SYS_BAUDRATE_TABLE	\
424 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
425 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
426 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
427 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
428 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
429 
430 /*
431  * I2C
432  */
433 #define CONFIG_SYS_I2C
434 #define CONFIG_SYS_I2C_FSL
435 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
436 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
437 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
438 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
439 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
440 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
441 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
442 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
443 #define CONFIG_SYS_FSL_I2C_SPEED   100000
444 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
445 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
446 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
447 #define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
448 #define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
449 #define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
450 #define I2C_MUX_CH_DEFAULT	0x8
451 
452 #define I2C_MUX_CH_VOL_MONITOR 0xa
453 
454 /* Voltage monitor on channel 2*/
455 #define I2C_VOL_MONITOR_ADDR           0x40
456 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
457 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
458 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
459 
460 #define CONFIG_VID_FLS_ENV		"t208xqds_vdd_mv"
461 #ifndef CONFIG_SPL_BUILD
462 #define CONFIG_VID
463 #endif
464 #define CONFIG_VOL_MONITOR_IR36021_SET
465 #define CONFIG_VOL_MONITOR_IR36021_READ
466 /* The lowest and highest voltage allowed for T208xQDS */
467 #define VDD_MV_MIN			819
468 #define VDD_MV_MAX			1212
469 
470 /*
471  * RapidIO
472  */
473 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
474 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
475 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
476 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
477 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
478 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
479 /*
480  * for slave u-boot IMAGE instored in master memory space,
481  * PHYS must be aligned based on the SIZE
482  */
483 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
484 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
485 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
486 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
487 /*
488  * for slave UCODE and ENV instored in master memory space,
489  * PHYS must be aligned based on the SIZE
490  */
491 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
492 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
493 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
494 
495 /* slave core release by master*/
496 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
497 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
498 
499 /*
500  * SRIO_PCIE_BOOT - SLAVE
501  */
502 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
503 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
504 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
505 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
506 #endif
507 
508 /*
509  * eSPI - Enhanced SPI
510  */
511 #ifdef CONFIG_SPI_FLASH
512 #ifndef CONFIG_SPL_BUILD
513 #endif
514 
515 #define CONFIG_SPI_FLASH_BAR
516 #define CONFIG_SF_DEFAULT_SPEED	 10000000
517 #define CONFIG_SF_DEFAULT_MODE	  0
518 #endif
519 
520 /*
521  * General PCI
522  * Memory space is mapped 1-1, but I/O space must start from 0.
523  */
524 #define CONFIG_PCIE1		/* PCIE controller 1 */
525 #define CONFIG_PCIE2		/* PCIE controller 2 */
526 #define CONFIG_PCIE3		/* PCIE controller 3 */
527 #define CONFIG_PCIE4		/* PCIE controller 4 */
528 #define CONFIG_FSL_PCIE_RESET   /* pcie reset fix link width 2x-4x*/
529 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
530 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
531 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
532 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
533 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
534 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
535 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
536 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
537 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
538 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
539 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
540 
541 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
542 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
543 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
544 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
545 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
546 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
547 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
548 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
549 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
550 
551 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
552 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
553 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
554 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
555 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
556 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
557 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
558 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
559 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
560 
561 /* controller 4, Base address 203000 */
562 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
563 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
564 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
565 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
566 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
567 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
568 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
569 
570 #ifdef CONFIG_PCI
571 #define CONFIG_PCI_INDIRECT_BRIDGE
572 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
573 #endif
574 
575 /* Qman/Bman */
576 #ifndef CONFIG_NOBQFMAN
577 #define CONFIG_SYS_BMAN_NUM_PORTALS	18
578 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
579 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
580 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
581 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
582 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
583 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
584 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
585 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
586 					CONFIG_SYS_BMAN_CENA_SIZE)
587 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
588 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
589 #define CONFIG_SYS_QMAN_NUM_PORTALS	18
590 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
591 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
592 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
593 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
594 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
595 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
596 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
597 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
598 					CONFIG_SYS_QMAN_CENA_SIZE)
599 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
600 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
601 
602 #define CONFIG_SYS_DPAA_FMAN
603 #define CONFIG_SYS_DPAA_PME
604 #define CONFIG_SYS_PMAN
605 #define CONFIG_SYS_DPAA_DCE
606 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
607 #define CONFIG_SYS_INTERLAKEN
608 
609 /* Default address of microcode for the Linux Fman driver */
610 #if defined(CONFIG_SPIFLASH)
611 /*
612  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
613  * env, so we got 0x110000.
614  */
615 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
616 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
617 #elif defined(CONFIG_SDCARD)
618 /*
619  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
620  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
621  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
622  */
623 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
624 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
625 #elif defined(CONFIG_NAND)
626 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
627 #define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
628 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
629 /*
630  * Slave has no ucode locally, it can fetch this from remote. When implementing
631  * in two corenet boards, slave's ucode could be stored in master's memory
632  * space, the address can be mapped from slave TLB->slave LAW->
633  * slave SRIO or PCIE outbound window->master inbound window->
634  * master LAW->the ucode address in master's memory space.
635  */
636 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
637 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
638 #else
639 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
640 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
641 #endif
642 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
643 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
644 #endif /* CONFIG_NOBQFMAN */
645 
646 #ifdef CONFIG_SYS_DPAA_FMAN
647 #define CONFIG_FMAN_ENET
648 #define CONFIG_PHYLIB_10G
649 #define CONFIG_PHY_VITESSE
650 #define CONFIG_PHY_REALTEK
651 #define CONFIG_PHY_TERANETICS
652 #define RGMII_PHY1_ADDR	0x1
653 #define RGMII_PHY2_ADDR	0x2
654 #define FM1_10GEC1_PHY_ADDR	  0x3
655 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
656 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
657 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
658 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
659 #endif
660 
661 #ifdef CONFIG_FMAN_ENET
662 #define CONFIG_MII		/* MII PHY management */
663 #define CONFIG_ETHPRIME		"FM1@DTSEC3"
664 #endif
665 
666 /*
667  * SATA
668  */
669 #ifdef CONFIG_FSL_SATA_V2
670 #define CONFIG_SYS_SATA_MAX_DEVICE	2
671 #define CONFIG_SATA1
672 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
673 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
674 #define CONFIG_SATA2
675 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
676 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
677 #define CONFIG_LBA48
678 #endif
679 
680 /*
681  * USB
682  */
683 #ifdef CONFIG_USB_EHCI_HCD
684 #define CONFIG_USB_EHCI_FSL
685 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
686 #define CONFIG_HAS_FSL_DR_USB
687 #endif
688 
689 /*
690  * SDHC
691  */
692 #ifdef CONFIG_MMC
693 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
694 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
695 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
696 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
697 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
698 #endif
699 
700 /*
701  * Dynamic MTD Partition support with mtdparts
702  */
703 #ifdef CONFIG_MTD_NOR_FLASH
704 #define CONFIG_MTD_DEVICE
705 #define CONFIG_MTD_PARTITIONS
706 #define CONFIG_FLASH_CFI_MTD
707 #endif
708 
709 /*
710  * Environment
711  */
712 #define CONFIG_LOADS_ECHO	/* echo on for serial download */
713 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
714 
715 /*
716  * Miscellaneous configurable options
717  */
718 #define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
719 
720 /*
721  * For booting Linux, the board info and command line data
722  * have to be in the first 64 MB of memory, since this is
723  * the maximum mapped by the Linux kernel during initialization.
724  */
725 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
726 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
727 
728 #ifdef CONFIG_CMD_KGDB
729 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
730 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
731 #endif
732 
733 /*
734  * Environment Configuration
735  */
736 #define CONFIG_ROOTPATH	 "/opt/nfsroot"
737 #define CONFIG_BOOTFILE	 "uImage"
738 #define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
739 
740 /* default location for tftp and bootm */
741 #define CONFIG_LOADADDR		1000000
742 #define __USB_PHY_TYPE		utmi
743 
744 #define	CONFIG_EXTRA_ENV_SETTINGS				\
745 	"hwconfig=fsl_ddr:"					\
746 	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
747 	"bank_intlv=auto;"					\
748 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
749 	"netdev=eth0\0"						\
750 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
751 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
752 	"tftpflash=tftpboot $loadaddr $uboot && "		\
753 	"protect off $ubootaddr +$filesize && "			\
754 	"erase $ubootaddr +$filesize && "			\
755 	"cp.b $loadaddr $ubootaddr $filesize && "		\
756 	"protect on $ubootaddr +$filesize && "			\
757 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
758 	"consoledev=ttyS0\0"					\
759 	"ramdiskaddr=2000000\0"					\
760 	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
761 	"fdtaddr=1e00000\0"					\
762 	"fdtfile=t2080qds/t2080qds.dtb\0"			\
763 	"bdev=sda3\0"
764 
765 /*
766  * For emulation this causes u-boot to jump to the start of the
767  * proof point app code automatically
768  */
769 #define CONFIG_PROOF_POINTS				\
770 	"setenv bootargs root=/dev/$bdev rw "		\
771 	"console=$consoledev,$baudrate $othbootargs;"	\
772 	"cpu 1 release 0x29000000 - - -;"		\
773 	"cpu 2 release 0x29000000 - - -;"		\
774 	"cpu 3 release 0x29000000 - - -;"		\
775 	"cpu 4 release 0x29000000 - - -;"		\
776 	"cpu 5 release 0x29000000 - - -;"		\
777 	"cpu 6 release 0x29000000 - - -;"		\
778 	"cpu 7 release 0x29000000 - - -;"		\
779 	"go 0x29000000"
780 
781 #define CONFIG_HVBOOT				\
782 	"setenv bootargs config-addr=0x60000000; "	\
783 	"bootm 0x01000000 - 0x00f00000"
784 
785 #define CONFIG_ALU				\
786 	"setenv bootargs root=/dev/$bdev rw "		\
787 	"console=$consoledev,$baudrate $othbootargs;"	\
788 	"cpu 1 release 0x01000000 - - -;"		\
789 	"cpu 2 release 0x01000000 - - -;"		\
790 	"cpu 3 release 0x01000000 - - -;"		\
791 	"cpu 4 release 0x01000000 - - -;"		\
792 	"cpu 5 release 0x01000000 - - -;"		\
793 	"cpu 6 release 0x01000000 - - -;"		\
794 	"cpu 7 release 0x01000000 - - -;"		\
795 	"go 0x01000000"
796 
797 #define CONFIG_LINUX				\
798 	"setenv bootargs root=/dev/ram rw "		\
799 	"console=$consoledev,$baudrate $othbootargs;"	\
800 	"setenv ramdiskaddr 0x02000000;"		\
801 	"setenv fdtaddr 0x00c00000;"			\
802 	"setenv loadaddr 0x1000000;"			\
803 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
804 
805 #define CONFIG_HDBOOT					\
806 	"setenv bootargs root=/dev/$bdev rw "		\
807 	"console=$consoledev,$baudrate $othbootargs;"	\
808 	"tftp $loadaddr $bootfile;"			\
809 	"tftp $fdtaddr $fdtfile;"			\
810 	"bootm $loadaddr - $fdtaddr"
811 
812 #define CONFIG_NFSBOOTCOMMAND			\
813 	"setenv bootargs root=/dev/nfs rw "	\
814 	"nfsroot=$serverip:$rootpath "		\
815 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
816 	"console=$consoledev,$baudrate $othbootargs;"	\
817 	"tftp $loadaddr $bootfile;"		\
818 	"tftp $fdtaddr $fdtfile;"		\
819 	"bootm $loadaddr - $fdtaddr"
820 
821 #define CONFIG_RAMBOOTCOMMAND				\
822 	"setenv bootargs root=/dev/ram rw "		\
823 	"console=$consoledev,$baudrate $othbootargs;"	\
824 	"tftp $ramdiskaddr $ramdiskfile;"		\
825 	"tftp $loadaddr $bootfile;"			\
826 	"tftp $fdtaddr $fdtfile;"			\
827 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
828 
829 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
830 
831 #include <asm/fsl_secure_boot.h>
832 
833 #endif	/* __T208xQDS_H */
834