xref: /openbmc/u-boot/include/configs/T208xQDS.h (revision 8435179271106ec6fe9a9a5679b897755b1db8dd)
1 /*
2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 /*
8  * T2080/T2081 QDS board configuration file
9  */
10 
11 #ifndef __T208xQDS_H
12 #define __T208xQDS_H
13 
14 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
15 #define CONFIG_MMC
16 #define CONFIG_USB_EHCI
17 #if defined(CONFIG_PPC_T2080)
18 #define CONFIG_T2080QDS
19 #define CONFIG_FSL_SATA_V2
20 #define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
21 #define CONFIG_SRIO1		/* SRIO port 1 */
22 #define CONFIG_SRIO2		/* SRIO port 2 */
23 #elif defined(CONFIG_PPC_T2081)
24 #define CONFIG_T2081QDS
25 #endif
26 
27 /* High Level Configuration Options */
28 #define CONFIG_BOOKE
29 #define CONFIG_E500		/* BOOKE e500 family */
30 #define CONFIG_E500MC		/* BOOKE e500mc family */
31 #define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
32 #define CONFIG_MP		/* support multiple processors */
33 #define CONFIG_ENABLE_36BIT_PHYS
34 
35 #ifdef CONFIG_PHYS_64BIT
36 #define CONFIG_ADDR_MAP 1
37 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
38 #endif
39 
40 #define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
41 #define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
42 #define CONFIG_FSL_IFC		/* Enable IFC Support */
43 #define CONFIG_FSL_CAAM		/* Enable SEC/CAAM */
44 #define CONFIG_FSL_LAW		/* Use common FSL init code */
45 #define CONFIG_ENV_OVERWRITE
46 
47 #ifdef CONFIG_RAMBOOT_PBL
48 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
49 #if defined(CONFIG_PPC_T2080)
50 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
51 #elif defined(CONFIG_PPC_T2081)
52 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
53 #endif
54 
55 #define CONFIG_SPL_FLUSH_IMAGE
56 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
57 #define CONFIG_FSL_LAW			/* Use common FSL init code */
58 #define CONFIG_SYS_TEXT_BASE		0x00201000
59 #define CONFIG_SPL_TEXT_BASE		0xFFFD8000
60 #define CONFIG_SPL_PAD_TO		0x40000
61 #define CONFIG_SPL_MAX_SIZE		0x28000
62 #define RESET_VECTOR_OFFSET		0x27FFC
63 #define BOOT_PAGE_OFFSET		0x27000
64 #ifdef CONFIG_SPL_BUILD
65 #define CONFIG_SPL_SKIP_RELOCATE
66 #define CONFIG_SPL_COMMON_INIT_DDR
67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
68 #define CONFIG_SYS_NO_FLASH
69 #endif
70 
71 #ifdef CONFIG_NAND
72 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
73 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
74 #define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
75 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
76 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
77 #define CONFIG_SPL_NAND_BOOT
78 #endif
79 
80 #ifdef CONFIG_SPIFLASH
81 #define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
82 #define CONFIG_SPL_SPI_FLASH_MINIMAL
83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
85 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
86 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
87 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
88 #ifndef CONFIG_SPL_BUILD
89 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
90 #endif
91 #define CONFIG_SPL_SPI_BOOT
92 #endif
93 
94 #ifdef CONFIG_SDCARD
95 #define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
96 #define CONFIG_SPL_MMC_MINIMAL
97 #define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
98 #define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
99 #define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
100 #define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
101 #define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
102 #ifndef CONFIG_SPL_BUILD
103 #define	CONFIG_SYS_MPC85XX_NO_RESETVEC
104 #endif
105 #define CONFIG_SPL_MMC_BOOT
106 #endif
107 
108 #endif /* CONFIG_RAMBOOT_PBL */
109 
110 #define CONFIG_SRIO_PCIE_BOOT_MASTER
111 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
112 /* Set 1M boot space */
113 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
114 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
115 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
116 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
117 #define CONFIG_SYS_NO_FLASH
118 #endif
119 
120 #ifndef CONFIG_SYS_TEXT_BASE
121 #define CONFIG_SYS_TEXT_BASE	0xeff40000
122 #endif
123 
124 #ifndef CONFIG_RESET_VECTOR_ADDRESS
125 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
126 #endif
127 
128 /*
129  * These can be toggled for performance analysis, otherwise use default.
130  */
131 #define CONFIG_SYS_CACHE_STASHING
132 #define CONFIG_BTB		/* toggle branch predition */
133 #define CONFIG_DDR_ECC
134 #ifdef CONFIG_DDR_ECC
135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
136 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
137 #endif
138 
139 #ifndef CONFIG_SYS_NO_FLASH
140 #define CONFIG_FLASH_CFI_DRIVER
141 #define CONFIG_SYS_FLASH_CFI
142 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
143 #endif
144 
145 #if defined(CONFIG_SPIFLASH)
146 #define CONFIG_SYS_EXTRA_ENV_RELOC
147 #define CONFIG_ENV_IS_IN_SPI_FLASH
148 #define CONFIG_ENV_SPI_BUS	0
149 #define CONFIG_ENV_SPI_CS	0
150 #define CONFIG_ENV_SPI_MAX_HZ	10000000
151 #define CONFIG_ENV_SPI_MODE	0
152 #define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
153 #define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
154 #define CONFIG_ENV_SECT_SIZE	0x10000
155 #elif defined(CONFIG_SDCARD)
156 #define CONFIG_SYS_EXTRA_ENV_RELOC
157 #define CONFIG_ENV_IS_IN_MMC
158 #define CONFIG_SYS_MMC_ENV_DEV	0
159 #define CONFIG_ENV_SIZE		0x2000
160 #define CONFIG_ENV_OFFSET	(512 * 0x800)
161 #elif defined(CONFIG_NAND)
162 #define CONFIG_SYS_EXTRA_ENV_RELOC
163 #define CONFIG_ENV_IS_IN_NAND
164 #define CONFIG_ENV_SIZE		0x2000
165 #define CONFIG_ENV_OFFSET	(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
166 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
167 #define CONFIG_ENV_IS_IN_REMOTE
168 #define CONFIG_ENV_ADDR		0xffe20000
169 #define CONFIG_ENV_SIZE		0x2000
170 #elif defined(CONFIG_ENV_IS_NOWHERE)
171 #define CONFIG_ENV_SIZE		0x2000
172 #else
173 #define CONFIG_ENV_IS_IN_FLASH
174 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
175 #define CONFIG_ENV_SIZE		0x2000
176 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
177 #endif
178 
179 #ifndef __ASSEMBLY__
180 unsigned long get_board_sys_clk(void);
181 unsigned long get_board_ddr_clk(void);
182 #endif
183 
184 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
185 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
186 
187 /*
188  * Config the L3 Cache as L3 SRAM
189  */
190 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
191 #define CONFIG_SYS_L3_SIZE		(512 << 10)
192 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
193 #ifdef CONFIG_RAMBOOT_PBL
194 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
195 #endif
196 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
197 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
198 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
199 #define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
200 
201 #define CONFIG_SYS_DCSRBAR	0xf0000000
202 #define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
203 
204 /* EEPROM */
205 #define CONFIG_ID_EEPROM
206 #define CONFIG_SYS_I2C_EEPROM_NXID
207 #define CONFIG_SYS_EEPROM_BUS_NUM	0
208 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
209 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
210 
211 /*
212  * DDR Setup
213  */
214 #define CONFIG_VERY_BIG_RAM
215 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
216 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
217 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
218 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
219 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
220 #define CONFIG_DDR_SPD
221 #define CONFIG_SYS_FSL_DDR3
222 #define CONFIG_FSL_DDR_INTERACTIVE
223 #define CONFIG_SYS_SPD_BUS_NUM	0
224 #define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
225 #define SPD_EEPROM_ADDRESS1	0x51
226 #define SPD_EEPROM_ADDRESS2	0x52
227 #define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
228 #define CTRL_INTLV_PREFERED	cacheline
229 
230 /*
231  * IFC Definitions
232  */
233 #define CONFIG_SYS_FLASH_BASE		0xe0000000
234 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
235 #define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
236 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
237 				+ 0x8000000) | \
238 				CSPR_PORT_SIZE_16 | \
239 				CSPR_MSEL_NOR | \
240 				CSPR_V)
241 #define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
242 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
243 				CSPR_PORT_SIZE_16 | \
244 				CSPR_MSEL_NOR | \
245 				CSPR_V)
246 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
247 /* NOR Flash Timing Params */
248 #define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
249 
250 #define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
251 				FTIM0_NOR_TEADC(0x5) | \
252 				FTIM0_NOR_TEAHC(0x5))
253 #define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
254 				FTIM1_NOR_TRAD_NOR(0x1A) |\
255 				FTIM1_NOR_TSEQRAD_NOR(0x13))
256 #define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
257 				FTIM2_NOR_TCH(0x4) | \
258 				FTIM2_NOR_TWPH(0x0E) | \
259 				FTIM2_NOR_TWP(0x1c))
260 #define CONFIG_SYS_NOR_FTIM3	0x0
261 
262 #define CONFIG_SYS_FLASH_QUIET_TEST
263 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
264 
265 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
266 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
267 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
268 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
269 
270 #define CONFIG_SYS_FLASH_EMPTY_INFO
271 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
272 					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
273 
274 #define CONFIG_FSL_QIXIS	/* use common QIXIS code */
275 #define QIXIS_BASE			0xffdf0000
276 #define QIXIS_LBMAP_SWITCH		6
277 #define QIXIS_LBMAP_MASK		0x0f
278 #define QIXIS_LBMAP_SHIFT		0
279 #define QIXIS_LBMAP_DFLTBANK		0x00
280 #define QIXIS_LBMAP_ALTBANK		0x04
281 #define QIXIS_LBMAP_NAND		0x09
282 #define QIXIS_LBMAP_SD			0x00
283 #define QIXIS_RCW_SRC_NAND		0x104
284 #define QIXIS_RCW_SRC_SD		0x040
285 #define QIXIS_RST_CTL_RESET		0x83
286 #define QIXIS_RST_FORCE_MEM		0x1
287 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
288 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
289 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
290 #define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
291 
292 #define CONFIG_SYS_CSPR3_EXT	(0xf)
293 #define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
294 				| CSPR_PORT_SIZE_8 \
295 				| CSPR_MSEL_GPCM \
296 				| CSPR_V)
297 #define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
298 #define CONFIG_SYS_CSOR3	0x0
299 /* QIXIS Timing parameters for IFC CS3 */
300 #define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
301 					FTIM0_GPCM_TEADC(0x0e) | \
302 					FTIM0_GPCM_TEAHC(0x0e))
303 #define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
304 					FTIM1_GPCM_TRAD(0x3f))
305 #define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
306 					FTIM2_GPCM_TCH(0x8) | \
307 					FTIM2_GPCM_TWP(0x1f))
308 #define CONFIG_SYS_CS3_FTIM3		0x0
309 
310 /* NAND Flash on IFC */
311 #define CONFIG_NAND_FSL_IFC
312 #define CONFIG_SYS_NAND_BASE		0xff800000
313 #define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
314 
315 #define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
316 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
317 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
318 				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
319 				| CSPR_V)
320 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
321 
322 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
323 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
324 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
325 				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
326 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
327 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
328 				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
329 
330 #define CONFIG_SYS_NAND_ONFI_DETECTION
331 
332 /* ONFI NAND Flash mode0 Timing Params */
333 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
334 					FTIM0_NAND_TWP(0x18)    | \
335 					FTIM0_NAND_TWCHT(0x07)  | \
336 					FTIM0_NAND_TWH(0x0a))
337 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
338 					FTIM1_NAND_TWBE(0x39)   | \
339 					FTIM1_NAND_TRR(0x0e)    | \
340 					FTIM1_NAND_TRP(0x18))
341 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
342 					FTIM2_NAND_TREH(0x0a)   | \
343 					FTIM2_NAND_TWHRE(0x1e))
344 #define CONFIG_SYS_NAND_FTIM3		0x0
345 
346 #define CONFIG_SYS_NAND_DDR_LAW		11
347 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
348 #define CONFIG_SYS_MAX_NAND_DEVICE	1
349 #define CONFIG_CMD_NAND
350 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
351 
352 #if defined(CONFIG_NAND)
353 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
354 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
355 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
356 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
357 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
358 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
359 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
360 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
361 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
362 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
363 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
364 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
365 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
366 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
367 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
368 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
369 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
370 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
371 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
372 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
373 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
374 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
375 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
376 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
377 #else
378 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
379 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
380 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
381 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
382 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
383 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
384 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
385 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
386 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
387 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
388 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
389 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
390 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
391 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
392 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
393 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
394 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
395 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
396 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
397 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
398 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
399 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
400 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
401 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
402 #endif
403 
404 #if defined(CONFIG_RAMBOOT_PBL)
405 #define CONFIG_SYS_RAMBOOT
406 #endif
407 
408 #ifdef CONFIG_SPL_BUILD
409 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
410 #else
411 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
412 #endif
413 
414 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
415 #define CONFIG_MISC_INIT_R
416 #define CONFIG_HWCONFIG
417 
418 /* define to use L1 as initial stack */
419 #define CONFIG_L1_INIT_RAM
420 #define CONFIG_SYS_INIT_RAM_LOCK
421 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
424 /* The assembler doesn't like typecast */
425 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
426 			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
427 			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
428 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
429 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
430 						GENERATED_GBL_DATA_SIZE)
431 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
432 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
433 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
434 
435 /*
436  * Serial Port
437  */
438 #define CONFIG_CONS_INDEX		1
439 #define CONFIG_SYS_NS16550_SERIAL
440 #define CONFIG_SYS_NS16550_REG_SIZE	1
441 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
442 #define CONFIG_SYS_BAUDRATE_TABLE	\
443 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
444 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
445 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
446 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
447 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
448 
449 /*
450  * I2C
451  */
452 #define CONFIG_SYS_I2C
453 #define CONFIG_SYS_I2C_FSL
454 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
455 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
456 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
457 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
458 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
459 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
460 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
461 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
462 #define CONFIG_SYS_FSL_I2C_SPEED   100000
463 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
464 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
465 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
466 #define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
467 #define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
468 #define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
469 #define I2C_MUX_CH_DEFAULT	0x8
470 
471 #define I2C_MUX_CH_VOL_MONITOR 0xa
472 
473 /* Voltage monitor on channel 2*/
474 #define I2C_VOL_MONITOR_ADDR           0x40
475 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
476 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
477 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
478 
479 #define CONFIG_VID_FLS_ENV		"t208xqds_vdd_mv"
480 #ifndef CONFIG_SPL_BUILD
481 #define CONFIG_VID
482 #endif
483 #define CONFIG_VOL_MONITOR_IR36021_SET
484 #define CONFIG_VOL_MONITOR_IR36021_READ
485 /* The lowest and highest voltage allowed for T208xQDS */
486 #define VDD_MV_MIN			819
487 #define VDD_MV_MAX			1212
488 
489 /*
490  * RapidIO
491  */
492 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
493 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
494 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
495 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
496 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
497 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
498 /*
499  * for slave u-boot IMAGE instored in master memory space,
500  * PHYS must be aligned based on the SIZE
501  */
502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
504 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
505 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
506 /*
507  * for slave UCODE and ENV instored in master memory space,
508  * PHYS must be aligned based on the SIZE
509  */
510 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
511 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
512 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
513 
514 /* slave core release by master*/
515 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
516 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
517 
518 /*
519  * SRIO_PCIE_BOOT - SLAVE
520  */
521 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
522 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
523 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
524 		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
525 #endif
526 
527 /*
528  * eSPI - Enhanced SPI
529  */
530 #ifdef CONFIG_SPI_FLASH
531 #ifndef CONFIG_SPL_BUILD
532 #endif
533 
534 #define CONFIG_SPI_FLASH_BAR
535 #define CONFIG_SF_DEFAULT_SPEED	 10000000
536 #define CONFIG_SF_DEFAULT_MODE	  0
537 #endif
538 
539 /*
540  * General PCI
541  * Memory space is mapped 1-1, but I/O space must start from 0.
542  */
543 #define CONFIG_PCI		/* Enable PCI/PCIE */
544 #define CONFIG_PCIE1		/* PCIE controller 1 */
545 #define CONFIG_PCIE2		/* PCIE controller 2 */
546 #define CONFIG_PCIE3		/* PCIE controller 3 */
547 #define CONFIG_PCIE4		/* PCIE controller 4 */
548 #define CONFIG_FSL_PCIE_RESET
549 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
550 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
551 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
552 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
553 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
554 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
555 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
556 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
557 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
558 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
559 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
560 
561 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
562 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
563 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
564 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
565 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
566 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
567 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
568 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
569 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
570 
571 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
572 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
573 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
574 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
575 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
576 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
577 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
578 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
579 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
580 
581 /* controller 4, Base address 203000 */
582 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
583 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
584 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
585 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
586 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
587 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
588 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
589 
590 #ifdef CONFIG_PCI
591 #define CONFIG_PCI_INDIRECT_BRIDGE
592 #define CONFIG_FSL_PCIE_RESET	   /* need PCIe reset errata */
593 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
594 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
595 #define CONFIG_DOS_PARTITION
596 #endif
597 
598 /* Qman/Bman */
599 #ifndef CONFIG_NOBQFMAN
600 #define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
601 #define CONFIG_SYS_BMAN_NUM_PORTALS	18
602 #define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
603 #define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
604 #define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
605 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
606 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
607 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
608 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
609 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
610 					CONFIG_SYS_BMAN_CENA_SIZE)
611 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
612 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
613 #define CONFIG_SYS_QMAN_NUM_PORTALS	18
614 #define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
615 #define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
616 #define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
617 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
618 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
619 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
620 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
621 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
622 					CONFIG_SYS_QMAN_CENA_SIZE)
623 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
624 #define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
625 
626 #define CONFIG_SYS_DPAA_FMAN
627 #define CONFIG_SYS_DPAA_PME
628 #define CONFIG_SYS_PMAN
629 #define CONFIG_SYS_DPAA_DCE
630 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
631 #define CONFIG_SYS_INTERLAKEN
632 
633 /* Default address of microcode for the Linux Fman driver */
634 #if defined(CONFIG_SPIFLASH)
635 /*
636  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
637  * env, so we got 0x110000.
638  */
639 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
640 #define CONFIG_SYS_FMAN_FW_ADDR	0x110000
641 #elif defined(CONFIG_SDCARD)
642 /*
643  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
644  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
645  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
646  */
647 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
648 #define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
649 #elif defined(CONFIG_NAND)
650 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
651 #define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
652 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
653 /*
654  * Slave has no ucode locally, it can fetch this from remote. When implementing
655  * in two corenet boards, slave's ucode could be stored in master's memory
656  * space, the address can be mapped from slave TLB->slave LAW->
657  * slave SRIO or PCIE outbound window->master inbound window->
658  * master LAW->the ucode address in master's memory space.
659  */
660 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
661 #define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
662 #else
663 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
664 #define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
665 #endif
666 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
667 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
668 #endif /* CONFIG_NOBQFMAN */
669 
670 #ifdef CONFIG_SYS_DPAA_FMAN
671 #define CONFIG_FMAN_ENET
672 #define CONFIG_PHYLIB_10G
673 #define CONFIG_PHY_VITESSE
674 #define CONFIG_PHY_REALTEK
675 #define CONFIG_PHY_TERANETICS
676 #define RGMII_PHY1_ADDR	0x1
677 #define RGMII_PHY2_ADDR	0x2
678 #define FM1_10GEC1_PHY_ADDR	  0x3
679 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
680 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
681 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
682 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
683 #endif
684 
685 #ifdef CONFIG_FMAN_ENET
686 #define CONFIG_MII		/* MII PHY management */
687 #define CONFIG_ETHPRIME		"FM1@DTSEC3"
688 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
689 #endif
690 
691 /*
692  * SATA
693  */
694 #ifdef CONFIG_FSL_SATA_V2
695 #define CONFIG_LIBATA
696 #define CONFIG_FSL_SATA
697 #define CONFIG_SYS_SATA_MAX_DEVICE	2
698 #define CONFIG_SATA1
699 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
700 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
701 #define CONFIG_SATA2
702 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
703 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
704 #define CONFIG_LBA48
705 #define CONFIG_CMD_SATA
706 #define CONFIG_DOS_PARTITION
707 #endif
708 
709 /*
710  * USB
711  */
712 #ifdef CONFIG_USB_EHCI
713 #define CONFIG_USB_EHCI_FSL
714 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
715 #define CONFIG_HAS_FSL_DR_USB
716 #endif
717 
718 /*
719  * SDHC
720  */
721 #ifdef CONFIG_MMC
722 #define CONFIG_FSL_ESDHC
723 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
724 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
725 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
726 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
727 #define CONFIG_GENERIC_MMC
728 #define CONFIG_DOS_PARTITION
729 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
730 #endif
731 
732 /*
733  * Dynamic MTD Partition support with mtdparts
734  */
735 #ifndef CONFIG_SYS_NO_FLASH
736 #define CONFIG_MTD_DEVICE
737 #define CONFIG_MTD_PARTITIONS
738 #define CONFIG_CMD_MTDPARTS
739 #define CONFIG_FLASH_CFI_MTD
740 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
741 			"spi0=spife110000.0"
742 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
743 			"128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
744 			"5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
745 			"1m(uboot),5m(kernel),128k(dtb),-(user)"
746 #endif
747 
748 /*
749  * Environment
750  */
751 #define CONFIG_LOADS_ECHO	/* echo on for serial download */
752 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
753 
754 /*
755  * Command line configuration.
756  */
757 #define CONFIG_CMD_ERRATA
758 #define CONFIG_CMD_IRQ
759 #define CONFIG_CMD_REGINFO
760 
761 #ifdef CONFIG_PCI
762 #define CONFIG_CMD_PCI
763 #endif
764 
765 /* Hash command with SHA acceleration supported in hardware */
766 #ifdef CONFIG_FSL_CAAM
767 #define CONFIG_CMD_HASH
768 #define CONFIG_SHA_HW_ACCEL
769 #endif
770 
771 /*
772  * Miscellaneous configurable options
773  */
774 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
775 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
776 #define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
777 #define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
778 #ifdef CONFIG_CMD_KGDB
779 #define CONFIG_SYS_CBSIZE	1024	  /* Console I/O Buffer Size */
780 #else
781 #define CONFIG_SYS_CBSIZE	256	  /* Console I/O Buffer Size */
782 #endif
783 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
784 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
785 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
786 
787 /*
788  * For booting Linux, the board info and command line data
789  * have to be in the first 64 MB of memory, since this is
790  * the maximum mapped by the Linux kernel during initialization.
791  */
792 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
793 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
794 
795 #ifdef CONFIG_CMD_KGDB
796 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
797 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
798 #endif
799 
800 /*
801  * Environment Configuration
802  */
803 #define CONFIG_ROOTPATH	 "/opt/nfsroot"
804 #define CONFIG_BOOTFILE	 "uImage"
805 #define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
806 
807 /* default location for tftp and bootm */
808 #define CONFIG_LOADADDR		1000000
809 #define CONFIG_BAUDRATE		115200
810 #define __USB_PHY_TYPE		utmi
811 
812 #define	CONFIG_EXTRA_ENV_SETTINGS				\
813 	"hwconfig=fsl_ddr:"					\
814 	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
815 	"bank_intlv=auto;"					\
816 	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
817 	"netdev=eth0\0"						\
818 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
819 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
820 	"tftpflash=tftpboot $loadaddr $uboot && "		\
821 	"protect off $ubootaddr +$filesize && "			\
822 	"erase $ubootaddr +$filesize && "			\
823 	"cp.b $loadaddr $ubootaddr $filesize && "		\
824 	"protect on $ubootaddr +$filesize && "			\
825 	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
826 	"consoledev=ttyS0\0"					\
827 	"ramdiskaddr=2000000\0"					\
828 	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
829 	"fdtaddr=1e00000\0"					\
830 	"fdtfile=t2080qds/t2080qds.dtb\0"			\
831 	"bdev=sda3\0"
832 
833 /*
834  * For emulation this causes u-boot to jump to the start of the
835  * proof point app code automatically
836  */
837 #define CONFIG_PROOF_POINTS				\
838 	"setenv bootargs root=/dev/$bdev rw "		\
839 	"console=$consoledev,$baudrate $othbootargs;"	\
840 	"cpu 1 release 0x29000000 - - -;"		\
841 	"cpu 2 release 0x29000000 - - -;"		\
842 	"cpu 3 release 0x29000000 - - -;"		\
843 	"cpu 4 release 0x29000000 - - -;"		\
844 	"cpu 5 release 0x29000000 - - -;"		\
845 	"cpu 6 release 0x29000000 - - -;"		\
846 	"cpu 7 release 0x29000000 - - -;"		\
847 	"go 0x29000000"
848 
849 #define CONFIG_HVBOOT				\
850 	"setenv bootargs config-addr=0x60000000; "	\
851 	"bootm 0x01000000 - 0x00f00000"
852 
853 #define CONFIG_ALU				\
854 	"setenv bootargs root=/dev/$bdev rw "		\
855 	"console=$consoledev,$baudrate $othbootargs;"	\
856 	"cpu 1 release 0x01000000 - - -;"		\
857 	"cpu 2 release 0x01000000 - - -;"		\
858 	"cpu 3 release 0x01000000 - - -;"		\
859 	"cpu 4 release 0x01000000 - - -;"		\
860 	"cpu 5 release 0x01000000 - - -;"		\
861 	"cpu 6 release 0x01000000 - - -;"		\
862 	"cpu 7 release 0x01000000 - - -;"		\
863 	"go 0x01000000"
864 
865 #define CONFIG_LINUX				\
866 	"setenv bootargs root=/dev/ram rw "		\
867 	"console=$consoledev,$baudrate $othbootargs;"	\
868 	"setenv ramdiskaddr 0x02000000;"		\
869 	"setenv fdtaddr 0x00c00000;"			\
870 	"setenv loadaddr 0x1000000;"			\
871 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
872 
873 #define CONFIG_HDBOOT					\
874 	"setenv bootargs root=/dev/$bdev rw "		\
875 	"console=$consoledev,$baudrate $othbootargs;"	\
876 	"tftp $loadaddr $bootfile;"			\
877 	"tftp $fdtaddr $fdtfile;"			\
878 	"bootm $loadaddr - $fdtaddr"
879 
880 #define CONFIG_NFSBOOTCOMMAND			\
881 	"setenv bootargs root=/dev/nfs rw "	\
882 	"nfsroot=$serverip:$rootpath "		\
883 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
884 	"console=$consoledev,$baudrate $othbootargs;"	\
885 	"tftp $loadaddr $bootfile;"		\
886 	"tftp $fdtaddr $fdtfile;"		\
887 	"bootm $loadaddr - $fdtaddr"
888 
889 #define CONFIG_RAMBOOTCOMMAND				\
890 	"setenv bootargs root=/dev/ram rw "		\
891 	"console=$consoledev,$baudrate $othbootargs;"	\
892 	"tftp $ramdiskaddr $ramdiskfile;"		\
893 	"tftp $loadaddr $bootfile;"			\
894 	"tftp $fdtaddr $fdtfile;"			\
895 	"bootm $loadaddr $ramdiskaddr $fdtaddr"
896 
897 #define CONFIG_BOOTCOMMAND		CONFIG_LINUX
898 
899 #include <asm/fsl_secure_boot.h>
900 
901 #endif	/* __T208xQDS_H */
902