1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #if defined(CONFIG_ARCH_T2080) 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 18 #define CONFIG_SRIO1 /* SRIO port 1 */ 19 #define CONFIG_SRIO2 /* SRIO port 2 */ 20 #elif defined(CONFIG_ARCH_T2081) 21 #endif 22 23 /* High Level Configuration Options */ 24 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 25 #define CONFIG_MP /* support multiple processors */ 26 #define CONFIG_ENABLE_36BIT_PHYS 27 28 #ifdef CONFIG_PHYS_64BIT 29 #define CONFIG_ADDR_MAP 1 30 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 31 #endif 32 33 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 34 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 35 #define CONFIG_ENV_OVERWRITE 36 37 #ifdef CONFIG_RAMBOOT_PBL 38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 39 40 #define CONFIG_SPL_FLUSH_IMAGE 41 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 42 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 43 #define CONFIG_SPL_PAD_TO 0x40000 44 #define CONFIG_SPL_MAX_SIZE 0x28000 45 #define RESET_VECTOR_OFFSET 0x27FFC 46 #define BOOT_PAGE_OFFSET 0x27000 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SPL_SKIP_RELOCATE 49 #define CONFIG_SPL_COMMON_INIT_DDR 50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 51 #endif 52 53 #ifdef CONFIG_NAND 54 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 55 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 56 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 57 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 59 #if defined(CONFIG_ARCH_T2080) 60 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 61 #elif defined(CONFIG_ARCH_T2081) 62 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 63 #endif 64 #define CONFIG_SPL_NAND_BOOT 65 #endif 66 67 #ifdef CONFIG_SPIFLASH 68 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 69 #define CONFIG_SPL_SPI_FLASH_MINIMAL 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 74 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 75 #ifndef CONFIG_SPL_BUILD 76 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 77 #endif 78 #if defined(CONFIG_ARCH_T2080) 79 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 80 #elif defined(CONFIG_ARCH_T2081) 81 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 82 #endif 83 #define CONFIG_SPL_SPI_BOOT 84 #endif 85 86 #ifdef CONFIG_SDCARD 87 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 88 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 89 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 90 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 91 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 92 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 93 #ifndef CONFIG_SPL_BUILD 94 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 95 #endif 96 #if defined(CONFIG_ARCH_T2080) 97 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 98 #elif defined(CONFIG_ARCH_T2081) 99 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 100 #endif 101 #define CONFIG_SPL_MMC_BOOT 102 #endif 103 104 #endif /* CONFIG_RAMBOOT_PBL */ 105 106 #define CONFIG_SRIO_PCIE_BOOT_MASTER 107 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 108 /* Set 1M boot space */ 109 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 110 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 111 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 112 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 113 #endif 114 115 #ifndef CONFIG_RESET_VECTOR_ADDRESS 116 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 117 #endif 118 119 /* 120 * These can be toggled for performance analysis, otherwise use default. 121 */ 122 #define CONFIG_SYS_CACHE_STASHING 123 #define CONFIG_BTB /* toggle branch predition */ 124 #define CONFIG_DDR_ECC 125 #ifdef CONFIG_DDR_ECC 126 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 127 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 128 #endif 129 130 #ifdef CONFIG_MTD_NOR_FLASH 131 #define CONFIG_FLASH_CFI_DRIVER 132 #define CONFIG_SYS_FLASH_CFI 133 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 134 #endif 135 136 #if defined(CONFIG_SPIFLASH) 137 #define CONFIG_SYS_EXTRA_ENV_RELOC 138 #define CONFIG_ENV_SPI_BUS 0 139 #define CONFIG_ENV_SPI_CS 0 140 #define CONFIG_ENV_SPI_MAX_HZ 10000000 141 #define CONFIG_ENV_SPI_MODE 0 142 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 143 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 144 #define CONFIG_ENV_SECT_SIZE 0x10000 145 #elif defined(CONFIG_SDCARD) 146 #define CONFIG_SYS_EXTRA_ENV_RELOC 147 #define CONFIG_SYS_MMC_ENV_DEV 0 148 #define CONFIG_ENV_SIZE 0x2000 149 #define CONFIG_ENV_OFFSET (512 * 0x800) 150 #elif defined(CONFIG_NAND) 151 #define CONFIG_SYS_EXTRA_ENV_RELOC 152 #define CONFIG_ENV_SIZE 0x2000 153 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 154 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 155 #define CONFIG_ENV_ADDR 0xffe20000 156 #define CONFIG_ENV_SIZE 0x2000 157 #elif defined(CONFIG_ENV_IS_NOWHERE) 158 #define CONFIG_ENV_SIZE 0x2000 159 #else 160 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 161 #define CONFIG_ENV_SIZE 0x2000 162 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 163 #endif 164 165 #ifndef __ASSEMBLY__ 166 unsigned long get_board_sys_clk(void); 167 unsigned long get_board_ddr_clk(void); 168 #endif 169 170 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 171 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 172 173 /* 174 * Config the L3 Cache as L3 SRAM 175 */ 176 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 177 #define CONFIG_SYS_L3_SIZE (512 << 10) 178 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 179 #ifdef CONFIG_RAMBOOT_PBL 180 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 181 #endif 182 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 183 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 184 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 185 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 186 187 #define CONFIG_SYS_DCSRBAR 0xf0000000 188 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 189 190 /* EEPROM */ 191 #define CONFIG_ID_EEPROM 192 #define CONFIG_SYS_I2C_EEPROM_NXID 193 #define CONFIG_SYS_EEPROM_BUS_NUM 0 194 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 195 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 196 197 /* 198 * DDR Setup 199 */ 200 #define CONFIG_VERY_BIG_RAM 201 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 202 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 203 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 204 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 205 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 206 #define CONFIG_DDR_SPD 207 #define CONFIG_FSL_DDR_INTERACTIVE 208 #define CONFIG_SYS_SPD_BUS_NUM 0 209 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 210 #define SPD_EEPROM_ADDRESS1 0x51 211 #define SPD_EEPROM_ADDRESS2 0x52 212 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 213 #define CTRL_INTLV_PREFERED cacheline 214 215 /* 216 * IFC Definitions 217 */ 218 #define CONFIG_SYS_FLASH_BASE 0xe0000000 219 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 220 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 221 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 222 + 0x8000000) | \ 223 CSPR_PORT_SIZE_16 | \ 224 CSPR_MSEL_NOR | \ 225 CSPR_V) 226 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 227 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 228 CSPR_PORT_SIZE_16 | \ 229 CSPR_MSEL_NOR | \ 230 CSPR_V) 231 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 232 /* NOR Flash Timing Params */ 233 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 234 235 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 236 FTIM0_NOR_TEADC(0x5) | \ 237 FTIM0_NOR_TEAHC(0x5)) 238 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 239 FTIM1_NOR_TRAD_NOR(0x1A) |\ 240 FTIM1_NOR_TSEQRAD_NOR(0x13)) 241 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 242 FTIM2_NOR_TCH(0x4) | \ 243 FTIM2_NOR_TWPH(0x0E) | \ 244 FTIM2_NOR_TWP(0x1c)) 245 #define CONFIG_SYS_NOR_FTIM3 0x0 246 247 #define CONFIG_SYS_FLASH_QUIET_TEST 248 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 249 250 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 251 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 252 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 253 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 254 255 #define CONFIG_SYS_FLASH_EMPTY_INFO 256 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 257 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 258 259 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 260 #define QIXIS_BASE 0xffdf0000 261 #define QIXIS_LBMAP_SWITCH 6 262 #define QIXIS_LBMAP_MASK 0x0f 263 #define QIXIS_LBMAP_SHIFT 0 264 #define QIXIS_LBMAP_DFLTBANK 0x00 265 #define QIXIS_LBMAP_ALTBANK 0x04 266 #define QIXIS_LBMAP_NAND 0x09 267 #define QIXIS_LBMAP_SD 0x00 268 #define QIXIS_RCW_SRC_NAND 0x104 269 #define QIXIS_RCW_SRC_SD 0x040 270 #define QIXIS_RST_CTL_RESET 0x83 271 #define QIXIS_RST_FORCE_MEM 0x1 272 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 273 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 274 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 275 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 276 277 #define CONFIG_SYS_CSPR3_EXT (0xf) 278 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 279 | CSPR_PORT_SIZE_8 \ 280 | CSPR_MSEL_GPCM \ 281 | CSPR_V) 282 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 283 #define CONFIG_SYS_CSOR3 0x0 284 /* QIXIS Timing parameters for IFC CS3 */ 285 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 286 FTIM0_GPCM_TEADC(0x0e) | \ 287 FTIM0_GPCM_TEAHC(0x0e)) 288 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 289 FTIM1_GPCM_TRAD(0x3f)) 290 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 291 FTIM2_GPCM_TCH(0x8) | \ 292 FTIM2_GPCM_TWP(0x1f)) 293 #define CONFIG_SYS_CS3_FTIM3 0x0 294 295 /* NAND Flash on IFC */ 296 #define CONFIG_NAND_FSL_IFC 297 #define CONFIG_SYS_NAND_BASE 0xff800000 298 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 299 300 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 301 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 302 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 303 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 304 | CSPR_V) 305 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 306 307 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 308 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 309 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 310 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 311 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 312 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 313 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 314 315 #define CONFIG_SYS_NAND_ONFI_DETECTION 316 317 /* ONFI NAND Flash mode0 Timing Params */ 318 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 319 FTIM0_NAND_TWP(0x18) | \ 320 FTIM0_NAND_TWCHT(0x07) | \ 321 FTIM0_NAND_TWH(0x0a)) 322 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 323 FTIM1_NAND_TWBE(0x39) | \ 324 FTIM1_NAND_TRR(0x0e) | \ 325 FTIM1_NAND_TRP(0x18)) 326 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 327 FTIM2_NAND_TREH(0x0a) | \ 328 FTIM2_NAND_TWHRE(0x1e)) 329 #define CONFIG_SYS_NAND_FTIM3 0x0 330 331 #define CONFIG_SYS_NAND_DDR_LAW 11 332 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 333 #define CONFIG_SYS_MAX_NAND_DEVICE 1 334 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 335 336 #if defined(CONFIG_NAND) 337 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 338 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 339 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 340 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 341 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 342 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 343 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 344 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 345 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 346 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 347 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 348 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 349 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 350 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 351 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 352 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 353 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 354 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 355 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 356 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 357 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 358 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 359 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 360 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 361 #else 362 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 363 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 364 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 365 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 366 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 367 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 368 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 369 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 370 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 371 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 372 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 373 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 374 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 375 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 376 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 377 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 378 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 379 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 380 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 381 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 382 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 383 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 384 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 385 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 386 #endif 387 388 #if defined(CONFIG_RAMBOOT_PBL) 389 #define CONFIG_SYS_RAMBOOT 390 #endif 391 392 #ifdef CONFIG_SPL_BUILD 393 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 394 #else 395 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 396 #endif 397 398 #define CONFIG_MISC_INIT_R 399 #define CONFIG_HWCONFIG 400 401 /* define to use L1 as initial stack */ 402 #define CONFIG_L1_INIT_RAM 403 #define CONFIG_SYS_INIT_RAM_LOCK 404 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 405 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 406 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 407 /* The assembler doesn't like typecast */ 408 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 409 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 410 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 411 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 412 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 413 GENERATED_GBL_DATA_SIZE) 414 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 415 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 416 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 417 418 /* 419 * Serial Port 420 */ 421 #define CONFIG_SYS_NS16550_SERIAL 422 #define CONFIG_SYS_NS16550_REG_SIZE 1 423 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 424 #define CONFIG_SYS_BAUDRATE_TABLE \ 425 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 426 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 427 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 428 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 429 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 430 431 /* 432 * I2C 433 */ 434 #define CONFIG_SYS_I2C 435 #define CONFIG_SYS_I2C_FSL 436 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 437 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 438 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 439 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 440 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 441 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 442 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 443 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 444 #define CONFIG_SYS_FSL_I2C_SPEED 100000 445 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 446 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 447 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 448 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 449 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 450 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 451 #define I2C_MUX_CH_DEFAULT 0x8 452 453 #define I2C_MUX_CH_VOL_MONITOR 0xa 454 455 /* Voltage monitor on channel 2*/ 456 #define I2C_VOL_MONITOR_ADDR 0x40 457 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 458 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 459 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 460 461 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 462 #ifndef CONFIG_SPL_BUILD 463 #define CONFIG_VID 464 #endif 465 #define CONFIG_VOL_MONITOR_IR36021_SET 466 #define CONFIG_VOL_MONITOR_IR36021_READ 467 /* The lowest and highest voltage allowed for T208xQDS */ 468 #define VDD_MV_MIN 819 469 #define VDD_MV_MAX 1212 470 471 /* 472 * RapidIO 473 */ 474 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 475 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 476 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 477 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 478 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 479 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 480 /* 481 * for slave u-boot IMAGE instored in master memory space, 482 * PHYS must be aligned based on the SIZE 483 */ 484 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 485 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 486 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 487 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 488 /* 489 * for slave UCODE and ENV instored in master memory space, 490 * PHYS must be aligned based on the SIZE 491 */ 492 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 493 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 494 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 495 496 /* slave core release by master*/ 497 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 498 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 499 500 /* 501 * SRIO_PCIE_BOOT - SLAVE 502 */ 503 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 504 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 505 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 506 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 507 #endif 508 509 /* 510 * eSPI - Enhanced SPI 511 */ 512 #ifdef CONFIG_SPI_FLASH 513 #ifndef CONFIG_SPL_BUILD 514 #endif 515 516 #define CONFIG_SPI_FLASH_BAR 517 #define CONFIG_SF_DEFAULT_SPEED 10000000 518 #define CONFIG_SF_DEFAULT_MODE 0 519 #endif 520 521 /* 522 * General PCI 523 * Memory space is mapped 1-1, but I/O space must start from 0. 524 */ 525 #define CONFIG_PCIE1 /* PCIE controller 1 */ 526 #define CONFIG_PCIE2 /* PCIE controller 2 */ 527 #define CONFIG_PCIE3 /* PCIE controller 3 */ 528 #define CONFIG_PCIE4 /* PCIE controller 4 */ 529 #define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/ 530 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 531 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 532 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 533 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 534 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 535 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 536 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 537 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 538 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 539 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 540 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 541 542 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 543 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 544 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 545 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 546 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 547 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 548 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 549 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 550 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 551 552 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 553 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 554 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 555 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 556 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 557 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 558 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 559 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 560 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 561 562 /* controller 4, Base address 203000 */ 563 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 564 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 565 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 566 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 567 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 568 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 569 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 570 571 #ifdef CONFIG_PCI 572 #define CONFIG_PCI_INDIRECT_BRIDGE 573 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 574 #endif 575 576 /* Qman/Bman */ 577 #ifndef CONFIG_NOBQFMAN 578 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 579 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 580 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 581 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 582 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 583 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 584 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 585 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 586 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 587 CONFIG_SYS_BMAN_CENA_SIZE) 588 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 589 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 590 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 591 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 592 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 593 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 594 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 595 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 596 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 597 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 598 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 599 CONFIG_SYS_QMAN_CENA_SIZE) 600 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 601 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 602 603 #define CONFIG_SYS_DPAA_FMAN 604 #define CONFIG_SYS_DPAA_PME 605 #define CONFIG_SYS_PMAN 606 #define CONFIG_SYS_DPAA_DCE 607 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 608 #define CONFIG_SYS_INTERLAKEN 609 610 /* Default address of microcode for the Linux Fman driver */ 611 #if defined(CONFIG_SPIFLASH) 612 /* 613 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 614 * env, so we got 0x110000. 615 */ 616 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 617 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 618 #elif defined(CONFIG_SDCARD) 619 /* 620 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 621 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 622 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 623 */ 624 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 625 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 626 #elif defined(CONFIG_NAND) 627 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 628 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 629 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 630 /* 631 * Slave has no ucode locally, it can fetch this from remote. When implementing 632 * in two corenet boards, slave's ucode could be stored in master's memory 633 * space, the address can be mapped from slave TLB->slave LAW-> 634 * slave SRIO or PCIE outbound window->master inbound window-> 635 * master LAW->the ucode address in master's memory space. 636 */ 637 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 638 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 639 #else 640 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 641 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 642 #endif 643 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 644 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 645 #endif /* CONFIG_NOBQFMAN */ 646 647 #ifdef CONFIG_SYS_DPAA_FMAN 648 #define CONFIG_FMAN_ENET 649 #define CONFIG_PHYLIB_10G 650 #define CONFIG_PHY_VITESSE 651 #define CONFIG_PHY_REALTEK 652 #define CONFIG_PHY_TERANETICS 653 #define RGMII_PHY1_ADDR 0x1 654 #define RGMII_PHY2_ADDR 0x2 655 #define FM1_10GEC1_PHY_ADDR 0x3 656 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 657 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 658 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 659 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 660 #endif 661 662 #ifdef CONFIG_FMAN_ENET 663 #define CONFIG_MII /* MII PHY management */ 664 #define CONFIG_ETHPRIME "FM1@DTSEC3" 665 #endif 666 667 /* 668 * SATA 669 */ 670 #ifdef CONFIG_FSL_SATA_V2 671 #define CONFIG_SYS_SATA_MAX_DEVICE 2 672 #define CONFIG_SATA1 673 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 674 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 675 #define CONFIG_SATA2 676 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 677 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 678 #define CONFIG_LBA48 679 #endif 680 681 /* 682 * USB 683 */ 684 #ifdef CONFIG_USB_EHCI_HCD 685 #define CONFIG_USB_EHCI_FSL 686 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 687 #define CONFIG_HAS_FSL_DR_USB 688 #endif 689 690 /* 691 * SDHC 692 */ 693 #ifdef CONFIG_MMC 694 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 695 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 696 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 697 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 698 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 699 #endif 700 701 /* 702 * Dynamic MTD Partition support with mtdparts 703 */ 704 #ifdef CONFIG_MTD_NOR_FLASH 705 #define CONFIG_MTD_DEVICE 706 #define CONFIG_MTD_PARTITIONS 707 #define CONFIG_FLASH_CFI_MTD 708 #endif 709 710 /* 711 * Environment 712 */ 713 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 714 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 715 716 /* 717 * Miscellaneous configurable options 718 */ 719 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 720 721 /* 722 * For booting Linux, the board info and command line data 723 * have to be in the first 64 MB of memory, since this is 724 * the maximum mapped by the Linux kernel during initialization. 725 */ 726 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 727 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 728 729 #ifdef CONFIG_CMD_KGDB 730 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 731 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 732 #endif 733 734 /* 735 * Environment Configuration 736 */ 737 #define CONFIG_ROOTPATH "/opt/nfsroot" 738 #define CONFIG_BOOTFILE "uImage" 739 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 740 741 /* default location for tftp and bootm */ 742 #define CONFIG_LOADADDR 1000000 743 #define __USB_PHY_TYPE utmi 744 745 #define CONFIG_EXTRA_ENV_SETTINGS \ 746 "hwconfig=fsl_ddr:" \ 747 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 748 "bank_intlv=auto;" \ 749 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 750 "netdev=eth0\0" \ 751 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 752 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 753 "tftpflash=tftpboot $loadaddr $uboot && " \ 754 "protect off $ubootaddr +$filesize && " \ 755 "erase $ubootaddr +$filesize && " \ 756 "cp.b $loadaddr $ubootaddr $filesize && " \ 757 "protect on $ubootaddr +$filesize && " \ 758 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 759 "consoledev=ttyS0\0" \ 760 "ramdiskaddr=2000000\0" \ 761 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 762 "fdtaddr=1e00000\0" \ 763 "fdtfile=t2080qds/t2080qds.dtb\0" \ 764 "bdev=sda3\0" 765 766 /* 767 * For emulation this causes u-boot to jump to the start of the 768 * proof point app code automatically 769 */ 770 #define CONFIG_PROOF_POINTS \ 771 "setenv bootargs root=/dev/$bdev rw " \ 772 "console=$consoledev,$baudrate $othbootargs;" \ 773 "cpu 1 release 0x29000000 - - -;" \ 774 "cpu 2 release 0x29000000 - - -;" \ 775 "cpu 3 release 0x29000000 - - -;" \ 776 "cpu 4 release 0x29000000 - - -;" \ 777 "cpu 5 release 0x29000000 - - -;" \ 778 "cpu 6 release 0x29000000 - - -;" \ 779 "cpu 7 release 0x29000000 - - -;" \ 780 "go 0x29000000" 781 782 #define CONFIG_HVBOOT \ 783 "setenv bootargs config-addr=0x60000000; " \ 784 "bootm 0x01000000 - 0x00f00000" 785 786 #define CONFIG_ALU \ 787 "setenv bootargs root=/dev/$bdev rw " \ 788 "console=$consoledev,$baudrate $othbootargs;" \ 789 "cpu 1 release 0x01000000 - - -;" \ 790 "cpu 2 release 0x01000000 - - -;" \ 791 "cpu 3 release 0x01000000 - - -;" \ 792 "cpu 4 release 0x01000000 - - -;" \ 793 "cpu 5 release 0x01000000 - - -;" \ 794 "cpu 6 release 0x01000000 - - -;" \ 795 "cpu 7 release 0x01000000 - - -;" \ 796 "go 0x01000000" 797 798 #define CONFIG_LINUX \ 799 "setenv bootargs root=/dev/ram rw " \ 800 "console=$consoledev,$baudrate $othbootargs;" \ 801 "setenv ramdiskaddr 0x02000000;" \ 802 "setenv fdtaddr 0x00c00000;" \ 803 "setenv loadaddr 0x1000000;" \ 804 "bootm $loadaddr $ramdiskaddr $fdtaddr" 805 806 #define CONFIG_HDBOOT \ 807 "setenv bootargs root=/dev/$bdev rw " \ 808 "console=$consoledev,$baudrate $othbootargs;" \ 809 "tftp $loadaddr $bootfile;" \ 810 "tftp $fdtaddr $fdtfile;" \ 811 "bootm $loadaddr - $fdtaddr" 812 813 #define CONFIG_NFSBOOTCOMMAND \ 814 "setenv bootargs root=/dev/nfs rw " \ 815 "nfsroot=$serverip:$rootpath " \ 816 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 817 "console=$consoledev,$baudrate $othbootargs;" \ 818 "tftp $loadaddr $bootfile;" \ 819 "tftp $fdtaddr $fdtfile;" \ 820 "bootm $loadaddr - $fdtaddr" 821 822 #define CONFIG_RAMBOOTCOMMAND \ 823 "setenv bootargs root=/dev/ram rw " \ 824 "console=$consoledev,$baudrate $othbootargs;" \ 825 "tftp $ramdiskaddr $ramdiskfile;" \ 826 "tftp $loadaddr $bootfile;" \ 827 "tftp $fdtaddr $fdtfile;" \ 828 "bootm $loadaddr $ramdiskaddr $fdtaddr" 829 830 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 831 832 #include <asm/fsl_secure_boot.h> 833 834 #endif /* __T208xQDS_H */ 835