1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #if defined(CONFIG_ARCH_T2080) 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 18 #define CONFIG_SRIO1 /* SRIO port 1 */ 19 #define CONFIG_SRIO2 /* SRIO port 2 */ 20 #elif defined(CONFIG_ARCH_T2081) 21 #endif 22 23 /* High Level Configuration Options */ 24 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 25 #define CONFIG_MP /* support multiple processors */ 26 #define CONFIG_ENABLE_36BIT_PHYS 27 28 #ifdef CONFIG_PHYS_64BIT 29 #define CONFIG_ADDR_MAP 1 30 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 31 #endif 32 33 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 34 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 35 #define CONFIG_ENV_OVERWRITE 36 37 #ifdef CONFIG_RAMBOOT_PBL 38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 39 40 #define CONFIG_SPL_FLUSH_IMAGE 41 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 42 #define CONFIG_SYS_TEXT_BASE 0x00201000 43 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 44 #define CONFIG_SPL_PAD_TO 0x40000 45 #define CONFIG_SPL_MAX_SIZE 0x28000 46 #define RESET_VECTOR_OFFSET 0x27FFC 47 #define BOOT_PAGE_OFFSET 0x27000 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_SKIP_RELOCATE 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 52 #endif 53 54 #ifdef CONFIG_NAND 55 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 56 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 57 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 58 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 59 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 60 #if defined(CONFIG_ARCH_T2080) 61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 62 #elif defined(CONFIG_ARCH_T2081) 63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 64 #endif 65 #define CONFIG_SPL_NAND_BOOT 66 #endif 67 68 #ifdef CONFIG_SPIFLASH 69 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 70 #define CONFIG_SPL_SPI_FLASH_MINIMAL 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 76 #ifndef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 78 #endif 79 #if defined(CONFIG_ARCH_T2080) 80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 81 #elif defined(CONFIG_ARCH_T2081) 82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 83 #endif 84 #define CONFIG_SPL_SPI_BOOT 85 #endif 86 87 #ifdef CONFIG_SDCARD 88 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 89 #define CONFIG_SPL_MMC_MINIMAL 90 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 91 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 92 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 93 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 94 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 95 #ifndef CONFIG_SPL_BUILD 96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 97 #endif 98 #if defined(CONFIG_ARCH_T2080) 99 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 100 #elif defined(CONFIG_ARCH_T2081) 101 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 102 #endif 103 #define CONFIG_SPL_MMC_BOOT 104 #endif 105 106 #endif /* CONFIG_RAMBOOT_PBL */ 107 108 #define CONFIG_SRIO_PCIE_BOOT_MASTER 109 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 110 /* Set 1M boot space */ 111 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 112 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 113 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 114 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 115 #endif 116 117 #ifndef CONFIG_SYS_TEXT_BASE 118 #define CONFIG_SYS_TEXT_BASE 0xeff40000 119 #endif 120 121 #ifndef CONFIG_RESET_VECTOR_ADDRESS 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 123 #endif 124 125 /* 126 * These can be toggled for performance analysis, otherwise use default. 127 */ 128 #define CONFIG_SYS_CACHE_STASHING 129 #define CONFIG_BTB /* toggle branch predition */ 130 #define CONFIG_DDR_ECC 131 #ifdef CONFIG_DDR_ECC 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 133 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 134 #endif 135 136 #ifdef CONFIG_MTD_NOR_FLASH 137 #define CONFIG_FLASH_CFI_DRIVER 138 #define CONFIG_SYS_FLASH_CFI 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 140 #endif 141 142 #if defined(CONFIG_SPIFLASH) 143 #define CONFIG_SYS_EXTRA_ENV_RELOC 144 #define CONFIG_ENV_IS_IN_SPI_FLASH 145 #define CONFIG_ENV_SPI_BUS 0 146 #define CONFIG_ENV_SPI_CS 0 147 #define CONFIG_ENV_SPI_MAX_HZ 10000000 148 #define CONFIG_ENV_SPI_MODE 0 149 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 150 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 151 #define CONFIG_ENV_SECT_SIZE 0x10000 152 #elif defined(CONFIG_SDCARD) 153 #define CONFIG_SYS_EXTRA_ENV_RELOC 154 #define CONFIG_ENV_IS_IN_MMC 155 #define CONFIG_SYS_MMC_ENV_DEV 0 156 #define CONFIG_ENV_SIZE 0x2000 157 #define CONFIG_ENV_OFFSET (512 * 0x800) 158 #elif defined(CONFIG_NAND) 159 #define CONFIG_SYS_EXTRA_ENV_RELOC 160 #define CONFIG_ENV_IS_IN_NAND 161 #define CONFIG_ENV_SIZE 0x2000 162 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 163 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 164 #define CONFIG_ENV_IS_IN_REMOTE 165 #define CONFIG_ENV_ADDR 0xffe20000 166 #define CONFIG_ENV_SIZE 0x2000 167 #elif defined(CONFIG_ENV_IS_NOWHERE) 168 #define CONFIG_ENV_SIZE 0x2000 169 #else 170 #define CONFIG_ENV_IS_IN_FLASH 171 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 172 #define CONFIG_ENV_SIZE 0x2000 173 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 174 #endif 175 176 #ifndef __ASSEMBLY__ 177 unsigned long get_board_sys_clk(void); 178 unsigned long get_board_ddr_clk(void); 179 #endif 180 181 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 182 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 183 184 /* 185 * Config the L3 Cache as L3 SRAM 186 */ 187 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 188 #define CONFIG_SYS_L3_SIZE (512 << 10) 189 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 190 #ifdef CONFIG_RAMBOOT_PBL 191 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 192 #endif 193 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 194 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 195 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 196 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 197 198 #define CONFIG_SYS_DCSRBAR 0xf0000000 199 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 200 201 /* EEPROM */ 202 #define CONFIG_ID_EEPROM 203 #define CONFIG_SYS_I2C_EEPROM_NXID 204 #define CONFIG_SYS_EEPROM_BUS_NUM 0 205 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 206 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 207 208 /* 209 * DDR Setup 210 */ 211 #define CONFIG_VERY_BIG_RAM 212 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 213 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 214 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 215 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 216 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 217 #define CONFIG_DDR_SPD 218 #define CONFIG_FSL_DDR_INTERACTIVE 219 #define CONFIG_SYS_SPD_BUS_NUM 0 220 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 221 #define SPD_EEPROM_ADDRESS1 0x51 222 #define SPD_EEPROM_ADDRESS2 0x52 223 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 224 #define CTRL_INTLV_PREFERED cacheline 225 226 /* 227 * IFC Definitions 228 */ 229 #define CONFIG_SYS_FLASH_BASE 0xe0000000 230 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 231 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 232 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 233 + 0x8000000) | \ 234 CSPR_PORT_SIZE_16 | \ 235 CSPR_MSEL_NOR | \ 236 CSPR_V) 237 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 238 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 239 CSPR_PORT_SIZE_16 | \ 240 CSPR_MSEL_NOR | \ 241 CSPR_V) 242 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 243 /* NOR Flash Timing Params */ 244 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 245 246 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 247 FTIM0_NOR_TEADC(0x5) | \ 248 FTIM0_NOR_TEAHC(0x5)) 249 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 250 FTIM1_NOR_TRAD_NOR(0x1A) |\ 251 FTIM1_NOR_TSEQRAD_NOR(0x13)) 252 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 253 FTIM2_NOR_TCH(0x4) | \ 254 FTIM2_NOR_TWPH(0x0E) | \ 255 FTIM2_NOR_TWP(0x1c)) 256 #define CONFIG_SYS_NOR_FTIM3 0x0 257 258 #define CONFIG_SYS_FLASH_QUIET_TEST 259 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 260 261 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 262 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 263 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 264 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 265 266 #define CONFIG_SYS_FLASH_EMPTY_INFO 267 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 268 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 269 270 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 271 #define QIXIS_BASE 0xffdf0000 272 #define QIXIS_LBMAP_SWITCH 6 273 #define QIXIS_LBMAP_MASK 0x0f 274 #define QIXIS_LBMAP_SHIFT 0 275 #define QIXIS_LBMAP_DFLTBANK 0x00 276 #define QIXIS_LBMAP_ALTBANK 0x04 277 #define QIXIS_LBMAP_NAND 0x09 278 #define QIXIS_LBMAP_SD 0x00 279 #define QIXIS_RCW_SRC_NAND 0x104 280 #define QIXIS_RCW_SRC_SD 0x040 281 #define QIXIS_RST_CTL_RESET 0x83 282 #define QIXIS_RST_FORCE_MEM 0x1 283 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 284 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 285 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 286 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 287 288 #define CONFIG_SYS_CSPR3_EXT (0xf) 289 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 290 | CSPR_PORT_SIZE_8 \ 291 | CSPR_MSEL_GPCM \ 292 | CSPR_V) 293 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 294 #define CONFIG_SYS_CSOR3 0x0 295 /* QIXIS Timing parameters for IFC CS3 */ 296 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 297 FTIM0_GPCM_TEADC(0x0e) | \ 298 FTIM0_GPCM_TEAHC(0x0e)) 299 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 300 FTIM1_GPCM_TRAD(0x3f)) 301 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 302 FTIM2_GPCM_TCH(0x8) | \ 303 FTIM2_GPCM_TWP(0x1f)) 304 #define CONFIG_SYS_CS3_FTIM3 0x0 305 306 /* NAND Flash on IFC */ 307 #define CONFIG_NAND_FSL_IFC 308 #define CONFIG_SYS_NAND_BASE 0xff800000 309 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 310 311 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 312 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 313 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 314 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 315 | CSPR_V) 316 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 317 318 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 319 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 320 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 321 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 322 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 323 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 324 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 325 326 #define CONFIG_SYS_NAND_ONFI_DETECTION 327 328 /* ONFI NAND Flash mode0 Timing Params */ 329 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 330 FTIM0_NAND_TWP(0x18) | \ 331 FTIM0_NAND_TWCHT(0x07) | \ 332 FTIM0_NAND_TWH(0x0a)) 333 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 334 FTIM1_NAND_TWBE(0x39) | \ 335 FTIM1_NAND_TRR(0x0e) | \ 336 FTIM1_NAND_TRP(0x18)) 337 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 338 FTIM2_NAND_TREH(0x0a) | \ 339 FTIM2_NAND_TWHRE(0x1e)) 340 #define CONFIG_SYS_NAND_FTIM3 0x0 341 342 #define CONFIG_SYS_NAND_DDR_LAW 11 343 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 344 #define CONFIG_SYS_MAX_NAND_DEVICE 1 345 #define CONFIG_CMD_NAND 346 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 347 348 #if defined(CONFIG_NAND) 349 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 357 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 358 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 359 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 360 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 361 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 362 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 363 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 364 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 365 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 366 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 367 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 368 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 369 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 370 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 371 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 372 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 373 #else 374 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 375 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 376 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 377 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 378 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 379 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 380 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 381 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 382 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 383 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 384 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 385 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 386 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 387 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 388 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 389 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 390 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 391 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 392 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 393 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 394 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 395 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 396 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 397 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 398 #endif 399 400 #if defined(CONFIG_RAMBOOT_PBL) 401 #define CONFIG_SYS_RAMBOOT 402 #endif 403 404 #ifdef CONFIG_SPL_BUILD 405 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 406 #else 407 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 408 #endif 409 410 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 411 #define CONFIG_MISC_INIT_R 412 #define CONFIG_HWCONFIG 413 414 /* define to use L1 as initial stack */ 415 #define CONFIG_L1_INIT_RAM 416 #define CONFIG_SYS_INIT_RAM_LOCK 417 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 418 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 420 /* The assembler doesn't like typecast */ 421 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 422 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 423 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 424 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 425 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 426 GENERATED_GBL_DATA_SIZE) 427 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 428 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 429 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 430 431 /* 432 * Serial Port 433 */ 434 #define CONFIG_CONS_INDEX 1 435 #define CONFIG_SYS_NS16550_SERIAL 436 #define CONFIG_SYS_NS16550_REG_SIZE 1 437 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 438 #define CONFIG_SYS_BAUDRATE_TABLE \ 439 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 440 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 441 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 442 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 443 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 444 445 /* 446 * I2C 447 */ 448 #define CONFIG_SYS_I2C 449 #define CONFIG_SYS_I2C_FSL 450 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 451 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 452 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 453 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 454 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 455 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 456 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 457 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 458 #define CONFIG_SYS_FSL_I2C_SPEED 100000 459 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 460 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 461 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 462 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 463 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 464 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 465 #define I2C_MUX_CH_DEFAULT 0x8 466 467 #define I2C_MUX_CH_VOL_MONITOR 0xa 468 469 /* Voltage monitor on channel 2*/ 470 #define I2C_VOL_MONITOR_ADDR 0x40 471 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 472 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 473 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 474 475 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 476 #ifndef CONFIG_SPL_BUILD 477 #define CONFIG_VID 478 #endif 479 #define CONFIG_VOL_MONITOR_IR36021_SET 480 #define CONFIG_VOL_MONITOR_IR36021_READ 481 /* The lowest and highest voltage allowed for T208xQDS */ 482 #define VDD_MV_MIN 819 483 #define VDD_MV_MAX 1212 484 485 /* 486 * RapidIO 487 */ 488 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 489 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 490 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 491 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 492 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 493 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 494 /* 495 * for slave u-boot IMAGE instored in master memory space, 496 * PHYS must be aligned based on the SIZE 497 */ 498 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 499 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 500 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 502 /* 503 * for slave UCODE and ENV instored in master memory space, 504 * PHYS must be aligned based on the SIZE 505 */ 506 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 507 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 508 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 509 510 /* slave core release by master*/ 511 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 512 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 513 514 /* 515 * SRIO_PCIE_BOOT - SLAVE 516 */ 517 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 518 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 519 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 520 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 521 #endif 522 523 /* 524 * eSPI - Enhanced SPI 525 */ 526 #ifdef CONFIG_SPI_FLASH 527 #ifndef CONFIG_SPL_BUILD 528 #endif 529 530 #define CONFIG_SPI_FLASH_BAR 531 #define CONFIG_SF_DEFAULT_SPEED 10000000 532 #define CONFIG_SF_DEFAULT_MODE 0 533 #endif 534 535 /* 536 * General PCI 537 * Memory space is mapped 1-1, but I/O space must start from 0. 538 */ 539 #define CONFIG_PCIE1 /* PCIE controller 1 */ 540 #define CONFIG_PCIE2 /* PCIE controller 2 */ 541 #define CONFIG_PCIE3 /* PCIE controller 3 */ 542 #define CONFIG_PCIE4 /* PCIE controller 4 */ 543 #define CONFIG_FSL_PCIE_RESET 544 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 545 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 546 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 547 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 548 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 549 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 550 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 551 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 552 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 553 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 554 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 555 556 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 557 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 558 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 559 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 560 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 561 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 562 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 563 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 564 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 565 566 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 567 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 568 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 569 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 570 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 571 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 572 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 573 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 574 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 575 576 /* controller 4, Base address 203000 */ 577 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 578 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 579 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 580 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 581 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 582 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 583 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 584 585 #ifdef CONFIG_PCI 586 #define CONFIG_PCI_INDIRECT_BRIDGE 587 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 588 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 589 #endif 590 591 /* Qman/Bman */ 592 #ifndef CONFIG_NOBQFMAN 593 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 594 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 595 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 596 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 597 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 598 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 599 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 600 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 601 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 602 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 603 CONFIG_SYS_BMAN_CENA_SIZE) 604 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 605 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 606 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 607 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 608 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 609 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 610 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 611 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 612 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 613 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 614 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 615 CONFIG_SYS_QMAN_CENA_SIZE) 616 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 617 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 618 619 #define CONFIG_SYS_DPAA_FMAN 620 #define CONFIG_SYS_DPAA_PME 621 #define CONFIG_SYS_PMAN 622 #define CONFIG_SYS_DPAA_DCE 623 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 624 #define CONFIG_SYS_INTERLAKEN 625 626 /* Default address of microcode for the Linux Fman driver */ 627 #if defined(CONFIG_SPIFLASH) 628 /* 629 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 630 * env, so we got 0x110000. 631 */ 632 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 633 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 634 #elif defined(CONFIG_SDCARD) 635 /* 636 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 637 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 638 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 639 */ 640 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 641 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 642 #elif defined(CONFIG_NAND) 643 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 644 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 645 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 646 /* 647 * Slave has no ucode locally, it can fetch this from remote. When implementing 648 * in two corenet boards, slave's ucode could be stored in master's memory 649 * space, the address can be mapped from slave TLB->slave LAW-> 650 * slave SRIO or PCIE outbound window->master inbound window-> 651 * master LAW->the ucode address in master's memory space. 652 */ 653 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 654 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 655 #else 656 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 657 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 658 #endif 659 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 660 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 661 #endif /* CONFIG_NOBQFMAN */ 662 663 #ifdef CONFIG_SYS_DPAA_FMAN 664 #define CONFIG_FMAN_ENET 665 #define CONFIG_PHYLIB_10G 666 #define CONFIG_PHY_VITESSE 667 #define CONFIG_PHY_REALTEK 668 #define CONFIG_PHY_TERANETICS 669 #define RGMII_PHY1_ADDR 0x1 670 #define RGMII_PHY2_ADDR 0x2 671 #define FM1_10GEC1_PHY_ADDR 0x3 672 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 673 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 674 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 675 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 676 #endif 677 678 #ifdef CONFIG_FMAN_ENET 679 #define CONFIG_MII /* MII PHY management */ 680 #define CONFIG_ETHPRIME "FM1@DTSEC3" 681 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 682 #endif 683 684 /* 685 * SATA 686 */ 687 #ifdef CONFIG_FSL_SATA_V2 688 #define CONFIG_LIBATA 689 #define CONFIG_FSL_SATA 690 #define CONFIG_SYS_SATA_MAX_DEVICE 2 691 #define CONFIG_SATA1 692 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 693 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 694 #define CONFIG_SATA2 695 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 696 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 697 #define CONFIG_LBA48 698 #endif 699 700 /* 701 * USB 702 */ 703 #ifdef CONFIG_USB_EHCI_HCD 704 #define CONFIG_USB_EHCI_FSL 705 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 706 #define CONFIG_HAS_FSL_DR_USB 707 #endif 708 709 /* 710 * SDHC 711 */ 712 #ifdef CONFIG_MMC 713 #define CONFIG_FSL_ESDHC 714 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 715 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 716 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 717 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 718 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 719 #endif 720 721 /* 722 * Dynamic MTD Partition support with mtdparts 723 */ 724 #ifdef CONFIG_MTD_NOR_FLASH 725 #define CONFIG_MTD_DEVICE 726 #define CONFIG_MTD_PARTITIONS 727 #define CONFIG_CMD_MTDPARTS 728 #define CONFIG_FLASH_CFI_MTD 729 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 730 "spi0=spife110000.0" 731 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 732 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 733 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 734 "1m(uboot),5m(kernel),128k(dtb),-(user)" 735 #endif 736 737 /* 738 * Environment 739 */ 740 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 741 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 742 743 /* 744 * Command line configuration. 745 */ 746 #define CONFIG_CMD_REGINFO 747 748 #ifdef CONFIG_PCI 749 #define CONFIG_CMD_PCI 750 #endif 751 752 /* 753 * Miscellaneous configurable options 754 */ 755 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 756 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 757 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 758 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 759 #ifdef CONFIG_CMD_KGDB 760 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 761 #else 762 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 763 #endif 764 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 765 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 766 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 767 768 /* 769 * For booting Linux, the board info and command line data 770 * have to be in the first 64 MB of memory, since this is 771 * the maximum mapped by the Linux kernel during initialization. 772 */ 773 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 774 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 775 776 #ifdef CONFIG_CMD_KGDB 777 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 778 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 779 #endif 780 781 /* 782 * Environment Configuration 783 */ 784 #define CONFIG_ROOTPATH "/opt/nfsroot" 785 #define CONFIG_BOOTFILE "uImage" 786 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 787 788 /* default location for tftp and bootm */ 789 #define CONFIG_LOADADDR 1000000 790 #define __USB_PHY_TYPE utmi 791 792 #define CONFIG_EXTRA_ENV_SETTINGS \ 793 "hwconfig=fsl_ddr:" \ 794 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 795 "bank_intlv=auto;" \ 796 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 797 "netdev=eth0\0" \ 798 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 799 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 800 "tftpflash=tftpboot $loadaddr $uboot && " \ 801 "protect off $ubootaddr +$filesize && " \ 802 "erase $ubootaddr +$filesize && " \ 803 "cp.b $loadaddr $ubootaddr $filesize && " \ 804 "protect on $ubootaddr +$filesize && " \ 805 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 806 "consoledev=ttyS0\0" \ 807 "ramdiskaddr=2000000\0" \ 808 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 809 "fdtaddr=1e00000\0" \ 810 "fdtfile=t2080qds/t2080qds.dtb\0" \ 811 "bdev=sda3\0" 812 813 /* 814 * For emulation this causes u-boot to jump to the start of the 815 * proof point app code automatically 816 */ 817 #define CONFIG_PROOF_POINTS \ 818 "setenv bootargs root=/dev/$bdev rw " \ 819 "console=$consoledev,$baudrate $othbootargs;" \ 820 "cpu 1 release 0x29000000 - - -;" \ 821 "cpu 2 release 0x29000000 - - -;" \ 822 "cpu 3 release 0x29000000 - - -;" \ 823 "cpu 4 release 0x29000000 - - -;" \ 824 "cpu 5 release 0x29000000 - - -;" \ 825 "cpu 6 release 0x29000000 - - -;" \ 826 "cpu 7 release 0x29000000 - - -;" \ 827 "go 0x29000000" 828 829 #define CONFIG_HVBOOT \ 830 "setenv bootargs config-addr=0x60000000; " \ 831 "bootm 0x01000000 - 0x00f00000" 832 833 #define CONFIG_ALU \ 834 "setenv bootargs root=/dev/$bdev rw " \ 835 "console=$consoledev,$baudrate $othbootargs;" \ 836 "cpu 1 release 0x01000000 - - -;" \ 837 "cpu 2 release 0x01000000 - - -;" \ 838 "cpu 3 release 0x01000000 - - -;" \ 839 "cpu 4 release 0x01000000 - - -;" \ 840 "cpu 5 release 0x01000000 - - -;" \ 841 "cpu 6 release 0x01000000 - - -;" \ 842 "cpu 7 release 0x01000000 - - -;" \ 843 "go 0x01000000" 844 845 #define CONFIG_LINUX \ 846 "setenv bootargs root=/dev/ram rw " \ 847 "console=$consoledev,$baudrate $othbootargs;" \ 848 "setenv ramdiskaddr 0x02000000;" \ 849 "setenv fdtaddr 0x00c00000;" \ 850 "setenv loadaddr 0x1000000;" \ 851 "bootm $loadaddr $ramdiskaddr $fdtaddr" 852 853 #define CONFIG_HDBOOT \ 854 "setenv bootargs root=/dev/$bdev rw " \ 855 "console=$consoledev,$baudrate $othbootargs;" \ 856 "tftp $loadaddr $bootfile;" \ 857 "tftp $fdtaddr $fdtfile;" \ 858 "bootm $loadaddr - $fdtaddr" 859 860 #define CONFIG_NFSBOOTCOMMAND \ 861 "setenv bootargs root=/dev/nfs rw " \ 862 "nfsroot=$serverip:$rootpath " \ 863 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 864 "console=$consoledev,$baudrate $othbootargs;" \ 865 "tftp $loadaddr $bootfile;" \ 866 "tftp $fdtaddr $fdtfile;" \ 867 "bootm $loadaddr - $fdtaddr" 868 869 #define CONFIG_RAMBOOTCOMMAND \ 870 "setenv bootargs root=/dev/ram rw " \ 871 "console=$consoledev,$baudrate $othbootargs;" \ 872 "tftp $ramdiskaddr $ramdiskfile;" \ 873 "tftp $loadaddr $bootfile;" \ 874 "tftp $fdtaddr $fdtfile;" \ 875 "bootm $loadaddr $ramdiskaddr $fdtaddr" 876 877 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 878 879 #include <asm/fsl_secure_boot.h> 880 881 #endif /* __T208xQDS_H */ 882