1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011-2013 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * T2080/T2081 QDS board configuration file 8 */ 9 10 #ifndef __T208xQDS_H 11 #define __T208xQDS_H 12 13 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 14 #if defined(CONFIG_ARCH_T2080) 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 17 #define CONFIG_SRIO1 /* SRIO port 1 */ 18 #define CONFIG_SRIO2 /* SRIO port 2 */ 19 #elif defined(CONFIG_ARCH_T2081) 20 #endif 21 22 /* High Level Configuration Options */ 23 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 24 #define CONFIG_ENABLE_36BIT_PHYS 25 26 #ifdef CONFIG_PHYS_64BIT 27 #define CONFIG_ADDR_MAP 1 28 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 29 #endif 30 31 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 32 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 33 #define CONFIG_ENV_OVERWRITE 34 35 #ifdef CONFIG_RAMBOOT_PBL 36 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 37 38 #define CONFIG_SPL_FLUSH_IMAGE 39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 40 #define CONFIG_SPL_PAD_TO 0x40000 41 #define CONFIG_SPL_MAX_SIZE 0x28000 42 #define RESET_VECTOR_OFFSET 0x27FFC 43 #define BOOT_PAGE_OFFSET 0x27000 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #endif 49 50 #ifdef CONFIG_NAND 51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 54 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 56 #if defined(CONFIG_ARCH_T2080) 57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 58 #elif defined(CONFIG_ARCH_T2081) 59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 60 #endif 61 #define CONFIG_SPL_NAND_BOOT 62 #endif 63 64 #ifdef CONFIG_SPIFLASH 65 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 66 #define CONFIG_SPL_SPI_FLASH_MINIMAL 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 71 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 72 #ifndef CONFIG_SPL_BUILD 73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 74 #endif 75 #if defined(CONFIG_ARCH_T2080) 76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 77 #elif defined(CONFIG_ARCH_T2081) 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 79 #endif 80 #define CONFIG_SPL_SPI_BOOT 81 #endif 82 83 #ifdef CONFIG_SDCARD 84 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 85 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 86 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 87 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 88 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 89 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 90 #ifndef CONFIG_SPL_BUILD 91 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 92 #endif 93 #if defined(CONFIG_ARCH_T2080) 94 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 95 #elif defined(CONFIG_ARCH_T2081) 96 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 97 #endif 98 #define CONFIG_SPL_MMC_BOOT 99 #endif 100 101 #endif /* CONFIG_RAMBOOT_PBL */ 102 103 #define CONFIG_SRIO_PCIE_BOOT_MASTER 104 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 105 /* Set 1M boot space */ 106 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 107 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 108 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 109 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 110 #endif 111 112 #ifndef CONFIG_RESET_VECTOR_ADDRESS 113 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 114 #endif 115 116 /* 117 * These can be toggled for performance analysis, otherwise use default. 118 */ 119 #define CONFIG_SYS_CACHE_STASHING 120 #define CONFIG_BTB /* toggle branch predition */ 121 #define CONFIG_DDR_ECC 122 #ifdef CONFIG_DDR_ECC 123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 124 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 125 #endif 126 127 #if defined(CONFIG_SPIFLASH) 128 #define CONFIG_ENV_SPI_BUS 0 129 #define CONFIG_ENV_SPI_CS 0 130 #define CONFIG_ENV_SPI_MAX_HZ 10000000 131 #define CONFIG_ENV_SPI_MODE 0 132 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 133 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 134 #define CONFIG_ENV_SECT_SIZE 0x10000 135 #elif defined(CONFIG_SDCARD) 136 #define CONFIG_SYS_MMC_ENV_DEV 0 137 #define CONFIG_ENV_SIZE 0x2000 138 #define CONFIG_ENV_OFFSET (512 * 0x800) 139 #elif defined(CONFIG_NAND) 140 #define CONFIG_ENV_SIZE 0x2000 141 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 142 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 143 #define CONFIG_ENV_ADDR 0xffe20000 144 #define CONFIG_ENV_SIZE 0x2000 145 #elif defined(CONFIG_ENV_IS_NOWHERE) 146 #define CONFIG_ENV_SIZE 0x2000 147 #else 148 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 149 #define CONFIG_ENV_SIZE 0x2000 150 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 151 #endif 152 153 #ifndef __ASSEMBLY__ 154 unsigned long get_board_sys_clk(void); 155 unsigned long get_board_ddr_clk(void); 156 #endif 157 158 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 159 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 160 161 /* 162 * Config the L3 Cache as L3 SRAM 163 */ 164 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 165 #define CONFIG_SYS_L3_SIZE (512 << 10) 166 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 167 #ifdef CONFIG_RAMBOOT_PBL 168 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 169 #endif 170 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 171 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 172 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 173 174 #define CONFIG_SYS_DCSRBAR 0xf0000000 175 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 176 177 /* EEPROM */ 178 #define CONFIG_ID_EEPROM 179 #define CONFIG_SYS_I2C_EEPROM_NXID 180 #define CONFIG_SYS_EEPROM_BUS_NUM 0 181 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 183 184 /* 185 * DDR Setup 186 */ 187 #define CONFIG_VERY_BIG_RAM 188 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 189 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 190 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 191 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 192 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 193 #define CONFIG_DDR_SPD 194 #define CONFIG_FSL_DDR_INTERACTIVE 195 #define CONFIG_SYS_SPD_BUS_NUM 0 196 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 197 #define SPD_EEPROM_ADDRESS1 0x51 198 #define SPD_EEPROM_ADDRESS2 0x52 199 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 200 #define CTRL_INTLV_PREFERED cacheline 201 202 /* 203 * IFC Definitions 204 */ 205 #define CONFIG_SYS_FLASH_BASE 0xe0000000 206 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 207 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 208 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 209 + 0x8000000) | \ 210 CSPR_PORT_SIZE_16 | \ 211 CSPR_MSEL_NOR | \ 212 CSPR_V) 213 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 214 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 215 CSPR_PORT_SIZE_16 | \ 216 CSPR_MSEL_NOR | \ 217 CSPR_V) 218 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 219 /* NOR Flash Timing Params */ 220 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 221 222 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 223 FTIM0_NOR_TEADC(0x5) | \ 224 FTIM0_NOR_TEAHC(0x5)) 225 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 226 FTIM1_NOR_TRAD_NOR(0x1A) |\ 227 FTIM1_NOR_TSEQRAD_NOR(0x13)) 228 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 229 FTIM2_NOR_TCH(0x4) | \ 230 FTIM2_NOR_TWPH(0x0E) | \ 231 FTIM2_NOR_TWP(0x1c)) 232 #define CONFIG_SYS_NOR_FTIM3 0x0 233 234 #define CONFIG_SYS_FLASH_QUIET_TEST 235 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 236 237 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 238 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 239 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 240 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 241 242 #define CONFIG_SYS_FLASH_EMPTY_INFO 243 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 244 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 245 246 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 247 #define QIXIS_BASE 0xffdf0000 248 #define QIXIS_LBMAP_SWITCH 6 249 #define QIXIS_LBMAP_MASK 0x0f 250 #define QIXIS_LBMAP_SHIFT 0 251 #define QIXIS_LBMAP_DFLTBANK 0x00 252 #define QIXIS_LBMAP_ALTBANK 0x04 253 #define QIXIS_LBMAP_NAND 0x09 254 #define QIXIS_LBMAP_SD 0x00 255 #define QIXIS_RCW_SRC_NAND 0x104 256 #define QIXIS_RCW_SRC_SD 0x040 257 #define QIXIS_RST_CTL_RESET 0x83 258 #define QIXIS_RST_FORCE_MEM 0x1 259 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 260 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 261 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 262 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 263 264 #define CONFIG_SYS_CSPR3_EXT (0xf) 265 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 266 | CSPR_PORT_SIZE_8 \ 267 | CSPR_MSEL_GPCM \ 268 | CSPR_V) 269 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 270 #define CONFIG_SYS_CSOR3 0x0 271 /* QIXIS Timing parameters for IFC CS3 */ 272 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 273 FTIM0_GPCM_TEADC(0x0e) | \ 274 FTIM0_GPCM_TEAHC(0x0e)) 275 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 276 FTIM1_GPCM_TRAD(0x3f)) 277 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 278 FTIM2_GPCM_TCH(0x8) | \ 279 FTIM2_GPCM_TWP(0x1f)) 280 #define CONFIG_SYS_CS3_FTIM3 0x0 281 282 /* NAND Flash on IFC */ 283 #define CONFIG_NAND_FSL_IFC 284 #define CONFIG_SYS_NAND_BASE 0xff800000 285 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 286 287 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 288 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 289 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 290 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 291 | CSPR_V) 292 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 293 294 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 295 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 296 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 297 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 298 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 299 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 300 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 301 302 #define CONFIG_SYS_NAND_ONFI_DETECTION 303 304 /* ONFI NAND Flash mode0 Timing Params */ 305 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 306 FTIM0_NAND_TWP(0x18) | \ 307 FTIM0_NAND_TWCHT(0x07) | \ 308 FTIM0_NAND_TWH(0x0a)) 309 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 310 FTIM1_NAND_TWBE(0x39) | \ 311 FTIM1_NAND_TRR(0x0e) | \ 312 FTIM1_NAND_TRP(0x18)) 313 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 314 FTIM2_NAND_TREH(0x0a) | \ 315 FTIM2_NAND_TWHRE(0x1e)) 316 #define CONFIG_SYS_NAND_FTIM3 0x0 317 318 #define CONFIG_SYS_NAND_DDR_LAW 11 319 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 320 #define CONFIG_SYS_MAX_NAND_DEVICE 1 321 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 322 323 #if defined(CONFIG_NAND) 324 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 325 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 326 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 327 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 328 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 329 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 330 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 331 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 332 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 340 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 341 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 342 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 343 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 344 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 345 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 346 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 347 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 348 #else 349 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 350 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 351 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 352 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 353 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 354 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 355 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 356 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 357 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 358 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 359 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 360 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 361 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 362 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 363 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 364 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 365 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 366 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 367 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 368 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 369 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 370 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 371 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 372 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 373 #endif 374 375 #if defined(CONFIG_RAMBOOT_PBL) 376 #define CONFIG_SYS_RAMBOOT 377 #endif 378 379 #ifdef CONFIG_SPL_BUILD 380 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 381 #else 382 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 383 #endif 384 385 #define CONFIG_HWCONFIG 386 387 /* define to use L1 as initial stack */ 388 #define CONFIG_L1_INIT_RAM 389 #define CONFIG_SYS_INIT_RAM_LOCK 390 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 393 /* The assembler doesn't like typecast */ 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 395 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 396 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 397 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 398 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 399 GENERATED_GBL_DATA_SIZE) 400 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 401 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 402 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 403 404 /* 405 * Serial Port 406 */ 407 #define CONFIG_SYS_NS16550_SERIAL 408 #define CONFIG_SYS_NS16550_REG_SIZE 1 409 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 410 #define CONFIG_SYS_BAUDRATE_TABLE \ 411 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 412 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 413 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 414 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 415 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 416 417 /* 418 * I2C 419 */ 420 #define CONFIG_SYS_I2C 421 #define CONFIG_SYS_I2C_FSL 422 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 423 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 424 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 425 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 426 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 427 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 428 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 429 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 430 #define CONFIG_SYS_FSL_I2C_SPEED 100000 431 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 432 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 433 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 434 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 435 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 436 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 437 #define I2C_MUX_CH_DEFAULT 0x8 438 439 #define I2C_MUX_CH_VOL_MONITOR 0xa 440 441 /* Voltage monitor on channel 2*/ 442 #define I2C_VOL_MONITOR_ADDR 0x40 443 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 444 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 445 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 446 447 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 448 #ifndef CONFIG_SPL_BUILD 449 #define CONFIG_VID 450 #endif 451 #define CONFIG_VOL_MONITOR_IR36021_SET 452 #define CONFIG_VOL_MONITOR_IR36021_READ 453 /* The lowest and highest voltage allowed for T208xQDS */ 454 #define VDD_MV_MIN 819 455 #define VDD_MV_MAX 1212 456 457 /* 458 * RapidIO 459 */ 460 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 461 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 462 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 463 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 464 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 465 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 466 /* 467 * for slave u-boot IMAGE instored in master memory space, 468 * PHYS must be aligned based on the SIZE 469 */ 470 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 471 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 472 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 473 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 474 /* 475 * for slave UCODE and ENV instored in master memory space, 476 * PHYS must be aligned based on the SIZE 477 */ 478 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 479 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 480 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 481 482 /* slave core release by master*/ 483 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 484 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 485 486 /* 487 * SRIO_PCIE_BOOT - SLAVE 488 */ 489 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 490 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 491 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 492 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 493 #endif 494 495 /* 496 * eSPI - Enhanced SPI 497 */ 498 #ifdef CONFIG_SPI_FLASH 499 500 #define CONFIG_SF_DEFAULT_SPEED 10000000 501 #define CONFIG_SF_DEFAULT_MODE 0 502 #endif 503 504 /* 505 * General PCI 506 * Memory space is mapped 1-1, but I/O space must start from 0. 507 */ 508 #define CONFIG_PCIE1 /* PCIE controller 1 */ 509 #define CONFIG_PCIE2 /* PCIE controller 2 */ 510 #define CONFIG_PCIE3 /* PCIE controller 3 */ 511 #define CONFIG_PCIE4 /* PCIE controller 4 */ 512 #define CONFIG_FSL_PCIE_RESET /* pcie reset fix link width 2x-4x*/ 513 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 514 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 515 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 516 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 517 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 518 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 519 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 520 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 521 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 522 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 523 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 524 525 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 526 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 527 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 528 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 529 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 530 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 531 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 532 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 533 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 534 535 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 536 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 537 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 538 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 539 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 540 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 541 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 542 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 543 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 544 545 /* controller 4, Base address 203000 */ 546 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 547 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 548 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 549 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 550 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 551 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 552 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 553 554 #ifdef CONFIG_PCI 555 #define CONFIG_PCI_INDIRECT_BRIDGE 556 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 557 #endif 558 559 /* Qman/Bman */ 560 #ifndef CONFIG_NOBQFMAN 561 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 562 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 563 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 564 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 565 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 566 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 567 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 568 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 569 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 570 CONFIG_SYS_BMAN_CENA_SIZE) 571 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 572 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 573 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 574 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 575 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 576 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 577 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 578 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 579 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 580 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 581 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 582 CONFIG_SYS_QMAN_CENA_SIZE) 583 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 584 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 585 586 #define CONFIG_SYS_DPAA_FMAN 587 #define CONFIG_SYS_DPAA_PME 588 #define CONFIG_SYS_PMAN 589 #define CONFIG_SYS_DPAA_DCE 590 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 591 #define CONFIG_SYS_INTERLAKEN 592 593 /* Default address of microcode for the Linux Fman driver */ 594 #if defined(CONFIG_SPIFLASH) 595 /* 596 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 597 * env, so we got 0x110000. 598 */ 599 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 600 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 601 #elif defined(CONFIG_SDCARD) 602 /* 603 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 604 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 605 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 606 */ 607 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 608 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 609 #elif defined(CONFIG_NAND) 610 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 611 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 612 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 613 /* 614 * Slave has no ucode locally, it can fetch this from remote. When implementing 615 * in two corenet boards, slave's ucode could be stored in master's memory 616 * space, the address can be mapped from slave TLB->slave LAW-> 617 * slave SRIO or PCIE outbound window->master inbound window-> 618 * master LAW->the ucode address in master's memory space. 619 */ 620 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 621 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 622 #else 623 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 624 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 625 #endif 626 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 627 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 628 #endif /* CONFIG_NOBQFMAN */ 629 630 #ifdef CONFIG_SYS_DPAA_FMAN 631 #define CONFIG_FMAN_ENET 632 #define CONFIG_PHY_VITESSE 633 #define CONFIG_PHY_REALTEK 634 #define CONFIG_PHY_TERANETICS 635 #define RGMII_PHY1_ADDR 0x1 636 #define RGMII_PHY2_ADDR 0x2 637 #define FM1_10GEC1_PHY_ADDR 0x3 638 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 639 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 640 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 641 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 642 #endif 643 644 #ifdef CONFIG_FMAN_ENET 645 #define CONFIG_ETHPRIME "FM1@DTSEC3" 646 #endif 647 648 /* 649 * SATA 650 */ 651 #ifdef CONFIG_FSL_SATA_V2 652 #define CONFIG_SYS_SATA_MAX_DEVICE 2 653 #define CONFIG_SATA1 654 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 655 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 656 #define CONFIG_SATA2 657 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 658 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 659 #define CONFIG_LBA48 660 #endif 661 662 /* 663 * USB 664 */ 665 #ifdef CONFIG_USB_EHCI_HCD 666 #define CONFIG_USB_EHCI_FSL 667 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 668 #define CONFIG_HAS_FSL_DR_USB 669 #endif 670 671 /* 672 * SDHC 673 */ 674 #ifdef CONFIG_MMC 675 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 676 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 677 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 678 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 679 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 680 #endif 681 682 /* 683 * Dynamic MTD Partition support with mtdparts 684 */ 685 686 /* 687 * Environment 688 */ 689 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 690 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 691 692 /* 693 * Miscellaneous configurable options 694 */ 695 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 696 697 /* 698 * For booting Linux, the board info and command line data 699 * have to be in the first 64 MB of memory, since this is 700 * the maximum mapped by the Linux kernel during initialization. 701 */ 702 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 703 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 704 705 #ifdef CONFIG_CMD_KGDB 706 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 707 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 708 #endif 709 710 /* 711 * Environment Configuration 712 */ 713 #define CONFIG_ROOTPATH "/opt/nfsroot" 714 #define CONFIG_BOOTFILE "uImage" 715 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 716 717 /* default location for tftp and bootm */ 718 #define CONFIG_LOADADDR 1000000 719 #define __USB_PHY_TYPE utmi 720 721 #define CONFIG_EXTRA_ENV_SETTINGS \ 722 "hwconfig=fsl_ddr:" \ 723 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 724 "bank_intlv=auto;" \ 725 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 726 "netdev=eth0\0" \ 727 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 728 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 729 "tftpflash=tftpboot $loadaddr $uboot && " \ 730 "protect off $ubootaddr +$filesize && " \ 731 "erase $ubootaddr +$filesize && " \ 732 "cp.b $loadaddr $ubootaddr $filesize && " \ 733 "protect on $ubootaddr +$filesize && " \ 734 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 735 "consoledev=ttyS0\0" \ 736 "ramdiskaddr=2000000\0" \ 737 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 738 "fdtaddr=1e00000\0" \ 739 "fdtfile=t2080qds/t2080qds.dtb\0" \ 740 "bdev=sda3\0" 741 742 /* 743 * For emulation this causes u-boot to jump to the start of the 744 * proof point app code automatically 745 */ 746 #define CONFIG_PROOF_POINTS \ 747 "setenv bootargs root=/dev/$bdev rw " \ 748 "console=$consoledev,$baudrate $othbootargs;" \ 749 "cpu 1 release 0x29000000 - - -;" \ 750 "cpu 2 release 0x29000000 - - -;" \ 751 "cpu 3 release 0x29000000 - - -;" \ 752 "cpu 4 release 0x29000000 - - -;" \ 753 "cpu 5 release 0x29000000 - - -;" \ 754 "cpu 6 release 0x29000000 - - -;" \ 755 "cpu 7 release 0x29000000 - - -;" \ 756 "go 0x29000000" 757 758 #define CONFIG_HVBOOT \ 759 "setenv bootargs config-addr=0x60000000; " \ 760 "bootm 0x01000000 - 0x00f00000" 761 762 #define CONFIG_ALU \ 763 "setenv bootargs root=/dev/$bdev rw " \ 764 "console=$consoledev,$baudrate $othbootargs;" \ 765 "cpu 1 release 0x01000000 - - -;" \ 766 "cpu 2 release 0x01000000 - - -;" \ 767 "cpu 3 release 0x01000000 - - -;" \ 768 "cpu 4 release 0x01000000 - - -;" \ 769 "cpu 5 release 0x01000000 - - -;" \ 770 "cpu 6 release 0x01000000 - - -;" \ 771 "cpu 7 release 0x01000000 - - -;" \ 772 "go 0x01000000" 773 774 #define CONFIG_LINUX \ 775 "setenv bootargs root=/dev/ram rw " \ 776 "console=$consoledev,$baudrate $othbootargs;" \ 777 "setenv ramdiskaddr 0x02000000;" \ 778 "setenv fdtaddr 0x00c00000;" \ 779 "setenv loadaddr 0x1000000;" \ 780 "bootm $loadaddr $ramdiskaddr $fdtaddr" 781 782 #define CONFIG_HDBOOT \ 783 "setenv bootargs root=/dev/$bdev rw " \ 784 "console=$consoledev,$baudrate $othbootargs;" \ 785 "tftp $loadaddr $bootfile;" \ 786 "tftp $fdtaddr $fdtfile;" \ 787 "bootm $loadaddr - $fdtaddr" 788 789 #define CONFIG_NFSBOOTCOMMAND \ 790 "setenv bootargs root=/dev/nfs rw " \ 791 "nfsroot=$serverip:$rootpath " \ 792 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 793 "console=$consoledev,$baudrate $othbootargs;" \ 794 "tftp $loadaddr $bootfile;" \ 795 "tftp $fdtaddr $fdtfile;" \ 796 "bootm $loadaddr - $fdtaddr" 797 798 #define CONFIG_RAMBOOTCOMMAND \ 799 "setenv bootargs root=/dev/ram rw " \ 800 "console=$consoledev,$baudrate $othbootargs;" \ 801 "tftp $ramdiskaddr $ramdiskfile;" \ 802 "tftp $loadaddr $bootfile;" \ 803 "tftp $fdtaddr $fdtfile;" \ 804 "bootm $loadaddr $ramdiskaddr $fdtaddr" 805 806 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 807 808 #include <asm/fsl_secure_boot.h> 809 810 #endif /* __T208xQDS_H */ 811