1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #define CONFIG_USB_EHCI 16 #if defined(CONFIG_ARCH_T2080) 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 19 #define CONFIG_SRIO1 /* SRIO port 1 */ 20 #define CONFIG_SRIO2 /* SRIO port 2 */ 21 #elif defined(CONFIG_ARCH_T2081) 22 #endif 23 24 /* High Level Configuration Options */ 25 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 26 #define CONFIG_MP /* support multiple processors */ 27 #define CONFIG_ENABLE_36BIT_PHYS 28 29 #ifdef CONFIG_PHYS_64BIT 30 #define CONFIG_ADDR_MAP 1 31 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 32 #endif 33 34 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 35 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 36 #define CONFIG_ENV_OVERWRITE 37 38 #ifdef CONFIG_RAMBOOT_PBL 39 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 40 41 #define CONFIG_SPL_FLUSH_IMAGE 42 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 43 #define CONFIG_SYS_TEXT_BASE 0x00201000 44 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 45 #define CONFIG_SPL_PAD_TO 0x40000 46 #define CONFIG_SPL_MAX_SIZE 0x28000 47 #define RESET_VECTOR_OFFSET 0x27FFC 48 #define BOOT_PAGE_OFFSET 0x27000 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SPL_SKIP_RELOCATE 51 #define CONFIG_SPL_COMMON_INIT_DDR 52 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 53 #endif 54 55 #ifdef CONFIG_NAND 56 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 57 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 58 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 59 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 60 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 61 #if defined(CONFIG_ARCH_T2080) 62 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 63 #elif defined(CONFIG_ARCH_T2081) 64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 65 #endif 66 #define CONFIG_SPL_NAND_BOOT 67 #endif 68 69 #ifdef CONFIG_SPIFLASH 70 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 71 #define CONFIG_SPL_SPI_FLASH_MINIMAL 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 75 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 76 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 77 #ifndef CONFIG_SPL_BUILD 78 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 79 #endif 80 #if defined(CONFIG_ARCH_T2080) 81 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 82 #elif defined(CONFIG_ARCH_T2081) 83 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 84 #endif 85 #define CONFIG_SPL_SPI_BOOT 86 #endif 87 88 #ifdef CONFIG_SDCARD 89 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 90 #define CONFIG_SPL_MMC_MINIMAL 91 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 92 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 93 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 94 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 95 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 96 #ifndef CONFIG_SPL_BUILD 97 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 98 #endif 99 #if defined(CONFIG_ARCH_T2080) 100 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 101 #elif defined(CONFIG_ARCH_T2081) 102 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 103 #endif 104 #define CONFIG_SPL_MMC_BOOT 105 #endif 106 107 #endif /* CONFIG_RAMBOOT_PBL */ 108 109 #define CONFIG_SRIO_PCIE_BOOT_MASTER 110 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 111 /* Set 1M boot space */ 112 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 113 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 114 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 115 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 116 #endif 117 118 #ifndef CONFIG_SYS_TEXT_BASE 119 #define CONFIG_SYS_TEXT_BASE 0xeff40000 120 #endif 121 122 #ifndef CONFIG_RESET_VECTOR_ADDRESS 123 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 124 #endif 125 126 /* 127 * These can be toggled for performance analysis, otherwise use default. 128 */ 129 #define CONFIG_SYS_CACHE_STASHING 130 #define CONFIG_BTB /* toggle branch predition */ 131 #define CONFIG_DDR_ECC 132 #ifdef CONFIG_DDR_ECC 133 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 134 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 135 #endif 136 137 #ifdef CONFIG_MTD_NOR_FLASH 138 #define CONFIG_FLASH_CFI_DRIVER 139 #define CONFIG_SYS_FLASH_CFI 140 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 141 #endif 142 143 #if defined(CONFIG_SPIFLASH) 144 #define CONFIG_SYS_EXTRA_ENV_RELOC 145 #define CONFIG_ENV_IS_IN_SPI_FLASH 146 #define CONFIG_ENV_SPI_BUS 0 147 #define CONFIG_ENV_SPI_CS 0 148 #define CONFIG_ENV_SPI_MAX_HZ 10000000 149 #define CONFIG_ENV_SPI_MODE 0 150 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 151 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 152 #define CONFIG_ENV_SECT_SIZE 0x10000 153 #elif defined(CONFIG_SDCARD) 154 #define CONFIG_SYS_EXTRA_ENV_RELOC 155 #define CONFIG_ENV_IS_IN_MMC 156 #define CONFIG_SYS_MMC_ENV_DEV 0 157 #define CONFIG_ENV_SIZE 0x2000 158 #define CONFIG_ENV_OFFSET (512 * 0x800) 159 #elif defined(CONFIG_NAND) 160 #define CONFIG_SYS_EXTRA_ENV_RELOC 161 #define CONFIG_ENV_IS_IN_NAND 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 164 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 165 #define CONFIG_ENV_IS_IN_REMOTE 166 #define CONFIG_ENV_ADDR 0xffe20000 167 #define CONFIG_ENV_SIZE 0x2000 168 #elif defined(CONFIG_ENV_IS_NOWHERE) 169 #define CONFIG_ENV_SIZE 0x2000 170 #else 171 #define CONFIG_ENV_IS_IN_FLASH 172 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 173 #define CONFIG_ENV_SIZE 0x2000 174 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 175 #endif 176 177 #ifndef __ASSEMBLY__ 178 unsigned long get_board_sys_clk(void); 179 unsigned long get_board_ddr_clk(void); 180 #endif 181 182 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 183 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 184 185 /* 186 * Config the L3 Cache as L3 SRAM 187 */ 188 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 189 #define CONFIG_SYS_L3_SIZE (512 << 10) 190 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 191 #ifdef CONFIG_RAMBOOT_PBL 192 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 193 #endif 194 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 195 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 196 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 197 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 198 199 #define CONFIG_SYS_DCSRBAR 0xf0000000 200 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 201 202 /* EEPROM */ 203 #define CONFIG_ID_EEPROM 204 #define CONFIG_SYS_I2C_EEPROM_NXID 205 #define CONFIG_SYS_EEPROM_BUS_NUM 0 206 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 207 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 208 209 /* 210 * DDR Setup 211 */ 212 #define CONFIG_VERY_BIG_RAM 213 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 214 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 215 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 216 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 217 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 218 #define CONFIG_DDR_SPD 219 #define CONFIG_FSL_DDR_INTERACTIVE 220 #define CONFIG_SYS_SPD_BUS_NUM 0 221 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 222 #define SPD_EEPROM_ADDRESS1 0x51 223 #define SPD_EEPROM_ADDRESS2 0x52 224 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 225 #define CTRL_INTLV_PREFERED cacheline 226 227 /* 228 * IFC Definitions 229 */ 230 #define CONFIG_SYS_FLASH_BASE 0xe0000000 231 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 232 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 233 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 234 + 0x8000000) | \ 235 CSPR_PORT_SIZE_16 | \ 236 CSPR_MSEL_NOR | \ 237 CSPR_V) 238 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 239 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 240 CSPR_PORT_SIZE_16 | \ 241 CSPR_MSEL_NOR | \ 242 CSPR_V) 243 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 244 /* NOR Flash Timing Params */ 245 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 246 247 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 248 FTIM0_NOR_TEADC(0x5) | \ 249 FTIM0_NOR_TEAHC(0x5)) 250 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 251 FTIM1_NOR_TRAD_NOR(0x1A) |\ 252 FTIM1_NOR_TSEQRAD_NOR(0x13)) 253 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 254 FTIM2_NOR_TCH(0x4) | \ 255 FTIM2_NOR_TWPH(0x0E) | \ 256 FTIM2_NOR_TWP(0x1c)) 257 #define CONFIG_SYS_NOR_FTIM3 0x0 258 259 #define CONFIG_SYS_FLASH_QUIET_TEST 260 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 261 262 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 263 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 264 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 265 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 266 267 #define CONFIG_SYS_FLASH_EMPTY_INFO 268 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 269 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 270 271 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 272 #define QIXIS_BASE 0xffdf0000 273 #define QIXIS_LBMAP_SWITCH 6 274 #define QIXIS_LBMAP_MASK 0x0f 275 #define QIXIS_LBMAP_SHIFT 0 276 #define QIXIS_LBMAP_DFLTBANK 0x00 277 #define QIXIS_LBMAP_ALTBANK 0x04 278 #define QIXIS_LBMAP_NAND 0x09 279 #define QIXIS_LBMAP_SD 0x00 280 #define QIXIS_RCW_SRC_NAND 0x104 281 #define QIXIS_RCW_SRC_SD 0x040 282 #define QIXIS_RST_CTL_RESET 0x83 283 #define QIXIS_RST_FORCE_MEM 0x1 284 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 285 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 286 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 287 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 288 289 #define CONFIG_SYS_CSPR3_EXT (0xf) 290 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 291 | CSPR_PORT_SIZE_8 \ 292 | CSPR_MSEL_GPCM \ 293 | CSPR_V) 294 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 295 #define CONFIG_SYS_CSOR3 0x0 296 /* QIXIS Timing parameters for IFC CS3 */ 297 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 298 FTIM0_GPCM_TEADC(0x0e) | \ 299 FTIM0_GPCM_TEAHC(0x0e)) 300 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 301 FTIM1_GPCM_TRAD(0x3f)) 302 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 303 FTIM2_GPCM_TCH(0x8) | \ 304 FTIM2_GPCM_TWP(0x1f)) 305 #define CONFIG_SYS_CS3_FTIM3 0x0 306 307 /* NAND Flash on IFC */ 308 #define CONFIG_NAND_FSL_IFC 309 #define CONFIG_SYS_NAND_BASE 0xff800000 310 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 311 312 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 313 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 314 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 315 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 316 | CSPR_V) 317 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 318 319 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 320 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 321 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 322 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 323 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 324 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 325 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 326 327 #define CONFIG_SYS_NAND_ONFI_DETECTION 328 329 /* ONFI NAND Flash mode0 Timing Params */ 330 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 331 FTIM0_NAND_TWP(0x18) | \ 332 FTIM0_NAND_TWCHT(0x07) | \ 333 FTIM0_NAND_TWH(0x0a)) 334 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 335 FTIM1_NAND_TWBE(0x39) | \ 336 FTIM1_NAND_TRR(0x0e) | \ 337 FTIM1_NAND_TRP(0x18)) 338 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 339 FTIM2_NAND_TREH(0x0a) | \ 340 FTIM2_NAND_TWHRE(0x1e)) 341 #define CONFIG_SYS_NAND_FTIM3 0x0 342 343 #define CONFIG_SYS_NAND_DDR_LAW 11 344 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 345 #define CONFIG_SYS_MAX_NAND_DEVICE 1 346 #define CONFIG_CMD_NAND 347 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 348 349 #if defined(CONFIG_NAND) 350 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 351 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 352 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 353 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 354 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 355 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 356 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 357 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 358 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 359 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 360 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 361 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 362 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 363 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 364 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 365 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 366 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 367 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 368 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 369 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 370 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 371 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 372 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 373 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 374 #else 375 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 376 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 377 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 378 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 379 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 380 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 381 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 382 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 383 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 384 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 385 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 386 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 387 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 388 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 389 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 390 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 391 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 392 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 393 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 394 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 395 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 396 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 397 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 398 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 399 #endif 400 401 #if defined(CONFIG_RAMBOOT_PBL) 402 #define CONFIG_SYS_RAMBOOT 403 #endif 404 405 #ifdef CONFIG_SPL_BUILD 406 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 407 #else 408 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 409 #endif 410 411 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 412 #define CONFIG_MISC_INIT_R 413 #define CONFIG_HWCONFIG 414 415 /* define to use L1 as initial stack */ 416 #define CONFIG_L1_INIT_RAM 417 #define CONFIG_SYS_INIT_RAM_LOCK 418 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 420 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 421 /* The assembler doesn't like typecast */ 422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 423 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 424 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 425 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 426 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 427 GENERATED_GBL_DATA_SIZE) 428 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 429 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 430 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 431 432 /* 433 * Serial Port 434 */ 435 #define CONFIG_CONS_INDEX 1 436 #define CONFIG_SYS_NS16550_SERIAL 437 #define CONFIG_SYS_NS16550_REG_SIZE 1 438 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 439 #define CONFIG_SYS_BAUDRATE_TABLE \ 440 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 441 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 442 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 443 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 444 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 445 446 /* 447 * I2C 448 */ 449 #define CONFIG_SYS_I2C 450 #define CONFIG_SYS_I2C_FSL 451 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 452 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 453 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 454 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 455 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 456 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 457 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 458 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 459 #define CONFIG_SYS_FSL_I2C_SPEED 100000 460 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 461 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 462 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 463 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 464 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 465 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 466 #define I2C_MUX_CH_DEFAULT 0x8 467 468 #define I2C_MUX_CH_VOL_MONITOR 0xa 469 470 /* Voltage monitor on channel 2*/ 471 #define I2C_VOL_MONITOR_ADDR 0x40 472 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 473 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 474 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 475 476 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 477 #ifndef CONFIG_SPL_BUILD 478 #define CONFIG_VID 479 #endif 480 #define CONFIG_VOL_MONITOR_IR36021_SET 481 #define CONFIG_VOL_MONITOR_IR36021_READ 482 /* The lowest and highest voltage allowed for T208xQDS */ 483 #define VDD_MV_MIN 819 484 #define VDD_MV_MAX 1212 485 486 /* 487 * RapidIO 488 */ 489 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 490 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 491 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 492 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 493 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 494 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 495 /* 496 * for slave u-boot IMAGE instored in master memory space, 497 * PHYS must be aligned based on the SIZE 498 */ 499 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 500 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 503 /* 504 * for slave UCODE and ENV instored in master memory space, 505 * PHYS must be aligned based on the SIZE 506 */ 507 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 508 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 509 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 510 511 /* slave core release by master*/ 512 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 513 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 514 515 /* 516 * SRIO_PCIE_BOOT - SLAVE 517 */ 518 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 519 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 520 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 521 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 522 #endif 523 524 /* 525 * eSPI - Enhanced SPI 526 */ 527 #ifdef CONFIG_SPI_FLASH 528 #ifndef CONFIG_SPL_BUILD 529 #endif 530 531 #define CONFIG_SPI_FLASH_BAR 532 #define CONFIG_SF_DEFAULT_SPEED 10000000 533 #define CONFIG_SF_DEFAULT_MODE 0 534 #endif 535 536 /* 537 * General PCI 538 * Memory space is mapped 1-1, but I/O space must start from 0. 539 */ 540 #define CONFIG_PCIE1 /* PCIE controller 1 */ 541 #define CONFIG_PCIE2 /* PCIE controller 2 */ 542 #define CONFIG_PCIE3 /* PCIE controller 3 */ 543 #define CONFIG_PCIE4 /* PCIE controller 4 */ 544 #define CONFIG_FSL_PCIE_RESET 545 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 546 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 547 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 548 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 549 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 550 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 551 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 552 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 553 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 554 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 555 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 556 557 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 558 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 559 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 560 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 561 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 562 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 563 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 564 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 565 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 566 567 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 568 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 569 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 570 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 571 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 572 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 573 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 574 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 575 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 576 577 /* controller 4, Base address 203000 */ 578 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 579 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 580 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 581 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 582 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 583 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 584 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 585 586 #ifdef CONFIG_PCI 587 #define CONFIG_PCI_INDIRECT_BRIDGE 588 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 589 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 590 #endif 591 592 /* Qman/Bman */ 593 #ifndef CONFIG_NOBQFMAN 594 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 595 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 596 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 597 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 598 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 599 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 600 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 601 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 602 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 603 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 604 CONFIG_SYS_BMAN_CENA_SIZE) 605 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 606 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 607 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 608 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 609 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 610 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 611 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 612 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 613 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 614 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 615 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 616 CONFIG_SYS_QMAN_CENA_SIZE) 617 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 618 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 619 620 #define CONFIG_SYS_DPAA_FMAN 621 #define CONFIG_SYS_DPAA_PME 622 #define CONFIG_SYS_PMAN 623 #define CONFIG_SYS_DPAA_DCE 624 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 625 #define CONFIG_SYS_INTERLAKEN 626 627 /* Default address of microcode for the Linux Fman driver */ 628 #if defined(CONFIG_SPIFLASH) 629 /* 630 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 631 * env, so we got 0x110000. 632 */ 633 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 634 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 635 #elif defined(CONFIG_SDCARD) 636 /* 637 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 638 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 639 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 640 */ 641 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 642 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 643 #elif defined(CONFIG_NAND) 644 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 645 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 646 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 647 /* 648 * Slave has no ucode locally, it can fetch this from remote. When implementing 649 * in two corenet boards, slave's ucode could be stored in master's memory 650 * space, the address can be mapped from slave TLB->slave LAW-> 651 * slave SRIO or PCIE outbound window->master inbound window-> 652 * master LAW->the ucode address in master's memory space. 653 */ 654 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 655 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 656 #else 657 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 658 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 659 #endif 660 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 661 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 662 #endif /* CONFIG_NOBQFMAN */ 663 664 #ifdef CONFIG_SYS_DPAA_FMAN 665 #define CONFIG_FMAN_ENET 666 #define CONFIG_PHYLIB_10G 667 #define CONFIG_PHY_VITESSE 668 #define CONFIG_PHY_REALTEK 669 #define CONFIG_PHY_TERANETICS 670 #define RGMII_PHY1_ADDR 0x1 671 #define RGMII_PHY2_ADDR 0x2 672 #define FM1_10GEC1_PHY_ADDR 0x3 673 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 674 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 675 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 676 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 677 #endif 678 679 #ifdef CONFIG_FMAN_ENET 680 #define CONFIG_MII /* MII PHY management */ 681 #define CONFIG_ETHPRIME "FM1@DTSEC3" 682 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 683 #endif 684 685 /* 686 * SATA 687 */ 688 #ifdef CONFIG_FSL_SATA_V2 689 #define CONFIG_LIBATA 690 #define CONFIG_FSL_SATA 691 #define CONFIG_SYS_SATA_MAX_DEVICE 2 692 #define CONFIG_SATA1 693 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 694 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 695 #define CONFIG_SATA2 696 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 697 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 698 #define CONFIG_LBA48 699 #define CONFIG_CMD_SATA 700 #endif 701 702 /* 703 * USB 704 */ 705 #ifdef CONFIG_USB_EHCI 706 #define CONFIG_USB_EHCI_FSL 707 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 708 #define CONFIG_HAS_FSL_DR_USB 709 #endif 710 711 /* 712 * SDHC 713 */ 714 #ifdef CONFIG_MMC 715 #define CONFIG_FSL_ESDHC 716 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 717 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 718 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 719 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 720 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 721 #endif 722 723 /* 724 * Dynamic MTD Partition support with mtdparts 725 */ 726 #ifdef CONFIG_MTD_NOR_FLASH 727 #define CONFIG_MTD_DEVICE 728 #define CONFIG_MTD_PARTITIONS 729 #define CONFIG_CMD_MTDPARTS 730 #define CONFIG_FLASH_CFI_MTD 731 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 732 "spi0=spife110000.0" 733 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 734 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 735 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 736 "1m(uboot),5m(kernel),128k(dtb),-(user)" 737 #endif 738 739 /* 740 * Environment 741 */ 742 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 743 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 744 745 /* 746 * Command line configuration. 747 */ 748 #define CONFIG_CMD_ERRATA 749 #define CONFIG_CMD_IRQ 750 #define CONFIG_CMD_REGINFO 751 752 #ifdef CONFIG_PCI 753 #define CONFIG_CMD_PCI 754 #endif 755 756 /* Hash command with SHA acceleration supported in hardware */ 757 #ifdef CONFIG_FSL_CAAM 758 #define CONFIG_CMD_HASH 759 #define CONFIG_SHA_HW_ACCEL 760 #endif 761 762 /* 763 * Miscellaneous configurable options 764 */ 765 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 766 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 767 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 768 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 769 #ifdef CONFIG_CMD_KGDB 770 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 771 #else 772 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 773 #endif 774 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 775 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 776 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 777 778 /* 779 * For booting Linux, the board info and command line data 780 * have to be in the first 64 MB of memory, since this is 781 * the maximum mapped by the Linux kernel during initialization. 782 */ 783 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 784 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 785 786 #ifdef CONFIG_CMD_KGDB 787 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 788 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 789 #endif 790 791 /* 792 * Environment Configuration 793 */ 794 #define CONFIG_ROOTPATH "/opt/nfsroot" 795 #define CONFIG_BOOTFILE "uImage" 796 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 797 798 /* default location for tftp and bootm */ 799 #define CONFIG_LOADADDR 1000000 800 #define __USB_PHY_TYPE utmi 801 802 #define CONFIG_EXTRA_ENV_SETTINGS \ 803 "hwconfig=fsl_ddr:" \ 804 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 805 "bank_intlv=auto;" \ 806 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 807 "netdev=eth0\0" \ 808 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 809 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 810 "tftpflash=tftpboot $loadaddr $uboot && " \ 811 "protect off $ubootaddr +$filesize && " \ 812 "erase $ubootaddr +$filesize && " \ 813 "cp.b $loadaddr $ubootaddr $filesize && " \ 814 "protect on $ubootaddr +$filesize && " \ 815 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 816 "consoledev=ttyS0\0" \ 817 "ramdiskaddr=2000000\0" \ 818 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 819 "fdtaddr=1e00000\0" \ 820 "fdtfile=t2080qds/t2080qds.dtb\0" \ 821 "bdev=sda3\0" 822 823 /* 824 * For emulation this causes u-boot to jump to the start of the 825 * proof point app code automatically 826 */ 827 #define CONFIG_PROOF_POINTS \ 828 "setenv bootargs root=/dev/$bdev rw " \ 829 "console=$consoledev,$baudrate $othbootargs;" \ 830 "cpu 1 release 0x29000000 - - -;" \ 831 "cpu 2 release 0x29000000 - - -;" \ 832 "cpu 3 release 0x29000000 - - -;" \ 833 "cpu 4 release 0x29000000 - - -;" \ 834 "cpu 5 release 0x29000000 - - -;" \ 835 "cpu 6 release 0x29000000 - - -;" \ 836 "cpu 7 release 0x29000000 - - -;" \ 837 "go 0x29000000" 838 839 #define CONFIG_HVBOOT \ 840 "setenv bootargs config-addr=0x60000000; " \ 841 "bootm 0x01000000 - 0x00f00000" 842 843 #define CONFIG_ALU \ 844 "setenv bootargs root=/dev/$bdev rw " \ 845 "console=$consoledev,$baudrate $othbootargs;" \ 846 "cpu 1 release 0x01000000 - - -;" \ 847 "cpu 2 release 0x01000000 - - -;" \ 848 "cpu 3 release 0x01000000 - - -;" \ 849 "cpu 4 release 0x01000000 - - -;" \ 850 "cpu 5 release 0x01000000 - - -;" \ 851 "cpu 6 release 0x01000000 - - -;" \ 852 "cpu 7 release 0x01000000 - - -;" \ 853 "go 0x01000000" 854 855 #define CONFIG_LINUX \ 856 "setenv bootargs root=/dev/ram rw " \ 857 "console=$consoledev,$baudrate $othbootargs;" \ 858 "setenv ramdiskaddr 0x02000000;" \ 859 "setenv fdtaddr 0x00c00000;" \ 860 "setenv loadaddr 0x1000000;" \ 861 "bootm $loadaddr $ramdiskaddr $fdtaddr" 862 863 #define CONFIG_HDBOOT \ 864 "setenv bootargs root=/dev/$bdev rw " \ 865 "console=$consoledev,$baudrate $othbootargs;" \ 866 "tftp $loadaddr $bootfile;" \ 867 "tftp $fdtaddr $fdtfile;" \ 868 "bootm $loadaddr - $fdtaddr" 869 870 #define CONFIG_NFSBOOTCOMMAND \ 871 "setenv bootargs root=/dev/nfs rw " \ 872 "nfsroot=$serverip:$rootpath " \ 873 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 874 "console=$consoledev,$baudrate $othbootargs;" \ 875 "tftp $loadaddr $bootfile;" \ 876 "tftp $fdtaddr $fdtfile;" \ 877 "bootm $loadaddr - $fdtaddr" 878 879 #define CONFIG_RAMBOOTCOMMAND \ 880 "setenv bootargs root=/dev/ram rw " \ 881 "console=$consoledev,$baudrate $othbootargs;" \ 882 "tftp $ramdiskaddr $ramdiskfile;" \ 883 "tftp $loadaddr $bootfile;" \ 884 "tftp $fdtaddr $fdtfile;" \ 885 "bootm $loadaddr $ramdiskaddr $fdtaddr" 886 887 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 888 889 #include <asm/fsl_secure_boot.h> 890 891 #endif /* __T208xQDS_H */ 892