1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 #define CONFIG_MMC 18 #define CONFIG_SPI_FLASH 19 #define CONFIG_USB_EHCI 20 #if defined(CONFIG_PPC_T2080) 21 #define CONFIG_T2080QDS 22 #define CONFIG_FSL_SATA_V2 23 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 24 #define CONFIG_SRIO1 /* SRIO port 1 */ 25 #define CONFIG_SRIO2 /* SRIO port 2 */ 26 #elif defined(CONFIG_PPC_T2081) 27 #define CONFIG_T2081QDS 28 #endif 29 30 /* High Level Configuration Options */ 31 #define CONFIG_PHYS_64BIT 32 #define CONFIG_BOOKE 33 #define CONFIG_E500 /* BOOKE e500 family */ 34 #define CONFIG_E500MC /* BOOKE e500mc family */ 35 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 36 #define CONFIG_MP /* support multiple processors */ 37 #define CONFIG_ENABLE_36BIT_PHYS 38 39 #ifdef CONFIG_PHYS_64BIT 40 #define CONFIG_ADDR_MAP 1 41 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 42 #endif 43 44 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 45 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 46 #define CONFIG_FSL_IFC /* Enable IFC Support */ 47 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 48 #define CONFIG_FSL_LAW /* Use common FSL init code */ 49 #define CONFIG_ENV_OVERWRITE 50 51 #ifdef CONFIG_RAMBOOT_PBL 52 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 53 #if defined(CONFIG_PPC_T2080) 54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg 55 #elif defined(CONFIG_PPC_T2081) 56 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg 57 #endif 58 59 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 60 #define CONFIG_SPL_ENV_SUPPORT 61 #define CONFIG_SPL_SERIAL_SUPPORT 62 #define CONFIG_SPL_FLUSH_IMAGE 63 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 64 #define CONFIG_SPL_LIBGENERIC_SUPPORT 65 #define CONFIG_SPL_LIBCOMMON_SUPPORT 66 #define CONFIG_SPL_I2C_SUPPORT 67 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 68 #define CONFIG_FSL_LAW /* Use common FSL init code */ 69 #define CONFIG_SYS_TEXT_BASE 0x00201000 70 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 71 #define CONFIG_SPL_PAD_TO 0x40000 72 #define CONFIG_SPL_MAX_SIZE 0x28000 73 #define RESET_VECTOR_OFFSET 0x27FFC 74 #define BOOT_PAGE_OFFSET 0x27000 75 #ifdef CONFIG_SPL_BUILD 76 #define CONFIG_SPL_SKIP_RELOCATE 77 #define CONFIG_SPL_COMMON_INIT_DDR 78 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 79 #define CONFIG_SYS_NO_FLASH 80 #endif 81 82 #ifdef CONFIG_NAND 83 #define CONFIG_SPL_NAND_SUPPORT 84 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 85 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 86 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 87 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 88 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 89 #define CONFIG_SPL_NAND_BOOT 90 #endif 91 92 #ifdef CONFIG_SPIFLASH 93 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 94 #define CONFIG_SPL_SPI_SUPPORT 95 #define CONFIG_SPL_SPI_FLASH_SUPPORT 96 #define CONFIG_SPL_SPI_FLASH_MINIMAL 97 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 98 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 99 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 100 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 101 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 102 #ifndef CONFIG_SPL_BUILD 103 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 104 #endif 105 #define CONFIG_SPL_SPI_BOOT 106 #endif 107 108 #ifdef CONFIG_SDCARD 109 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 110 #define CONFIG_SPL_MMC_SUPPORT 111 #define CONFIG_SPL_MMC_MINIMAL 112 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 113 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 114 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 115 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 116 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 117 #ifndef CONFIG_SPL_BUILD 118 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 119 #endif 120 #define CONFIG_SPL_MMC_BOOT 121 #endif 122 123 #endif /* CONFIG_RAMBOOT_PBL */ 124 125 #define CONFIG_SRIO_PCIE_BOOT_MASTER 126 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 127 /* Set 1M boot space */ 128 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 129 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 130 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 131 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 132 #define CONFIG_SYS_NO_FLASH 133 #endif 134 135 #ifndef CONFIG_SYS_TEXT_BASE 136 #define CONFIG_SYS_TEXT_BASE 0xeff40000 137 #endif 138 139 #ifndef CONFIG_RESET_VECTOR_ADDRESS 140 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 141 #endif 142 143 /* 144 * These can be toggled for performance analysis, otherwise use default. 145 */ 146 #define CONFIG_SYS_CACHE_STASHING 147 #define CONFIG_BTB /* toggle branch predition */ 148 #define CONFIG_DDR_ECC 149 #ifdef CONFIG_DDR_ECC 150 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 151 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 152 #endif 153 154 #ifndef CONFIG_SYS_NO_FLASH 155 #define CONFIG_FLASH_CFI_DRIVER 156 #define CONFIG_SYS_FLASH_CFI 157 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 158 #endif 159 160 #if defined(CONFIG_SPIFLASH) 161 #define CONFIG_SYS_EXTRA_ENV_RELOC 162 #define CONFIG_ENV_IS_IN_SPI_FLASH 163 #define CONFIG_ENV_SPI_BUS 0 164 #define CONFIG_ENV_SPI_CS 0 165 #define CONFIG_ENV_SPI_MAX_HZ 10000000 166 #define CONFIG_ENV_SPI_MODE 0 167 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 168 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 169 #define CONFIG_ENV_SECT_SIZE 0x10000 170 #elif defined(CONFIG_SDCARD) 171 #define CONFIG_SYS_EXTRA_ENV_RELOC 172 #define CONFIG_ENV_IS_IN_MMC 173 #define CONFIG_SYS_MMC_ENV_DEV 0 174 #define CONFIG_ENV_SIZE 0x2000 175 #define CONFIG_ENV_OFFSET (512 * 0x800) 176 #elif defined(CONFIG_NAND) 177 #define CONFIG_SYS_EXTRA_ENV_RELOC 178 #define CONFIG_ENV_IS_IN_NAND 179 #define CONFIG_ENV_SIZE 0x2000 180 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 181 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 182 #define CONFIG_ENV_IS_IN_REMOTE 183 #define CONFIG_ENV_ADDR 0xffe20000 184 #define CONFIG_ENV_SIZE 0x2000 185 #elif defined(CONFIG_ENV_IS_NOWHERE) 186 #define CONFIG_ENV_SIZE 0x2000 187 #else 188 #define CONFIG_ENV_IS_IN_FLASH 189 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 190 #define CONFIG_ENV_SIZE 0x2000 191 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 192 #endif 193 194 #ifndef __ASSEMBLY__ 195 unsigned long get_board_sys_clk(void); 196 unsigned long get_board_ddr_clk(void); 197 #endif 198 199 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 200 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 201 202 /* 203 * Config the L3 Cache as L3 SRAM 204 */ 205 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 206 #define CONFIG_SYS_L3_SIZE (512 << 10) 207 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 208 #ifdef CONFIG_RAMBOOT_PBL 209 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 210 #endif 211 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 212 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 213 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 214 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 215 216 #define CONFIG_SYS_DCSRBAR 0xf0000000 217 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 218 219 /* EEPROM */ 220 #define CONFIG_ID_EEPROM 221 #define CONFIG_SYS_I2C_EEPROM_NXID 222 #define CONFIG_SYS_EEPROM_BUS_NUM 0 223 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 224 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 225 226 /* 227 * DDR Setup 228 */ 229 #define CONFIG_VERY_BIG_RAM 230 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 231 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 232 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 233 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 234 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 235 #define CONFIG_DDR_SPD 236 #define CONFIG_SYS_FSL_DDR3 237 #define CONFIG_FSL_DDR_INTERACTIVE 238 #define CONFIG_SYS_SPD_BUS_NUM 0 239 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 240 #define SPD_EEPROM_ADDRESS1 0x51 241 #define SPD_EEPROM_ADDRESS2 0x52 242 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 243 #define CTRL_INTLV_PREFERED cacheline 244 245 /* 246 * IFC Definitions 247 */ 248 #define CONFIG_SYS_FLASH_BASE 0xe0000000 249 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 250 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 251 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 252 + 0x8000000) | \ 253 CSPR_PORT_SIZE_16 | \ 254 CSPR_MSEL_NOR | \ 255 CSPR_V) 256 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 257 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 258 CSPR_PORT_SIZE_16 | \ 259 CSPR_MSEL_NOR | \ 260 CSPR_V) 261 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 262 /* NOR Flash Timing Params */ 263 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 264 265 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 266 FTIM0_NOR_TEADC(0x5) | \ 267 FTIM0_NOR_TEAHC(0x5)) 268 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 269 FTIM1_NOR_TRAD_NOR(0x1A) |\ 270 FTIM1_NOR_TSEQRAD_NOR(0x13)) 271 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 272 FTIM2_NOR_TCH(0x4) | \ 273 FTIM2_NOR_TWPH(0x0E) | \ 274 FTIM2_NOR_TWP(0x1c)) 275 #define CONFIG_SYS_NOR_FTIM3 0x0 276 277 #define CONFIG_SYS_FLASH_QUIET_TEST 278 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 279 280 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 281 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 282 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 283 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 284 285 #define CONFIG_SYS_FLASH_EMPTY_INFO 286 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 287 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 288 289 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 290 #define QIXIS_BASE 0xffdf0000 291 #define QIXIS_LBMAP_SWITCH 6 292 #define QIXIS_LBMAP_MASK 0x0f 293 #define QIXIS_LBMAP_SHIFT 0 294 #define QIXIS_LBMAP_DFLTBANK 0x00 295 #define QIXIS_LBMAP_ALTBANK 0x04 296 #define QIXIS_RST_CTL_RESET 0x83 297 #define QIXIS_RST_FORCE_MEM 0x1 298 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 299 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 300 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 301 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 302 303 #define CONFIG_SYS_CSPR3_EXT (0xf) 304 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 305 | CSPR_PORT_SIZE_8 \ 306 | CSPR_MSEL_GPCM \ 307 | CSPR_V) 308 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 309 #define CONFIG_SYS_CSOR3 0x0 310 /* QIXIS Timing parameters for IFC CS3 */ 311 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 312 FTIM0_GPCM_TEADC(0x0e) | \ 313 FTIM0_GPCM_TEAHC(0x0e)) 314 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 315 FTIM1_GPCM_TRAD(0x3f)) 316 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 317 FTIM2_GPCM_TCH(0x8) | \ 318 FTIM2_GPCM_TWP(0x1f)) 319 #define CONFIG_SYS_CS3_FTIM3 0x0 320 321 /* NAND Flash on IFC */ 322 #define CONFIG_NAND_FSL_IFC 323 #define CONFIG_SYS_NAND_BASE 0xff800000 324 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 325 326 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 327 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 328 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 329 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 330 | CSPR_V) 331 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 332 333 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 334 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 335 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 336 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 337 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 338 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 339 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 340 341 #define CONFIG_SYS_NAND_ONFI_DETECTION 342 343 /* ONFI NAND Flash mode0 Timing Params */ 344 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 345 FTIM0_NAND_TWP(0x18) | \ 346 FTIM0_NAND_TWCHT(0x07) | \ 347 FTIM0_NAND_TWH(0x0a)) 348 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 349 FTIM1_NAND_TWBE(0x39) | \ 350 FTIM1_NAND_TRR(0x0e) | \ 351 FTIM1_NAND_TRP(0x18)) 352 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 353 FTIM2_NAND_TREH(0x0a) | \ 354 FTIM2_NAND_TWHRE(0x1e)) 355 #define CONFIG_SYS_NAND_FTIM3 0x0 356 357 #define CONFIG_SYS_NAND_DDR_LAW 11 358 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 359 #define CONFIG_SYS_MAX_NAND_DEVICE 1 360 #define CONFIG_CMD_NAND 361 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 362 363 #if defined(CONFIG_NAND) 364 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 365 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 366 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 367 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 368 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 369 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 370 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 371 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 372 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 373 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 374 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 375 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 376 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 377 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 378 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 379 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 380 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 381 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 382 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 383 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 384 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 385 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 386 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 387 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 388 #else 389 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 390 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 391 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 392 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 393 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 394 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 395 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 396 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 397 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 398 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 399 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 400 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 401 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 402 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 403 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 404 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 405 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 406 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 407 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 408 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 409 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 410 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 411 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 412 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 413 #endif 414 415 #if defined(CONFIG_RAMBOOT_PBL) 416 #define CONFIG_SYS_RAMBOOT 417 #endif 418 419 #ifdef CONFIG_SPL_BUILD 420 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 421 #else 422 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 423 #endif 424 425 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 426 #define CONFIG_MISC_INIT_R 427 #define CONFIG_HWCONFIG 428 429 /* define to use L1 as initial stack */ 430 #define CONFIG_L1_INIT_RAM 431 #define CONFIG_SYS_INIT_RAM_LOCK 432 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 433 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 434 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 435 /* The assembler doesn't like typecast */ 436 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 437 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 438 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 439 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 440 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 441 GENERATED_GBL_DATA_SIZE) 442 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 443 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 444 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 445 446 /* 447 * Serial Port 448 */ 449 #define CONFIG_CONS_INDEX 1 450 #define CONFIG_SYS_NS16550 451 #define CONFIG_SYS_NS16550_SERIAL 452 #define CONFIG_SYS_NS16550_REG_SIZE 1 453 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 454 #define CONFIG_SYS_BAUDRATE_TABLE \ 455 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 456 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 457 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 458 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 459 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 460 461 /* Use the HUSH parser */ 462 #define CONFIG_SYS_HUSH_PARSER 463 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 464 465 /* pass open firmware flat tree */ 466 #define CONFIG_OF_LIBFDT 467 #define CONFIG_OF_BOARD_SETUP 468 #define CONFIG_OF_STDOUT_VIA_ALIAS 469 470 /* new uImage format support */ 471 #define CONFIG_FIT 472 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 473 474 /* 475 * I2C 476 */ 477 #define CONFIG_SYS_I2C 478 #define CONFIG_SYS_I2C_FSL 479 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 480 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 481 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 482 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 483 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 484 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 485 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 486 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 487 #define CONFIG_SYS_FSL_I2C_SPEED 100000 488 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 489 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 490 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 491 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 492 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 493 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 494 #define I2C_MUX_CH_DEFAULT 0x8 495 496 #define I2C_MUX_CH_VOL_MONITOR 0xa 497 498 /* Voltage monitor on channel 2*/ 499 #define I2C_VOL_MONITOR_ADDR 0x40 500 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 501 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 502 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 503 504 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 505 #ifndef CONFIG_SPL_BUILD 506 #define CONFIG_VID 507 #endif 508 #define CONFIG_VOL_MONITOR_IR36021_SET 509 #define CONFIG_VOL_MONITOR_IR36021_READ 510 /* The lowest and highest voltage allowed for T208xQDS */ 511 #define VDD_MV_MIN 819 512 #define VDD_MV_MAX 1212 513 514 /* 515 * RapidIO 516 */ 517 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 518 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 519 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 520 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 521 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 522 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 523 /* 524 * for slave u-boot IMAGE instored in master memory space, 525 * PHYS must be aligned based on the SIZE 526 */ 527 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 528 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 529 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 530 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 531 /* 532 * for slave UCODE and ENV instored in master memory space, 533 * PHYS must be aligned based on the SIZE 534 */ 535 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 536 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 537 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 538 539 /* slave core release by master*/ 540 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 541 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 542 543 /* 544 * SRIO_PCIE_BOOT - SLAVE 545 */ 546 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 547 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 548 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 549 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 550 #endif 551 552 /* 553 * eSPI - Enhanced SPI 554 */ 555 #ifdef CONFIG_SPI_FLASH 556 #define CONFIG_FSL_ESPI 557 #define CONFIG_SPI_FLASH_STMICRO 558 #ifndef CONFIG_SPL_BUILD 559 #define CONFIG_SPI_FLASH_SST 560 #define CONFIG_SPI_FLASH_EON 561 #endif 562 563 #define CONFIG_CMD_SF 564 #define CONFIG_SPI_FLASH_BAR 565 #define CONFIG_SF_DEFAULT_SPEED 10000000 566 #define CONFIG_SF_DEFAULT_MODE 0 567 #endif 568 569 /* 570 * General PCI 571 * Memory space is mapped 1-1, but I/O space must start from 0. 572 */ 573 #define CONFIG_PCI /* Enable PCI/PCIE */ 574 #define CONFIG_PCIE1 /* PCIE controler 1 */ 575 #define CONFIG_PCIE2 /* PCIE controler 2 */ 576 #define CONFIG_PCIE3 /* PCIE controler 3 */ 577 #define CONFIG_PCIE4 /* PCIE controler 4 */ 578 #define CONFIG_FSL_PCIE_RESET 579 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 580 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 581 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 582 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 583 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 584 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 585 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 586 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 587 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 588 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 589 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 590 591 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 592 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 593 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 594 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 595 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 596 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 597 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 598 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 599 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 600 601 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 602 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 603 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 604 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 605 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 606 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 607 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 608 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 609 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 610 611 /* controller 4, Base address 203000 */ 612 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 613 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 614 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 615 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 616 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 617 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 618 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 619 620 #ifdef CONFIG_PCI 621 #define CONFIG_PCI_INDIRECT_BRIDGE 622 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 623 #define CONFIG_E1000 624 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 625 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 626 #define CONFIG_DOS_PARTITION 627 #endif 628 629 /* Qman/Bman */ 630 #ifndef CONFIG_NOBQFMAN 631 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 632 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 633 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 634 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 635 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 636 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 637 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 638 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 639 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 640 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 641 CONFIG_SYS_BMAN_CENA_SIZE) 642 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 643 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 644 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 645 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 646 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 647 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 648 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 649 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 650 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 651 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 652 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 653 CONFIG_SYS_QMAN_CENA_SIZE) 654 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 655 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 656 657 #define CONFIG_SYS_DPAA_FMAN 658 #define CONFIG_SYS_DPAA_PME 659 #define CONFIG_SYS_PMAN 660 #define CONFIG_SYS_DPAA_DCE 661 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 662 #define CONFIG_SYS_INTERLAKEN 663 664 /* Default address of microcode for the Linux Fman driver */ 665 #if defined(CONFIG_SPIFLASH) 666 /* 667 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 668 * env, so we got 0x110000. 669 */ 670 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 671 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 672 #elif defined(CONFIG_SDCARD) 673 /* 674 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 675 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 676 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 677 */ 678 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 679 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 680 #elif defined(CONFIG_NAND) 681 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 682 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 683 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 684 /* 685 * Slave has no ucode locally, it can fetch this from remote. When implementing 686 * in two corenet boards, slave's ucode could be stored in master's memory 687 * space, the address can be mapped from slave TLB->slave LAW-> 688 * slave SRIO or PCIE outbound window->master inbound window-> 689 * master LAW->the ucode address in master's memory space. 690 */ 691 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 692 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 693 #else 694 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 695 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 696 #endif 697 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 698 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 699 #endif /* CONFIG_NOBQFMAN */ 700 701 #ifdef CONFIG_SYS_DPAA_FMAN 702 #define CONFIG_FMAN_ENET 703 #define CONFIG_PHYLIB_10G 704 #define CONFIG_PHY_VITESSE 705 #define CONFIG_PHY_REALTEK 706 #define CONFIG_PHY_TERANETICS 707 #define RGMII_PHY1_ADDR 0x1 708 #define RGMII_PHY2_ADDR 0x2 709 #define FM1_10GEC1_PHY_ADDR 0x3 710 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 711 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 712 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 713 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 714 #endif 715 716 #ifdef CONFIG_FMAN_ENET 717 #define CONFIG_MII /* MII PHY management */ 718 #define CONFIG_ETHPRIME "FM1@DTSEC3" 719 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 720 #endif 721 722 /* 723 * SATA 724 */ 725 #ifdef CONFIG_FSL_SATA_V2 726 #define CONFIG_LIBATA 727 #define CONFIG_FSL_SATA 728 #define CONFIG_SYS_SATA_MAX_DEVICE 2 729 #define CONFIG_SATA1 730 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 731 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 732 #define CONFIG_SATA2 733 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 734 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 735 #define CONFIG_LBA48 736 #define CONFIG_CMD_SATA 737 #define CONFIG_DOS_PARTITION 738 #define CONFIG_CMD_EXT2 739 #endif 740 741 /* 742 * USB 743 */ 744 #ifdef CONFIG_USB_EHCI 745 #define CONFIG_CMD_USB 746 #define CONFIG_USB_STORAGE 747 #define CONFIG_USB_EHCI_FSL 748 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 749 #define CONFIG_CMD_EXT2 750 #define CONFIG_HAS_FSL_DR_USB 751 #endif 752 753 /* 754 * SDHC 755 */ 756 #ifdef CONFIG_MMC 757 #define CONFIG_CMD_MMC 758 #define CONFIG_FSL_ESDHC 759 #define define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 760 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 761 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 762 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 763 #define CONFIG_GENERIC_MMC 764 #define CONFIG_CMD_EXT2 765 #define CONFIG_CMD_FAT 766 #define CONFIG_DOS_PARTITION 767 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 768 #endif 769 770 771 /* 772 * Dynamic MTD Partition support with mtdparts 773 */ 774 #ifndef CONFIG_SYS_NO_FLASH 775 #define CONFIG_MTD_DEVICE 776 #define CONFIG_MTD_PARTITIONS 777 #define CONFIG_CMD_MTDPARTS 778 #define CONFIG_FLASH_CFI_MTD 779 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 780 "spi0=spife110000.0" 781 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 782 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 783 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 784 "1m(uboot),5m(kernel),128k(dtb),-(user)" 785 #endif 786 787 /* 788 * Environment 789 */ 790 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 791 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 792 793 /* 794 * Command line configuration. 795 */ 796 #include <config_cmd_default.h> 797 798 #define CONFIG_CMD_DHCP 799 #define CONFIG_CMD_ELF 800 #define CONFIG_CMD_ERRATA 801 #define CONFIG_CMD_GREPENV 802 #define CONFIG_CMD_IRQ 803 #define CONFIG_CMD_I2C 804 #define CONFIG_CMD_MII 805 #define CONFIG_CMD_PING 806 #define CONFIG_CMD_REGINFO 807 #define CONFIG_CMD_BDI 808 809 #ifdef CONFIG_PCI 810 #define CONFIG_CMD_PCI 811 #endif 812 813 /* Hash command with SHA acceleration supported in hardware */ 814 #ifdef CONFIG_FSL_CAAM 815 #define CONFIG_CMD_HASH 816 #define CONFIG_SHA_HW_ACCEL 817 #endif 818 819 /* 820 * Miscellaneous configurable options 821 */ 822 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 823 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 824 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 825 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 826 #ifdef CONFIG_CMD_KGDB 827 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 828 #else 829 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 830 #endif 831 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 832 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 833 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 834 835 /* 836 * For booting Linux, the board info and command line data 837 * have to be in the first 64 MB of memory, since this is 838 * the maximum mapped by the Linux kernel during initialization. 839 */ 840 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 841 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 842 843 #ifdef CONFIG_CMD_KGDB 844 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 845 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 846 #endif 847 848 /* 849 * Environment Configuration 850 */ 851 #define CONFIG_ROOTPATH "/opt/nfsroot" 852 #define CONFIG_BOOTFILE "uImage" 853 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 854 855 /* default location for tftp and bootm */ 856 #define CONFIG_LOADADDR 1000000 857 #define CONFIG_BAUDRATE 115200 858 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 859 #define __USB_PHY_TYPE utmi 860 861 #define CONFIG_EXTRA_ENV_SETTINGS \ 862 "hwconfig=fsl_ddr:" \ 863 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 864 "bank_intlv=auto;" \ 865 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 866 "netdev=eth0\0" \ 867 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 868 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 869 "tftpflash=tftpboot $loadaddr $uboot && " \ 870 "protect off $ubootaddr +$filesize && " \ 871 "erase $ubootaddr +$filesize && " \ 872 "cp.b $loadaddr $ubootaddr $filesize && " \ 873 "protect on $ubootaddr +$filesize && " \ 874 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 875 "consoledev=ttyS0\0" \ 876 "ramdiskaddr=2000000\0" \ 877 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 878 "fdtaddr=c00000\0" \ 879 "fdtfile=t2080qds/t2080qds.dtb\0" \ 880 "bdev=sda3\0" 881 882 /* 883 * For emulation this causes u-boot to jump to the start of the 884 * proof point app code automatically 885 */ 886 #define CONFIG_PROOF_POINTS \ 887 "setenv bootargs root=/dev/$bdev rw " \ 888 "console=$consoledev,$baudrate $othbootargs;" \ 889 "cpu 1 release 0x29000000 - - -;" \ 890 "cpu 2 release 0x29000000 - - -;" \ 891 "cpu 3 release 0x29000000 - - -;" \ 892 "cpu 4 release 0x29000000 - - -;" \ 893 "cpu 5 release 0x29000000 - - -;" \ 894 "cpu 6 release 0x29000000 - - -;" \ 895 "cpu 7 release 0x29000000 - - -;" \ 896 "go 0x29000000" 897 898 #define CONFIG_HVBOOT \ 899 "setenv bootargs config-addr=0x60000000; " \ 900 "bootm 0x01000000 - 0x00f00000" 901 902 #define CONFIG_ALU \ 903 "setenv bootargs root=/dev/$bdev rw " \ 904 "console=$consoledev,$baudrate $othbootargs;" \ 905 "cpu 1 release 0x01000000 - - -;" \ 906 "cpu 2 release 0x01000000 - - -;" \ 907 "cpu 3 release 0x01000000 - - -;" \ 908 "cpu 4 release 0x01000000 - - -;" \ 909 "cpu 5 release 0x01000000 - - -;" \ 910 "cpu 6 release 0x01000000 - - -;" \ 911 "cpu 7 release 0x01000000 - - -;" \ 912 "go 0x01000000" 913 914 #define CONFIG_LINUX \ 915 "setenv bootargs root=/dev/ram rw " \ 916 "console=$consoledev,$baudrate $othbootargs;" \ 917 "setenv ramdiskaddr 0x02000000;" \ 918 "setenv fdtaddr 0x00c00000;" \ 919 "setenv loadaddr 0x1000000;" \ 920 "bootm $loadaddr $ramdiskaddr $fdtaddr" 921 922 #define CONFIG_HDBOOT \ 923 "setenv bootargs root=/dev/$bdev rw " \ 924 "console=$consoledev,$baudrate $othbootargs;" \ 925 "tftp $loadaddr $bootfile;" \ 926 "tftp $fdtaddr $fdtfile;" \ 927 "bootm $loadaddr - $fdtaddr" 928 929 #define CONFIG_NFSBOOTCOMMAND \ 930 "setenv bootargs root=/dev/nfs rw " \ 931 "nfsroot=$serverip:$rootpath " \ 932 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 933 "console=$consoledev,$baudrate $othbootargs;" \ 934 "tftp $loadaddr $bootfile;" \ 935 "tftp $fdtaddr $fdtfile;" \ 936 "bootm $loadaddr - $fdtaddr" 937 938 #define CONFIG_RAMBOOTCOMMAND \ 939 "setenv bootargs root=/dev/ram rw " \ 940 "console=$consoledev,$baudrate $othbootargs;" \ 941 "tftp $ramdiskaddr $ramdiskfile;" \ 942 "tftp $loadaddr $bootfile;" \ 943 "tftp $fdtaddr $fdtfile;" \ 944 "bootm $loadaddr $ramdiskaddr $fdtaddr" 945 946 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 947 948 #ifdef CONFIG_SECURE_BOOT 949 #include <asm/fsl_secure_boot.h> 950 #define CONFIG_CMD_BLOB 951 #undef CONFIG_CMD_USB 952 #endif 953 954 #endif /* __T208xQDS_H */ 955