1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #include <asm/config_mpc85xx.h> 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 17 #ifndef CONFIG_SECURE_BOOT 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 19 #else 20 #define CONFIG_SYS_FSL_PBL_PBI \ 21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 22 #endif 23 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x30001000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_SKIP_RELOCATE 32 #define CONFIG_SPL_COMMON_INIT_DDR 33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 34 #define CONFIG_SYS_NO_FLASH 35 #endif 36 #define RESET_VECTOR_OFFSET 0x27FFC 37 #define BOOT_PAGE_OFFSET 0x27000 38 39 #ifdef CONFIG_NAND 40 #ifdef CONFIG_SECURE_BOOT 41 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 42 /* 43 * HDR would be appended at end of image and copied to DDR along 44 * with U-Boot image. 45 */ 46 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 47 CONFIG_U_BOOT_HDR_SIZE) 48 #else 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 50 #endif 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #ifdef CONFIG_TARGET_T1040RDB 56 #define CONFIG_SYS_FSL_PBL_RCW \ 57 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 58 #endif 59 #ifdef CONFIG_TARGET_T1042RDB_PI 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 62 #endif 63 #ifdef CONFIG_TARGET_T1042RDB 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 66 #endif 67 #ifdef CONFIG_TARGET_T1040D4RDB 68 #define CONFIG_SYS_FSL_PBL_RCW \ 69 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 70 #endif 71 #ifdef CONFIG_TARGET_T1042D4RDB 72 #define CONFIG_SYS_FSL_PBL_RCW \ 73 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 74 #endif 75 #define CONFIG_SPL_NAND_BOOT 76 #endif 77 78 #ifdef CONFIG_SPIFLASH 79 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 80 #define CONFIG_SPL_SPI_FLASH_MINIMAL 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #ifdef CONFIG_TARGET_T1040RDB 90 #define CONFIG_SYS_FSL_PBL_RCW \ 91 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 92 #endif 93 #ifdef CONFIG_TARGET_T1042RDB_PI 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_TARGET_T1042RDB 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 100 #endif 101 #ifdef CONFIG_TARGET_T1040D4RDB 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 104 #endif 105 #ifdef CONFIG_TARGET_T1042D4RDB 106 #define CONFIG_SYS_FSL_PBL_RCW \ 107 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 108 #endif 109 #define CONFIG_SPL_SPI_BOOT 110 #endif 111 112 #ifdef CONFIG_SDCARD 113 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 114 #define CONFIG_SPL_MMC_MINIMAL 115 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 116 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 117 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 118 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 119 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 120 #ifndef CONFIG_SPL_BUILD 121 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 122 #endif 123 #ifdef CONFIG_TARGET_T1040RDB 124 #define CONFIG_SYS_FSL_PBL_RCW \ 125 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 126 #endif 127 #ifdef CONFIG_TARGET_T1042RDB_PI 128 #define CONFIG_SYS_FSL_PBL_RCW \ 129 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 130 #endif 131 #ifdef CONFIG_TARGET_T1042RDB 132 #define CONFIG_SYS_FSL_PBL_RCW \ 133 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 134 #endif 135 #ifdef CONFIG_TARGET_T1040D4RDB 136 #define CONFIG_SYS_FSL_PBL_RCW \ 137 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 138 #endif 139 #ifdef CONFIG_TARGET_T1042D4RDB 140 #define CONFIG_SYS_FSL_PBL_RCW \ 141 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 142 #endif 143 #define CONFIG_SPL_MMC_BOOT 144 #endif 145 146 #endif 147 148 /* High Level Configuration Options */ 149 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 150 #define CONFIG_MP /* support multiple processors */ 151 152 /* support deep sleep */ 153 #define CONFIG_DEEP_SLEEP 154 #if defined(CONFIG_DEEP_SLEEP) 155 #define CONFIG_BOARD_EARLY_INIT_F 156 #endif 157 158 #ifndef CONFIG_SYS_TEXT_BASE 159 #define CONFIG_SYS_TEXT_BASE 0xeff40000 160 #endif 161 162 #ifndef CONFIG_RESET_VECTOR_ADDRESS 163 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 164 #endif 165 166 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 167 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 168 #define CONFIG_FSL_IFC /* Enable IFC Support */ 169 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 170 #define CONFIG_PCI_INDIRECT_BRIDGE 171 #define CONFIG_PCIE1 /* PCIE controller 1 */ 172 #define CONFIG_PCIE2 /* PCIE controller 2 */ 173 #define CONFIG_PCIE3 /* PCIE controller 3 */ 174 #define CONFIG_PCIE4 /* PCIE controller 4 */ 175 176 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 177 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 178 179 #define CONFIG_ENV_OVERWRITE 180 181 #ifndef CONFIG_SYS_NO_FLASH 182 #define CONFIG_FLASH_CFI_DRIVER 183 #define CONFIG_SYS_FLASH_CFI 184 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 185 #endif 186 187 #if defined(CONFIG_SPIFLASH) 188 #define CONFIG_SYS_EXTRA_ENV_RELOC 189 #define CONFIG_ENV_IS_IN_SPI_FLASH 190 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 191 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 192 #define CONFIG_ENV_SECT_SIZE 0x10000 193 #elif defined(CONFIG_SDCARD) 194 #define CONFIG_SYS_EXTRA_ENV_RELOC 195 #define CONFIG_ENV_IS_IN_MMC 196 #define CONFIG_SYS_MMC_ENV_DEV 0 197 #define CONFIG_ENV_SIZE 0x2000 198 #define CONFIG_ENV_OFFSET (512 * 0x800) 199 #elif defined(CONFIG_NAND) 200 #ifdef CONFIG_SECURE_BOOT 201 #define CONFIG_RAMBOOT_NAND 202 #define CONFIG_BOOTSCRIPT_COPY_RAM 203 #endif 204 #define CONFIG_SYS_EXTRA_ENV_RELOC 205 #define CONFIG_ENV_IS_IN_NAND 206 #define CONFIG_ENV_SIZE 0x2000 207 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 208 #else 209 #define CONFIG_ENV_IS_IN_FLASH 210 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 211 #define CONFIG_ENV_SIZE 0x2000 212 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 213 #endif 214 215 #define CONFIG_SYS_CLK_FREQ 100000000 216 #define CONFIG_DDR_CLK_FREQ 66666666 217 218 /* 219 * These can be toggled for performance analysis, otherwise use default. 220 */ 221 #define CONFIG_SYS_CACHE_STASHING 222 #define CONFIG_BACKSIDE_L2_CACHE 223 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 224 #define CONFIG_BTB /* toggle branch predition */ 225 #define CONFIG_DDR_ECC 226 #ifdef CONFIG_DDR_ECC 227 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 228 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 229 #endif 230 231 #define CONFIG_ENABLE_36BIT_PHYS 232 233 #define CONFIG_ADDR_MAP 234 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 235 236 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 237 #define CONFIG_SYS_MEMTEST_END 0x00400000 238 #define CONFIG_SYS_ALT_MEMTEST 239 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 240 241 /* 242 * Config the L3 Cache as L3 SRAM 243 */ 244 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 245 /* 246 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 247 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 248 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 249 */ 250 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 251 #define CONFIG_SYS_L3_SIZE 256 << 10 252 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 253 #ifdef CONFIG_RAMBOOT_PBL 254 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 255 #endif 256 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 257 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 258 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 259 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 260 261 #define CONFIG_SYS_DCSRBAR 0xf0000000 262 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 263 264 /* 265 * DDR Setup 266 */ 267 #define CONFIG_VERY_BIG_RAM 268 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 269 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 270 271 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 272 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 273 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 274 275 #define CONFIG_DDR_SPD 276 #ifndef CONFIG_SYS_FSL_DDR4 277 #define CONFIG_SYS_FSL_DDR3 278 #endif 279 280 #define CONFIG_SYS_SPD_BUS_NUM 0 281 #define SPD_EEPROM_ADDRESS 0x51 282 283 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 284 285 /* 286 * IFC Definitions 287 */ 288 #define CONFIG_SYS_FLASH_BASE 0xe8000000 289 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 290 291 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 292 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 293 CSPR_PORT_SIZE_16 | \ 294 CSPR_MSEL_NOR | \ 295 CSPR_V) 296 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 297 298 /* 299 * TDM Definition 300 */ 301 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 302 303 /* NOR Flash Timing Params */ 304 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 305 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 306 FTIM0_NOR_TEADC(0x5) | \ 307 FTIM0_NOR_TEAHC(0x5)) 308 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 309 FTIM1_NOR_TRAD_NOR(0x1A) |\ 310 FTIM1_NOR_TSEQRAD_NOR(0x13)) 311 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 312 FTIM2_NOR_TCH(0x4) | \ 313 FTIM2_NOR_TWPH(0x0E) | \ 314 FTIM2_NOR_TWP(0x1c)) 315 #define CONFIG_SYS_NOR_FTIM3 0x0 316 317 #define CONFIG_SYS_FLASH_QUIET_TEST 318 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 319 320 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 321 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 322 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 323 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 324 325 #define CONFIG_SYS_FLASH_EMPTY_INFO 326 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 327 328 /* CPLD on IFC */ 329 #define CPLD_LBMAP_MASK 0x3F 330 #define CPLD_BANK_SEL_MASK 0x07 331 #define CPLD_BANK_OVERRIDE 0x40 332 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 333 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 334 #define CPLD_LBMAP_RESET 0xFF 335 #define CPLD_LBMAP_SHIFT 0x03 336 337 #if defined(CONFIG_TARGET_T1042RDB_PI) 338 #define CPLD_DIU_SEL_DFP 0x80 339 #elif defined(CONFIG_TARGET_T1042D4RDB) 340 #define CPLD_DIU_SEL_DFP 0xc0 341 #endif 342 343 #if defined(CONFIG_TARGET_T1040D4RDB) 344 #define CPLD_INT_MASK_ALL 0xFF 345 #define CPLD_INT_MASK_THERM 0x80 346 #define CPLD_INT_MASK_DVI_DFP 0x40 347 #define CPLD_INT_MASK_QSGMII1 0x20 348 #define CPLD_INT_MASK_QSGMII2 0x10 349 #define CPLD_INT_MASK_SGMI1 0x08 350 #define CPLD_INT_MASK_SGMI2 0x04 351 #define CPLD_INT_MASK_TDMR1 0x02 352 #define CPLD_INT_MASK_TDMR2 0x01 353 #endif 354 355 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 356 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 357 #define CONFIG_SYS_CSPR2_EXT (0xf) 358 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 359 | CSPR_PORT_SIZE_8 \ 360 | CSPR_MSEL_GPCM \ 361 | CSPR_V) 362 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 363 #define CONFIG_SYS_CSOR2 0x0 364 /* CPLD Timing parameters for IFC CS2 */ 365 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 366 FTIM0_GPCM_TEADC(0x0e) | \ 367 FTIM0_GPCM_TEAHC(0x0e)) 368 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 369 FTIM1_GPCM_TRAD(0x1f)) 370 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 371 FTIM2_GPCM_TCH(0x8) | \ 372 FTIM2_GPCM_TWP(0x1f)) 373 #define CONFIG_SYS_CS2_FTIM3 0x0 374 375 /* NAND Flash on IFC */ 376 #define CONFIG_NAND_FSL_IFC 377 #define CONFIG_SYS_NAND_BASE 0xff800000 378 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 379 380 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 381 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 382 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 383 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 384 | CSPR_V) 385 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 386 387 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 388 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 389 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 390 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 391 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 392 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 393 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 394 395 #define CONFIG_SYS_NAND_ONFI_DETECTION 396 397 /* ONFI NAND Flash mode0 Timing Params */ 398 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 399 FTIM0_NAND_TWP(0x18) | \ 400 FTIM0_NAND_TWCHT(0x07) | \ 401 FTIM0_NAND_TWH(0x0a)) 402 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 403 FTIM1_NAND_TWBE(0x39) | \ 404 FTIM1_NAND_TRR(0x0e) | \ 405 FTIM1_NAND_TRP(0x18)) 406 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 407 FTIM2_NAND_TREH(0x0a) | \ 408 FTIM2_NAND_TWHRE(0x1e)) 409 #define CONFIG_SYS_NAND_FTIM3 0x0 410 411 #define CONFIG_SYS_NAND_DDR_LAW 11 412 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 413 #define CONFIG_SYS_MAX_NAND_DEVICE 1 414 #define CONFIG_CMD_NAND 415 416 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 417 418 #if defined(CONFIG_NAND) 419 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 420 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 421 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 422 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 423 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 424 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 425 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 426 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 427 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 428 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 429 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 430 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 431 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 432 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 433 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 434 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 435 #else 436 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 437 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 438 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 439 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 440 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 441 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 442 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 443 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 444 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 445 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 446 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 447 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 448 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 449 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 450 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 451 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 452 #endif 453 454 #ifdef CONFIG_SPL_BUILD 455 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 456 #else 457 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 458 #endif 459 460 #if defined(CONFIG_RAMBOOT_PBL) 461 #define CONFIG_SYS_RAMBOOT 462 #endif 463 464 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 465 #if defined(CONFIG_NAND) 466 #define CONFIG_A008044_WORKAROUND 467 #endif 468 #endif 469 470 #define CONFIG_BOARD_EARLY_INIT_R 471 #define CONFIG_MISC_INIT_R 472 473 #define CONFIG_HWCONFIG 474 475 /* define to use L1 as initial stack */ 476 #define CONFIG_L1_INIT_RAM 477 #define CONFIG_SYS_INIT_RAM_LOCK 478 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 480 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 481 /* The assembler doesn't like typecast */ 482 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 483 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 484 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 485 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 486 487 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 488 GENERATED_GBL_DATA_SIZE) 489 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 490 491 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 492 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 493 494 /* Serial Port - controlled on board with jumper J8 495 * open - index 2 496 * shorted - index 1 497 */ 498 #define CONFIG_CONS_INDEX 1 499 #define CONFIG_SYS_NS16550_SERIAL 500 #define CONFIG_SYS_NS16550_REG_SIZE 1 501 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 502 503 #define CONFIG_SYS_BAUDRATE_TABLE \ 504 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 505 506 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 507 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 508 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 509 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 510 511 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 512 /* Video */ 513 #define CONFIG_FSL_DIU_FB 514 515 #ifdef CONFIG_FSL_DIU_FB 516 #define CONFIG_FSL_DIU_CH7301 517 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 518 #define CONFIG_CMD_BMP 519 #define CONFIG_VIDEO_LOGO 520 #define CONFIG_VIDEO_BMP_LOGO 521 #endif 522 #endif 523 524 /* I2C */ 525 #define CONFIG_SYS_I2C 526 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 527 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 528 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 529 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 530 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 531 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 532 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 533 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 534 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 535 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 536 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 537 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 538 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 539 540 /* I2C bus multiplexer */ 541 #define I2C_MUX_PCA_ADDR 0x70 542 #define I2C_MUX_CH_DEFAULT 0x8 543 544 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 545 defined(CONFIG_TARGET_T1040D4RDB) || \ 546 defined(CONFIG_TARGET_T1042D4RDB) 547 /* LDI/DVI Encoder for display */ 548 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 549 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 550 551 /* 552 * RTC configuration 553 */ 554 #define RTC 555 #define CONFIG_RTC_DS1337 1 556 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 557 558 /*DVI encoder*/ 559 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 560 #endif 561 562 /* 563 * eSPI - Enhanced SPI 564 */ 565 #define CONFIG_SPI_FLASH_BAR 566 #define CONFIG_SF_DEFAULT_SPEED 10000000 567 #define CONFIG_SF_DEFAULT_MODE 0 568 #define CONFIG_ENV_SPI_BUS 0 569 #define CONFIG_ENV_SPI_CS 0 570 #define CONFIG_ENV_SPI_MAX_HZ 10000000 571 #define CONFIG_ENV_SPI_MODE 0 572 573 /* 574 * General PCI 575 * Memory space is mapped 1-1, but I/O space must start from 0. 576 */ 577 578 #ifdef CONFIG_PCI 579 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 580 #ifdef CONFIG_PCIE1 581 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 582 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 583 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 584 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 585 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 586 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 587 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 588 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 589 #endif 590 591 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 592 #ifdef CONFIG_PCIE2 593 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 594 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 595 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 596 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 597 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 598 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 599 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 600 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 601 #endif 602 603 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 604 #ifdef CONFIG_PCIE3 605 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 606 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 607 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 608 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 609 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 610 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 611 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 612 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 613 #endif 614 615 /* controller 4, Base address 203000 */ 616 #ifdef CONFIG_PCIE4 617 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 618 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 619 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 620 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 621 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 622 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 623 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 624 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 625 #endif 626 627 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 628 #define CONFIG_DOS_PARTITION 629 #endif /* CONFIG_PCI */ 630 631 /* SATA */ 632 #define CONFIG_FSL_SATA_V2 633 #ifdef CONFIG_FSL_SATA_V2 634 #define CONFIG_LIBATA 635 #define CONFIG_FSL_SATA 636 637 #define CONFIG_SYS_SATA_MAX_DEVICE 1 638 #define CONFIG_SATA1 639 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 640 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 641 642 #define CONFIG_LBA48 643 #define CONFIG_CMD_SATA 644 #define CONFIG_DOS_PARTITION 645 #endif 646 647 /* 648 * USB 649 */ 650 #define CONFIG_HAS_FSL_DR_USB 651 652 #ifdef CONFIG_HAS_FSL_DR_USB 653 #define CONFIG_USB_EHCI 654 655 #ifdef CONFIG_USB_EHCI 656 #define CONFIG_USB_EHCI_FSL 657 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 658 #endif 659 #endif 660 661 #ifdef CONFIG_MMC 662 #define CONFIG_FSL_ESDHC 663 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 664 #define CONFIG_GENERIC_MMC 665 #define CONFIG_DOS_PARTITION 666 #endif 667 668 /* Qman/Bman */ 669 #ifndef CONFIG_NOBQFMAN 670 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 671 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 672 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 673 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 674 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 675 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 676 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 677 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 678 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 679 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 680 CONFIG_SYS_BMAN_CENA_SIZE) 681 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 682 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 683 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 684 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 685 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 686 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 687 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 688 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 689 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 690 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 691 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 692 CONFIG_SYS_QMAN_CENA_SIZE) 693 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 694 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 695 696 #define CONFIG_SYS_DPAA_FMAN 697 #define CONFIG_SYS_DPAA_PME 698 699 #define CONFIG_QE 700 #define CONFIG_U_QE 701 702 /* Default address of microcode for the Linux Fman driver */ 703 #if defined(CONFIG_SPIFLASH) 704 /* 705 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 706 * env, so we got 0x110000. 707 */ 708 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 709 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 710 #elif defined(CONFIG_SDCARD) 711 /* 712 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 713 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 714 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 715 */ 716 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 717 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 718 #elif defined(CONFIG_NAND) 719 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 720 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 721 #else 722 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 723 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 724 #endif 725 726 #if defined(CONFIG_SPIFLASH) 727 #define CONFIG_SYS_QE_FW_ADDR 0x130000 728 #elif defined(CONFIG_SDCARD) 729 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 730 #elif defined(CONFIG_NAND) 731 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 732 #else 733 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 734 #endif 735 736 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 737 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 738 #endif /* CONFIG_NOBQFMAN */ 739 740 #ifdef CONFIG_SYS_DPAA_FMAN 741 #define CONFIG_FMAN_ENET 742 #define CONFIG_PHY_VITESSE 743 #define CONFIG_PHY_REALTEK 744 #endif 745 746 #ifdef CONFIG_FMAN_ENET 747 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 748 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 749 #elif defined(CONFIG_TARGET_T1040D4RDB) 750 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 751 #elif defined(CONFIG_TARGET_T1042D4RDB) 752 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 753 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 754 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 755 #endif 756 757 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 758 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 759 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 760 #else 761 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 762 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 763 #endif 764 765 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 766 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 767 #define CONFIG_VSC9953 768 #define CONFIG_CMD_ETHSW 769 #ifdef CONFIG_TARGET_T1040RDB 770 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 771 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 772 #else 773 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 774 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 775 #endif 776 #endif 777 778 #define CONFIG_MII /* MII PHY management */ 779 #define CONFIG_ETHPRIME "FM1@DTSEC4" 780 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 781 #endif 782 783 /* 784 * Environment 785 */ 786 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 787 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 788 789 /* 790 * Command line configuration. 791 */ 792 #ifdef CONFIG_TARGET_T1042RDB_PI 793 #define CONFIG_CMD_DATE 794 #endif 795 #define CONFIG_CMD_ERRATA 796 #define CONFIG_CMD_IRQ 797 #define CONFIG_CMD_REGINFO 798 799 #ifdef CONFIG_PCI 800 #define CONFIG_CMD_PCI 801 #endif 802 803 /* Hash command with SHA acceleration supported in hardware */ 804 #ifdef CONFIG_FSL_CAAM 805 #define CONFIG_CMD_HASH 806 #define CONFIG_SHA_HW_ACCEL 807 #endif 808 809 /* 810 * Miscellaneous configurable options 811 */ 812 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 813 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 814 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 815 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 816 #ifdef CONFIG_CMD_KGDB 817 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 818 #else 819 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 820 #endif 821 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 822 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 823 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 824 825 /* 826 * For booting Linux, the board info and command line data 827 * have to be in the first 64 MB of memory, since this is 828 * the maximum mapped by the Linux kernel during initialization. 829 */ 830 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 831 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 832 833 #ifdef CONFIG_CMD_KGDB 834 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 835 #endif 836 837 /* 838 * Dynamic MTD Partition support with mtdparts 839 */ 840 #ifndef CONFIG_SYS_NO_FLASH 841 #define CONFIG_MTD_DEVICE 842 #define CONFIG_MTD_PARTITIONS 843 #define CONFIG_CMD_MTDPARTS 844 #define CONFIG_FLASH_CFI_MTD 845 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 846 "spi0=spife110000.0" 847 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 848 "128k(dtb),96m(fs),-(user);"\ 849 "fff800000.flash:2m(uboot),9m(kernel),"\ 850 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 851 "2m(uboot),9m(kernel),128k(dtb),-(user)" 852 #endif 853 854 /* 855 * Environment Configuration 856 */ 857 #define CONFIG_ROOTPATH "/opt/nfsroot" 858 #define CONFIG_BOOTFILE "uImage" 859 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 860 861 /* default location for tftp and bootm */ 862 #define CONFIG_LOADADDR 1000000 863 864 865 #define CONFIG_BAUDRATE 115200 866 867 #define __USB_PHY_TYPE utmi 868 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 869 870 #ifdef CONFIG_TARGET_T1040RDB 871 #define FDTFILE "t1040rdb/t1040rdb.dtb" 872 #elif defined(CONFIG_TARGET_T1042RDB_PI) 873 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 874 #elif defined(CONFIG_TARGET_T1042RDB) 875 #define FDTFILE "t1042rdb/t1042rdb.dtb" 876 #elif defined(CONFIG_TARGET_T1040D4RDB) 877 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 878 #elif defined(CONFIG_TARGET_T1042D4RDB) 879 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 880 #endif 881 882 #ifdef CONFIG_FSL_DIU_FB 883 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 884 #else 885 #define DIU_ENVIRONMENT 886 #endif 887 888 #define CONFIG_EXTRA_ENV_SETTINGS \ 889 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 890 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 891 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 892 "netdev=eth0\0" \ 893 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 894 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 895 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 896 "tftpflash=tftpboot $loadaddr $uboot && " \ 897 "protect off $ubootaddr +$filesize && " \ 898 "erase $ubootaddr +$filesize && " \ 899 "cp.b $loadaddr $ubootaddr $filesize && " \ 900 "protect on $ubootaddr +$filesize && " \ 901 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 902 "consoledev=ttyS0\0" \ 903 "ramdiskaddr=2000000\0" \ 904 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 905 "fdtaddr=1e00000\0" \ 906 "fdtfile=" __stringify(FDTFILE) "\0" \ 907 "bdev=sda3\0" 908 909 #define CONFIG_LINUX \ 910 "setenv bootargs root=/dev/ram rw " \ 911 "console=$consoledev,$baudrate $othbootargs;" \ 912 "setenv ramdiskaddr 0x02000000;" \ 913 "setenv fdtaddr 0x00c00000;" \ 914 "setenv loadaddr 0x1000000;" \ 915 "bootm $loadaddr $ramdiskaddr $fdtaddr" 916 917 #define CONFIG_HDBOOT \ 918 "setenv bootargs root=/dev/$bdev rw " \ 919 "console=$consoledev,$baudrate $othbootargs;" \ 920 "tftp $loadaddr $bootfile;" \ 921 "tftp $fdtaddr $fdtfile;" \ 922 "bootm $loadaddr - $fdtaddr" 923 924 #define CONFIG_NFSBOOTCOMMAND \ 925 "setenv bootargs root=/dev/nfs rw " \ 926 "nfsroot=$serverip:$rootpath " \ 927 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 928 "console=$consoledev,$baudrate $othbootargs;" \ 929 "tftp $loadaddr $bootfile;" \ 930 "tftp $fdtaddr $fdtfile;" \ 931 "bootm $loadaddr - $fdtaddr" 932 933 #define CONFIG_RAMBOOTCOMMAND \ 934 "setenv bootargs root=/dev/ram rw " \ 935 "console=$consoledev,$baudrate $othbootargs;" \ 936 "tftp $ramdiskaddr $ramdiskfile;" \ 937 "tftp $loadaddr $bootfile;" \ 938 "tftp $fdtaddr $fdtfile;" \ 939 "bootm $loadaddr $ramdiskaddr $fdtaddr" 940 941 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 942 943 #include <asm/fsl_secure_boot.h> 944 945 #endif /* __CONFIG_H */ 946