1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 /* 10 * T104x RDB board configuration file 11 */ 12 #include <asm/config_mpc85xx.h> 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 16 #ifndef CONFIG_SECURE_BOOT 17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 18 #else 19 #define CONFIG_SYS_FSL_PBL_PBI \ 20 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 21 #endif 22 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 25 #define CONFIG_SPL_PAD_TO 0x40000 26 #define CONFIG_SPL_MAX_SIZE 0x28000 27 #ifdef CONFIG_SPL_BUILD 28 #define CONFIG_SPL_SKIP_RELOCATE 29 #define CONFIG_SPL_COMMON_INIT_DDR 30 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 31 #endif 32 #define RESET_VECTOR_OFFSET 0x27FFC 33 #define BOOT_PAGE_OFFSET 0x27000 34 35 #ifdef CONFIG_NAND 36 #ifdef CONFIG_SECURE_BOOT 37 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 38 /* 39 * HDR would be appended at end of image and copied to DDR along 40 * with U-Boot image. 41 */ 42 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 43 CONFIG_U_BOOT_HDR_SIZE) 44 #else 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 46 #endif 47 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 48 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 49 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 50 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 51 #ifdef CONFIG_TARGET_T1040RDB 52 #define CONFIG_SYS_FSL_PBL_RCW \ 53 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 54 #endif 55 #ifdef CONFIG_TARGET_T1042RDB_PI 56 #define CONFIG_SYS_FSL_PBL_RCW \ 57 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 58 #endif 59 #ifdef CONFIG_TARGET_T1042RDB 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 62 #endif 63 #ifdef CONFIG_TARGET_T1040D4RDB 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 66 #endif 67 #ifdef CONFIG_TARGET_T1042D4RDB 68 #define CONFIG_SYS_FSL_PBL_RCW \ 69 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 70 #endif 71 #define CONFIG_SPL_NAND_BOOT 72 #endif 73 74 #ifdef CONFIG_SPIFLASH 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 76 #define CONFIG_SPL_SPI_FLASH_MINIMAL 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 82 #ifndef CONFIG_SPL_BUILD 83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 84 #endif 85 #ifdef CONFIG_TARGET_T1040RDB 86 #define CONFIG_SYS_FSL_PBL_RCW \ 87 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 88 #endif 89 #ifdef CONFIG_TARGET_T1042RDB_PI 90 #define CONFIG_SYS_FSL_PBL_RCW \ 91 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 92 #endif 93 #ifdef CONFIG_TARGET_T1042RDB 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_TARGET_T1040D4RDB 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 100 #endif 101 #ifdef CONFIG_TARGET_T1042D4RDB 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 104 #endif 105 #define CONFIG_SPL_SPI_BOOT 106 #endif 107 108 #ifdef CONFIG_SDCARD 109 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 110 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 111 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 112 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 113 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 114 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 115 #ifndef CONFIG_SPL_BUILD 116 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 117 #endif 118 #ifdef CONFIG_TARGET_T1040RDB 119 #define CONFIG_SYS_FSL_PBL_RCW \ 120 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 121 #endif 122 #ifdef CONFIG_TARGET_T1042RDB_PI 123 #define CONFIG_SYS_FSL_PBL_RCW \ 124 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 125 #endif 126 #ifdef CONFIG_TARGET_T1042RDB 127 #define CONFIG_SYS_FSL_PBL_RCW \ 128 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 129 #endif 130 #ifdef CONFIG_TARGET_T1040D4RDB 131 #define CONFIG_SYS_FSL_PBL_RCW \ 132 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 133 #endif 134 #ifdef CONFIG_TARGET_T1042D4RDB 135 #define CONFIG_SYS_FSL_PBL_RCW \ 136 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 137 #endif 138 #define CONFIG_SPL_MMC_BOOT 139 #endif 140 141 #endif 142 143 /* High Level Configuration Options */ 144 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 145 146 /* support deep sleep */ 147 #define CONFIG_DEEP_SLEEP 148 149 #ifndef CONFIG_RESET_VECTOR_ADDRESS 150 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 151 #endif 152 153 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 154 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 155 #define CONFIG_PCI_INDIRECT_BRIDGE 156 #define CONFIG_PCIE1 /* PCIE controller 1 */ 157 #define CONFIG_PCIE2 /* PCIE controller 2 */ 158 #define CONFIG_PCIE3 /* PCIE controller 3 */ 159 #define CONFIG_PCIE4 /* PCIE controller 4 */ 160 161 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 162 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 163 164 #define CONFIG_ENV_OVERWRITE 165 166 #ifdef CONFIG_MTD_NOR_FLASH 167 #define CONFIG_FLASH_CFI_DRIVER 168 #define CONFIG_SYS_FLASH_CFI 169 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 170 #endif 171 172 #if defined(CONFIG_SPIFLASH) 173 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 174 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 175 #define CONFIG_ENV_SECT_SIZE 0x10000 176 #elif defined(CONFIG_SDCARD) 177 #define CONFIG_SYS_MMC_ENV_DEV 0 178 #define CONFIG_ENV_SIZE 0x2000 179 #define CONFIG_ENV_OFFSET (512 * 0x800) 180 #elif defined(CONFIG_NAND) 181 #ifdef CONFIG_SECURE_BOOT 182 #define CONFIG_RAMBOOT_NAND 183 #define CONFIG_BOOTSCRIPT_COPY_RAM 184 #endif 185 #define CONFIG_ENV_SIZE 0x2000 186 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 187 #else 188 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 189 #define CONFIG_ENV_SIZE 0x2000 190 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 191 #endif 192 193 #define CONFIG_SYS_CLK_FREQ 100000000 194 #define CONFIG_DDR_CLK_FREQ 66666666 195 196 /* 197 * These can be toggled for performance analysis, otherwise use default. 198 */ 199 #define CONFIG_SYS_CACHE_STASHING 200 #define CONFIG_BACKSIDE_L2_CACHE 201 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 202 #define CONFIG_BTB /* toggle branch predition */ 203 #define CONFIG_DDR_ECC 204 #ifdef CONFIG_DDR_ECC 205 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 206 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 207 #endif 208 209 #define CONFIG_ENABLE_36BIT_PHYS 210 211 #define CONFIG_ADDR_MAP 212 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 213 214 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 215 #define CONFIG_SYS_MEMTEST_END 0x00400000 216 217 /* 218 * Config the L3 Cache as L3 SRAM 219 */ 220 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 221 /* 222 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 223 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 224 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 225 */ 226 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 227 #define CONFIG_SYS_L3_SIZE 256 << 10 228 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 229 #ifdef CONFIG_RAMBOOT_PBL 230 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 231 #endif 232 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 233 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 234 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 235 236 #define CONFIG_SYS_DCSRBAR 0xf0000000 237 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 238 239 /* 240 * DDR Setup 241 */ 242 #define CONFIG_VERY_BIG_RAM 243 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 244 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 245 246 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 247 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 248 249 #define CONFIG_DDR_SPD 250 251 #define CONFIG_SYS_SPD_BUS_NUM 0 252 #define SPD_EEPROM_ADDRESS 0x51 253 254 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 255 256 /* 257 * IFC Definitions 258 */ 259 #define CONFIG_SYS_FLASH_BASE 0xe8000000 260 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 261 262 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 263 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 264 CSPR_PORT_SIZE_16 | \ 265 CSPR_MSEL_NOR | \ 266 CSPR_V) 267 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 268 269 /* 270 * TDM Definition 271 */ 272 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 273 274 /* NOR Flash Timing Params */ 275 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 276 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 277 FTIM0_NOR_TEADC(0x5) | \ 278 FTIM0_NOR_TEAHC(0x5)) 279 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 280 FTIM1_NOR_TRAD_NOR(0x1A) |\ 281 FTIM1_NOR_TSEQRAD_NOR(0x13)) 282 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 283 FTIM2_NOR_TCH(0x4) | \ 284 FTIM2_NOR_TWPH(0x0E) | \ 285 FTIM2_NOR_TWP(0x1c)) 286 #define CONFIG_SYS_NOR_FTIM3 0x0 287 288 #define CONFIG_SYS_FLASH_QUIET_TEST 289 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 290 291 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 292 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 293 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 294 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 295 296 #define CONFIG_SYS_FLASH_EMPTY_INFO 297 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 298 299 /* CPLD on IFC */ 300 #define CPLD_LBMAP_MASK 0x3F 301 #define CPLD_BANK_SEL_MASK 0x07 302 #define CPLD_BANK_OVERRIDE 0x40 303 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 304 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 305 #define CPLD_LBMAP_RESET 0xFF 306 #define CPLD_LBMAP_SHIFT 0x03 307 308 #if defined(CONFIG_TARGET_T1042RDB_PI) 309 #define CPLD_DIU_SEL_DFP 0x80 310 #elif defined(CONFIG_TARGET_T1042D4RDB) 311 #define CPLD_DIU_SEL_DFP 0xc0 312 #endif 313 314 #if defined(CONFIG_TARGET_T1040D4RDB) 315 #define CPLD_INT_MASK_ALL 0xFF 316 #define CPLD_INT_MASK_THERM 0x80 317 #define CPLD_INT_MASK_DVI_DFP 0x40 318 #define CPLD_INT_MASK_QSGMII1 0x20 319 #define CPLD_INT_MASK_QSGMII2 0x10 320 #define CPLD_INT_MASK_SGMI1 0x08 321 #define CPLD_INT_MASK_SGMI2 0x04 322 #define CPLD_INT_MASK_TDMR1 0x02 323 #define CPLD_INT_MASK_TDMR2 0x01 324 #endif 325 326 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 327 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 328 #define CONFIG_SYS_CSPR2_EXT (0xf) 329 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 330 | CSPR_PORT_SIZE_8 \ 331 | CSPR_MSEL_GPCM \ 332 | CSPR_V) 333 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 334 #define CONFIG_SYS_CSOR2 0x0 335 /* CPLD Timing parameters for IFC CS2 */ 336 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 337 FTIM0_GPCM_TEADC(0x0e) | \ 338 FTIM0_GPCM_TEAHC(0x0e)) 339 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 340 FTIM1_GPCM_TRAD(0x1f)) 341 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 342 FTIM2_GPCM_TCH(0x8) | \ 343 FTIM2_GPCM_TWP(0x1f)) 344 #define CONFIG_SYS_CS2_FTIM3 0x0 345 346 /* NAND Flash on IFC */ 347 #define CONFIG_NAND_FSL_IFC 348 #define CONFIG_SYS_NAND_BASE 0xff800000 349 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 350 351 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 352 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 353 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 354 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 355 | CSPR_V) 356 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 357 358 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 359 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 360 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 361 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 362 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 363 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 364 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 365 366 #define CONFIG_SYS_NAND_ONFI_DETECTION 367 368 /* ONFI NAND Flash mode0 Timing Params */ 369 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 370 FTIM0_NAND_TWP(0x18) | \ 371 FTIM0_NAND_TWCHT(0x07) | \ 372 FTIM0_NAND_TWH(0x0a)) 373 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 374 FTIM1_NAND_TWBE(0x39) | \ 375 FTIM1_NAND_TRR(0x0e) | \ 376 FTIM1_NAND_TRP(0x18)) 377 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 378 FTIM2_NAND_TREH(0x0a) | \ 379 FTIM2_NAND_TWHRE(0x1e)) 380 #define CONFIG_SYS_NAND_FTIM3 0x0 381 382 #define CONFIG_SYS_NAND_DDR_LAW 11 383 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 384 #define CONFIG_SYS_MAX_NAND_DEVICE 1 385 386 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 387 388 #if defined(CONFIG_NAND) 389 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 390 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 391 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 392 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 393 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 394 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 395 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 396 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 397 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 398 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 399 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 400 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 401 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 402 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 403 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 404 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 405 #else 406 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 407 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 408 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 409 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 410 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 411 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 412 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 413 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 414 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 415 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 416 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 417 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 418 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 419 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 420 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 421 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 422 #endif 423 424 #ifdef CONFIG_SPL_BUILD 425 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 426 #else 427 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 428 #endif 429 430 #if defined(CONFIG_RAMBOOT_PBL) 431 #define CONFIG_SYS_RAMBOOT 432 #endif 433 434 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 435 #if defined(CONFIG_NAND) 436 #define CONFIG_A008044_WORKAROUND 437 #endif 438 #endif 439 440 #define CONFIG_HWCONFIG 441 442 /* define to use L1 as initial stack */ 443 #define CONFIG_L1_INIT_RAM 444 #define CONFIG_SYS_INIT_RAM_LOCK 445 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 448 /* The assembler doesn't like typecast */ 449 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 450 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 451 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 452 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 453 454 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 455 GENERATED_GBL_DATA_SIZE) 456 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 457 458 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 459 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 460 461 /* Serial Port - controlled on board with jumper J8 462 * open - index 2 463 * shorted - index 1 464 */ 465 #define CONFIG_SYS_NS16550_SERIAL 466 #define CONFIG_SYS_NS16550_REG_SIZE 1 467 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 468 469 #define CONFIG_SYS_BAUDRATE_TABLE \ 470 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 471 472 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 473 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 474 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 475 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 476 477 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 478 /* Video */ 479 #define CONFIG_FSL_DIU_FB 480 481 #ifdef CONFIG_FSL_DIU_FB 482 #define CONFIG_FSL_DIU_CH7301 483 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 484 #define CONFIG_VIDEO_LOGO 485 #define CONFIG_VIDEO_BMP_LOGO 486 #endif 487 #endif 488 489 /* I2C */ 490 #define CONFIG_SYS_I2C 491 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 492 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 493 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 494 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 495 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 496 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 497 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 498 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 499 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 500 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 501 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 502 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 503 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 504 505 /* I2C bus multiplexer */ 506 #define I2C_MUX_PCA_ADDR 0x70 507 #define I2C_MUX_CH_DEFAULT 0x8 508 509 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 510 defined(CONFIG_TARGET_T1040D4RDB) || \ 511 defined(CONFIG_TARGET_T1042D4RDB) 512 /* LDI/DVI Encoder for display */ 513 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 514 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 515 516 /* 517 * RTC configuration 518 */ 519 #define RTC 520 #define CONFIG_RTC_DS1337 1 521 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 522 523 /*DVI encoder*/ 524 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 525 #endif 526 527 /* 528 * eSPI - Enhanced SPI 529 */ 530 #define CONFIG_SPI_FLASH_BAR 531 #define CONFIG_SF_DEFAULT_SPEED 10000000 532 #define CONFIG_SF_DEFAULT_MODE 0 533 #define CONFIG_ENV_SPI_BUS 0 534 #define CONFIG_ENV_SPI_CS 0 535 #define CONFIG_ENV_SPI_MAX_HZ 10000000 536 #define CONFIG_ENV_SPI_MODE 0 537 538 /* 539 * General PCI 540 * Memory space is mapped 1-1, but I/O space must start from 0. 541 */ 542 543 #ifdef CONFIG_PCI 544 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 545 #ifdef CONFIG_PCIE1 546 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 547 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 548 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 549 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 550 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 551 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 552 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 553 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 554 #endif 555 556 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 557 #ifdef CONFIG_PCIE2 558 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 559 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 560 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 561 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 562 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 563 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 564 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 565 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 566 #endif 567 568 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 569 #ifdef CONFIG_PCIE3 570 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 571 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 572 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 573 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 574 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 575 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 576 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 577 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 578 #endif 579 580 /* controller 4, Base address 203000 */ 581 #ifdef CONFIG_PCIE4 582 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 583 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 584 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 585 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 586 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 587 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 588 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 589 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 590 #endif 591 592 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 593 #endif /* CONFIG_PCI */ 594 595 /* SATA */ 596 #define CONFIG_FSL_SATA_V2 597 #ifdef CONFIG_FSL_SATA_V2 598 #define CONFIG_SYS_SATA_MAX_DEVICE 1 599 #define CONFIG_SATA1 600 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 601 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 602 603 #define CONFIG_LBA48 604 #endif 605 606 /* 607 * USB 608 */ 609 #define CONFIG_HAS_FSL_DR_USB 610 611 #ifdef CONFIG_HAS_FSL_DR_USB 612 #ifdef CONFIG_USB_EHCI_HCD 613 #define CONFIG_USB_EHCI_FSL 614 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 615 #endif 616 #endif 617 618 #ifdef CONFIG_MMC 619 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 620 #endif 621 622 /* Qman/Bman */ 623 #ifndef CONFIG_NOBQFMAN 624 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 625 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 626 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 627 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 628 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 629 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 630 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 631 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 632 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 633 CONFIG_SYS_BMAN_CENA_SIZE) 634 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 635 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 636 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 637 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 638 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 639 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 640 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 641 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 642 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 643 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 644 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 645 CONFIG_SYS_QMAN_CENA_SIZE) 646 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 647 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 648 649 #define CONFIG_SYS_DPAA_FMAN 650 #define CONFIG_SYS_DPAA_PME 651 652 #define CONFIG_QE 653 #define CONFIG_U_QE 654 655 /* Default address of microcode for the Linux Fman driver */ 656 #if defined(CONFIG_SPIFLASH) 657 /* 658 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 659 * env, so we got 0x110000. 660 */ 661 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 662 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 663 #elif defined(CONFIG_SDCARD) 664 /* 665 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 666 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 667 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 668 */ 669 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 670 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 671 #elif defined(CONFIG_NAND) 672 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 673 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 674 #else 675 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 676 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 677 #endif 678 679 #if defined(CONFIG_SPIFLASH) 680 #define CONFIG_SYS_QE_FW_ADDR 0x130000 681 #elif defined(CONFIG_SDCARD) 682 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 683 #elif defined(CONFIG_NAND) 684 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 685 #else 686 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 687 #endif 688 689 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 690 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 691 #endif /* CONFIG_NOBQFMAN */ 692 693 #ifdef CONFIG_SYS_DPAA_FMAN 694 #define CONFIG_FMAN_ENET 695 #define CONFIG_PHY_VITESSE 696 #define CONFIG_PHY_REALTEK 697 #endif 698 699 #ifdef CONFIG_FMAN_ENET 700 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 701 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 702 #elif defined(CONFIG_TARGET_T1040D4RDB) 703 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 704 #elif defined(CONFIG_TARGET_T1042D4RDB) 705 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 706 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 707 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 708 #endif 709 710 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 711 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 712 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 713 #else 714 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 715 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 716 #endif 717 718 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 719 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 720 #define CONFIG_VSC9953 721 #ifdef CONFIG_TARGET_T1040RDB 722 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 723 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 724 #else 725 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 726 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 727 #endif 728 #endif 729 730 #define CONFIG_ETHPRIME "FM1@DTSEC4" 731 #endif 732 733 /* 734 * Environment 735 */ 736 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 737 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 738 739 /* 740 * Miscellaneous configurable options 741 */ 742 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 743 744 /* 745 * For booting Linux, the board info and command line data 746 * have to be in the first 64 MB of memory, since this is 747 * the maximum mapped by the Linux kernel during initialization. 748 */ 749 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 750 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 751 752 #ifdef CONFIG_CMD_KGDB 753 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 754 #endif 755 756 /* 757 * Dynamic MTD Partition support with mtdparts 758 */ 759 #ifdef CONFIG_MTD_NOR_FLASH 760 #define CONFIG_FLASH_CFI_MTD 761 #endif 762 763 /* 764 * Environment Configuration 765 */ 766 #define CONFIG_ROOTPATH "/opt/nfsroot" 767 #define CONFIG_BOOTFILE "uImage" 768 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 769 770 /* default location for tftp and bootm */ 771 #define CONFIG_LOADADDR 1000000 772 773 #define __USB_PHY_TYPE utmi 774 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 775 776 #ifdef CONFIG_TARGET_T1040RDB 777 #define FDTFILE "t1040rdb/t1040rdb.dtb" 778 #elif defined(CONFIG_TARGET_T1042RDB_PI) 779 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 780 #elif defined(CONFIG_TARGET_T1042RDB) 781 #define FDTFILE "t1042rdb/t1042rdb.dtb" 782 #elif defined(CONFIG_TARGET_T1040D4RDB) 783 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 784 #elif defined(CONFIG_TARGET_T1042D4RDB) 785 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 786 #endif 787 788 #ifdef CONFIG_FSL_DIU_FB 789 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 790 #else 791 #define DIU_ENVIRONMENT 792 #endif 793 794 #define CONFIG_EXTRA_ENV_SETTINGS \ 795 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 796 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 797 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 798 "netdev=eth0\0" \ 799 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 800 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 801 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 802 "tftpflash=tftpboot $loadaddr $uboot && " \ 803 "protect off $ubootaddr +$filesize && " \ 804 "erase $ubootaddr +$filesize && " \ 805 "cp.b $loadaddr $ubootaddr $filesize && " \ 806 "protect on $ubootaddr +$filesize && " \ 807 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 808 "consoledev=ttyS0\0" \ 809 "ramdiskaddr=2000000\0" \ 810 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 811 "fdtaddr=1e00000\0" \ 812 "fdtfile=" __stringify(FDTFILE) "\0" \ 813 "bdev=sda3\0" 814 815 #define CONFIG_LINUX \ 816 "setenv bootargs root=/dev/ram rw " \ 817 "console=$consoledev,$baudrate $othbootargs;" \ 818 "setenv ramdiskaddr 0x02000000;" \ 819 "setenv fdtaddr 0x00c00000;" \ 820 "setenv loadaddr 0x1000000;" \ 821 "bootm $loadaddr $ramdiskaddr $fdtaddr" 822 823 #define CONFIG_HDBOOT \ 824 "setenv bootargs root=/dev/$bdev rw " \ 825 "console=$consoledev,$baudrate $othbootargs;" \ 826 "tftp $loadaddr $bootfile;" \ 827 "tftp $fdtaddr $fdtfile;" \ 828 "bootm $loadaddr - $fdtaddr" 829 830 #define CONFIG_NFSBOOTCOMMAND \ 831 "setenv bootargs root=/dev/nfs rw " \ 832 "nfsroot=$serverip:$rootpath " \ 833 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 834 "console=$consoledev,$baudrate $othbootargs;" \ 835 "tftp $loadaddr $bootfile;" \ 836 "tftp $fdtaddr $fdtfile;" \ 837 "bootm $loadaddr - $fdtaddr" 838 839 #define CONFIG_RAMBOOTCOMMAND \ 840 "setenv bootargs root=/dev/ram rw " \ 841 "console=$consoledev,$baudrate $othbootargs;" \ 842 "tftp $ramdiskaddr $ramdiskfile;" \ 843 "tftp $loadaddr $bootfile;" \ 844 "tftp $fdtaddr $fdtfile;" \ 845 "bootm $loadaddr $ramdiskaddr $fdtaddr" 846 847 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 848 849 #include <asm/fsl_secure_boot.h> 850 851 #endif /* __CONFIG_H */ 852