1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #include <asm/config_mpc85xx.h> 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 17 #ifndef CONFIG_SECURE_BOOT 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 19 #else 20 #define CONFIG_SYS_FSL_PBL_PBI \ 21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 22 #endif 23 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x30001000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_SKIP_RELOCATE 32 #define CONFIG_SPL_COMMON_INIT_DDR 33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 34 #endif 35 #define RESET_VECTOR_OFFSET 0x27FFC 36 #define BOOT_PAGE_OFFSET 0x27000 37 38 #ifdef CONFIG_NAND 39 #ifdef CONFIG_SECURE_BOOT 40 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 41 /* 42 * HDR would be appended at end of image and copied to DDR along 43 * with U-Boot image. 44 */ 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 46 CONFIG_U_BOOT_HDR_SIZE) 47 #else 48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 49 #endif 50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #ifdef CONFIG_TARGET_T1040RDB 55 #define CONFIG_SYS_FSL_PBL_RCW \ 56 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 57 #endif 58 #ifdef CONFIG_TARGET_T1042RDB_PI 59 #define CONFIG_SYS_FSL_PBL_RCW \ 60 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 61 #endif 62 #ifdef CONFIG_TARGET_T1042RDB 63 #define CONFIG_SYS_FSL_PBL_RCW \ 64 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 65 #endif 66 #ifdef CONFIG_TARGET_T1040D4RDB 67 #define CONFIG_SYS_FSL_PBL_RCW \ 68 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 69 #endif 70 #ifdef CONFIG_TARGET_T1042D4RDB 71 #define CONFIG_SYS_FSL_PBL_RCW \ 72 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 73 #endif 74 #define CONFIG_SPL_NAND_BOOT 75 #endif 76 77 #ifdef CONFIG_SPIFLASH 78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 79 #define CONFIG_SPL_SPI_FLASH_MINIMAL 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 85 #ifndef CONFIG_SPL_BUILD 86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 87 #endif 88 #ifdef CONFIG_TARGET_T1040RDB 89 #define CONFIG_SYS_FSL_PBL_RCW \ 90 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 91 #endif 92 #ifdef CONFIG_TARGET_T1042RDB_PI 93 #define CONFIG_SYS_FSL_PBL_RCW \ 94 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 95 #endif 96 #ifdef CONFIG_TARGET_T1042RDB 97 #define CONFIG_SYS_FSL_PBL_RCW \ 98 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 99 #endif 100 #ifdef CONFIG_TARGET_T1040D4RDB 101 #define CONFIG_SYS_FSL_PBL_RCW \ 102 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 103 #endif 104 #ifdef CONFIG_TARGET_T1042D4RDB 105 #define CONFIG_SYS_FSL_PBL_RCW \ 106 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 107 #endif 108 #define CONFIG_SPL_SPI_BOOT 109 #endif 110 111 #ifdef CONFIG_SDCARD 112 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 113 #define CONFIG_SPL_MMC_MINIMAL 114 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 115 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 116 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 117 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 118 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 119 #ifndef CONFIG_SPL_BUILD 120 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 121 #endif 122 #ifdef CONFIG_TARGET_T1040RDB 123 #define CONFIG_SYS_FSL_PBL_RCW \ 124 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 125 #endif 126 #ifdef CONFIG_TARGET_T1042RDB_PI 127 #define CONFIG_SYS_FSL_PBL_RCW \ 128 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 129 #endif 130 #ifdef CONFIG_TARGET_T1042RDB 131 #define CONFIG_SYS_FSL_PBL_RCW \ 132 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 133 #endif 134 #ifdef CONFIG_TARGET_T1040D4RDB 135 #define CONFIG_SYS_FSL_PBL_RCW \ 136 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 137 #endif 138 #ifdef CONFIG_TARGET_T1042D4RDB 139 #define CONFIG_SYS_FSL_PBL_RCW \ 140 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 141 #endif 142 #define CONFIG_SPL_MMC_BOOT 143 #endif 144 145 #endif 146 147 /* High Level Configuration Options */ 148 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 149 #define CONFIG_MP /* support multiple processors */ 150 151 /* support deep sleep */ 152 #define CONFIG_DEEP_SLEEP 153 154 #ifndef CONFIG_SYS_TEXT_BASE 155 #define CONFIG_SYS_TEXT_BASE 0xeff40000 156 #endif 157 158 #ifndef CONFIG_RESET_VECTOR_ADDRESS 159 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 160 #endif 161 162 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 163 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 164 #define CONFIG_PCI_INDIRECT_BRIDGE 165 #define CONFIG_PCIE1 /* PCIE controller 1 */ 166 #define CONFIG_PCIE2 /* PCIE controller 2 */ 167 #define CONFIG_PCIE3 /* PCIE controller 3 */ 168 #define CONFIG_PCIE4 /* PCIE controller 4 */ 169 170 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 171 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 172 173 #define CONFIG_ENV_OVERWRITE 174 175 #ifdef CONFIG_MTD_NOR_FLASH 176 #define CONFIG_FLASH_CFI_DRIVER 177 #define CONFIG_SYS_FLASH_CFI 178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 179 #endif 180 181 #if defined(CONFIG_SPIFLASH) 182 #define CONFIG_SYS_EXTRA_ENV_RELOC 183 #define CONFIG_ENV_IS_IN_SPI_FLASH 184 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 185 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 186 #define CONFIG_ENV_SECT_SIZE 0x10000 187 #elif defined(CONFIG_SDCARD) 188 #define CONFIG_SYS_EXTRA_ENV_RELOC 189 #define CONFIG_ENV_IS_IN_MMC 190 #define CONFIG_SYS_MMC_ENV_DEV 0 191 #define CONFIG_ENV_SIZE 0x2000 192 #define CONFIG_ENV_OFFSET (512 * 0x800) 193 #elif defined(CONFIG_NAND) 194 #ifdef CONFIG_SECURE_BOOT 195 #define CONFIG_RAMBOOT_NAND 196 #define CONFIG_BOOTSCRIPT_COPY_RAM 197 #endif 198 #define CONFIG_SYS_EXTRA_ENV_RELOC 199 #define CONFIG_ENV_IS_IN_NAND 200 #define CONFIG_ENV_SIZE 0x2000 201 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 202 #else 203 #define CONFIG_ENV_IS_IN_FLASH 204 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 205 #define CONFIG_ENV_SIZE 0x2000 206 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 207 #endif 208 209 #define CONFIG_SYS_CLK_FREQ 100000000 210 #define CONFIG_DDR_CLK_FREQ 66666666 211 212 /* 213 * These can be toggled for performance analysis, otherwise use default. 214 */ 215 #define CONFIG_SYS_CACHE_STASHING 216 #define CONFIG_BACKSIDE_L2_CACHE 217 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 218 #define CONFIG_BTB /* toggle branch predition */ 219 #define CONFIG_DDR_ECC 220 #ifdef CONFIG_DDR_ECC 221 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 222 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 223 #endif 224 225 #define CONFIG_ENABLE_36BIT_PHYS 226 227 #define CONFIG_ADDR_MAP 228 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 229 230 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 231 #define CONFIG_SYS_MEMTEST_END 0x00400000 232 #define CONFIG_SYS_ALT_MEMTEST 233 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 234 235 /* 236 * Config the L3 Cache as L3 SRAM 237 */ 238 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 239 /* 240 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 241 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 242 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 243 */ 244 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 245 #define CONFIG_SYS_L3_SIZE 256 << 10 246 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 247 #ifdef CONFIG_RAMBOOT_PBL 248 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 249 #endif 250 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 251 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 252 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 253 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 254 255 #define CONFIG_SYS_DCSRBAR 0xf0000000 256 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 257 258 /* 259 * DDR Setup 260 */ 261 #define CONFIG_VERY_BIG_RAM 262 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 263 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 264 265 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 266 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 267 268 #define CONFIG_DDR_SPD 269 270 #define CONFIG_SYS_SPD_BUS_NUM 0 271 #define SPD_EEPROM_ADDRESS 0x51 272 273 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 274 275 /* 276 * IFC Definitions 277 */ 278 #define CONFIG_SYS_FLASH_BASE 0xe8000000 279 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 280 281 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 282 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 283 CSPR_PORT_SIZE_16 | \ 284 CSPR_MSEL_NOR | \ 285 CSPR_V) 286 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 287 288 /* 289 * TDM Definition 290 */ 291 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 292 293 /* NOR Flash Timing Params */ 294 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 295 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 296 FTIM0_NOR_TEADC(0x5) | \ 297 FTIM0_NOR_TEAHC(0x5)) 298 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 299 FTIM1_NOR_TRAD_NOR(0x1A) |\ 300 FTIM1_NOR_TSEQRAD_NOR(0x13)) 301 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 302 FTIM2_NOR_TCH(0x4) | \ 303 FTIM2_NOR_TWPH(0x0E) | \ 304 FTIM2_NOR_TWP(0x1c)) 305 #define CONFIG_SYS_NOR_FTIM3 0x0 306 307 #define CONFIG_SYS_FLASH_QUIET_TEST 308 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 309 310 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 311 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 312 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 313 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 314 315 #define CONFIG_SYS_FLASH_EMPTY_INFO 316 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 317 318 /* CPLD on IFC */ 319 #define CPLD_LBMAP_MASK 0x3F 320 #define CPLD_BANK_SEL_MASK 0x07 321 #define CPLD_BANK_OVERRIDE 0x40 322 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 323 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 324 #define CPLD_LBMAP_RESET 0xFF 325 #define CPLD_LBMAP_SHIFT 0x03 326 327 #if defined(CONFIG_TARGET_T1042RDB_PI) 328 #define CPLD_DIU_SEL_DFP 0x80 329 #elif defined(CONFIG_TARGET_T1042D4RDB) 330 #define CPLD_DIU_SEL_DFP 0xc0 331 #endif 332 333 #if defined(CONFIG_TARGET_T1040D4RDB) 334 #define CPLD_INT_MASK_ALL 0xFF 335 #define CPLD_INT_MASK_THERM 0x80 336 #define CPLD_INT_MASK_DVI_DFP 0x40 337 #define CPLD_INT_MASK_QSGMII1 0x20 338 #define CPLD_INT_MASK_QSGMII2 0x10 339 #define CPLD_INT_MASK_SGMI1 0x08 340 #define CPLD_INT_MASK_SGMI2 0x04 341 #define CPLD_INT_MASK_TDMR1 0x02 342 #define CPLD_INT_MASK_TDMR2 0x01 343 #endif 344 345 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 346 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 347 #define CONFIG_SYS_CSPR2_EXT (0xf) 348 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 349 | CSPR_PORT_SIZE_8 \ 350 | CSPR_MSEL_GPCM \ 351 | CSPR_V) 352 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 353 #define CONFIG_SYS_CSOR2 0x0 354 /* CPLD Timing parameters for IFC CS2 */ 355 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 356 FTIM0_GPCM_TEADC(0x0e) | \ 357 FTIM0_GPCM_TEAHC(0x0e)) 358 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 359 FTIM1_GPCM_TRAD(0x1f)) 360 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 361 FTIM2_GPCM_TCH(0x8) | \ 362 FTIM2_GPCM_TWP(0x1f)) 363 #define CONFIG_SYS_CS2_FTIM3 0x0 364 365 /* NAND Flash on IFC */ 366 #define CONFIG_NAND_FSL_IFC 367 #define CONFIG_SYS_NAND_BASE 0xff800000 368 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 369 370 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 371 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 372 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 373 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 374 | CSPR_V) 375 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 376 377 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 378 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 379 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 380 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 381 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 382 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 383 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 384 385 #define CONFIG_SYS_NAND_ONFI_DETECTION 386 387 /* ONFI NAND Flash mode0 Timing Params */ 388 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 389 FTIM0_NAND_TWP(0x18) | \ 390 FTIM0_NAND_TWCHT(0x07) | \ 391 FTIM0_NAND_TWH(0x0a)) 392 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 393 FTIM1_NAND_TWBE(0x39) | \ 394 FTIM1_NAND_TRR(0x0e) | \ 395 FTIM1_NAND_TRP(0x18)) 396 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 397 FTIM2_NAND_TREH(0x0a) | \ 398 FTIM2_NAND_TWHRE(0x1e)) 399 #define CONFIG_SYS_NAND_FTIM3 0x0 400 401 #define CONFIG_SYS_NAND_DDR_LAW 11 402 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 403 #define CONFIG_SYS_MAX_NAND_DEVICE 1 404 #define CONFIG_CMD_NAND 405 406 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 407 408 #if defined(CONFIG_NAND) 409 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 410 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 411 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 412 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 413 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 414 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 415 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 416 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 417 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 418 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 419 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 420 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 421 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 422 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 423 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 424 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 425 #else 426 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 427 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 428 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 429 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 430 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 431 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 432 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 433 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 434 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 435 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 436 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 437 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 438 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 439 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 440 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 441 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 442 #endif 443 444 #ifdef CONFIG_SPL_BUILD 445 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 446 #else 447 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 448 #endif 449 450 #if defined(CONFIG_RAMBOOT_PBL) 451 #define CONFIG_SYS_RAMBOOT 452 #endif 453 454 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 455 #if defined(CONFIG_NAND) 456 #define CONFIG_A008044_WORKAROUND 457 #endif 458 #endif 459 460 #define CONFIG_BOARD_EARLY_INIT_R 461 #define CONFIG_MISC_INIT_R 462 463 #define CONFIG_HWCONFIG 464 465 /* define to use L1 as initial stack */ 466 #define CONFIG_L1_INIT_RAM 467 #define CONFIG_SYS_INIT_RAM_LOCK 468 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 469 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 471 /* The assembler doesn't like typecast */ 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 473 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 474 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 475 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 476 477 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 478 GENERATED_GBL_DATA_SIZE) 479 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 480 481 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 482 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 483 484 /* Serial Port - controlled on board with jumper J8 485 * open - index 2 486 * shorted - index 1 487 */ 488 #define CONFIG_CONS_INDEX 1 489 #define CONFIG_SYS_NS16550_SERIAL 490 #define CONFIG_SYS_NS16550_REG_SIZE 1 491 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 492 493 #define CONFIG_SYS_BAUDRATE_TABLE \ 494 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 495 496 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 497 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 498 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 499 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 500 501 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 502 /* Video */ 503 #define CONFIG_FSL_DIU_FB 504 505 #ifdef CONFIG_FSL_DIU_FB 506 #define CONFIG_FSL_DIU_CH7301 507 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 508 #define CONFIG_VIDEO_LOGO 509 #define CONFIG_VIDEO_BMP_LOGO 510 #endif 511 #endif 512 513 /* I2C */ 514 #define CONFIG_SYS_I2C 515 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 516 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 517 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 518 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 519 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 520 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 521 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 522 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 523 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 524 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 525 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 526 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 527 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 528 529 /* I2C bus multiplexer */ 530 #define I2C_MUX_PCA_ADDR 0x70 531 #define I2C_MUX_CH_DEFAULT 0x8 532 533 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 534 defined(CONFIG_TARGET_T1040D4RDB) || \ 535 defined(CONFIG_TARGET_T1042D4RDB) 536 /* LDI/DVI Encoder for display */ 537 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 538 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 539 540 /* 541 * RTC configuration 542 */ 543 #define RTC 544 #define CONFIG_RTC_DS1337 1 545 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 546 547 /*DVI encoder*/ 548 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 549 #endif 550 551 /* 552 * eSPI - Enhanced SPI 553 */ 554 #define CONFIG_SPI_FLASH_BAR 555 #define CONFIG_SF_DEFAULT_SPEED 10000000 556 #define CONFIG_SF_DEFAULT_MODE 0 557 #define CONFIG_ENV_SPI_BUS 0 558 #define CONFIG_ENV_SPI_CS 0 559 #define CONFIG_ENV_SPI_MAX_HZ 10000000 560 #define CONFIG_ENV_SPI_MODE 0 561 562 /* 563 * General PCI 564 * Memory space is mapped 1-1, but I/O space must start from 0. 565 */ 566 567 #ifdef CONFIG_PCI 568 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 569 #ifdef CONFIG_PCIE1 570 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 571 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 572 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 573 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 574 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 575 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 576 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 577 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 578 #endif 579 580 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 581 #ifdef CONFIG_PCIE2 582 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 583 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 584 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 585 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 586 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 587 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 588 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 589 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 590 #endif 591 592 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 593 #ifdef CONFIG_PCIE3 594 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 595 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 596 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 597 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 598 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 599 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 600 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 601 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 602 #endif 603 604 /* controller 4, Base address 203000 */ 605 #ifdef CONFIG_PCIE4 606 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 607 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 608 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 609 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 610 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 611 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 612 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 613 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 614 #endif 615 616 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 617 #endif /* CONFIG_PCI */ 618 619 /* SATA */ 620 #define CONFIG_FSL_SATA_V2 621 #ifdef CONFIG_FSL_SATA_V2 622 #define CONFIG_LIBATA 623 #define CONFIG_FSL_SATA 624 625 #define CONFIG_SYS_SATA_MAX_DEVICE 1 626 #define CONFIG_SATA1 627 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 628 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 629 630 #define CONFIG_LBA48 631 #define CONFIG_CMD_SATA 632 #endif 633 634 /* 635 * USB 636 */ 637 #define CONFIG_HAS_FSL_DR_USB 638 639 #ifdef CONFIG_HAS_FSL_DR_USB 640 #ifdef CONFIG_USB_EHCI_HCD 641 #define CONFIG_USB_EHCI_FSL 642 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 643 #endif 644 #endif 645 646 #ifdef CONFIG_MMC 647 #define CONFIG_FSL_ESDHC 648 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 649 #endif 650 651 /* Qman/Bman */ 652 #ifndef CONFIG_NOBQFMAN 653 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 654 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 655 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 656 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 657 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 658 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 659 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 660 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 661 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 662 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 663 CONFIG_SYS_BMAN_CENA_SIZE) 664 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 665 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 666 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 667 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 668 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 669 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 670 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 671 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 672 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 673 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 674 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 675 CONFIG_SYS_QMAN_CENA_SIZE) 676 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 677 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 678 679 #define CONFIG_SYS_DPAA_FMAN 680 #define CONFIG_SYS_DPAA_PME 681 682 #define CONFIG_QE 683 #define CONFIG_U_QE 684 685 /* Default address of microcode for the Linux Fman driver */ 686 #if defined(CONFIG_SPIFLASH) 687 /* 688 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 689 * env, so we got 0x110000. 690 */ 691 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 692 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 693 #elif defined(CONFIG_SDCARD) 694 /* 695 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 696 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 697 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 698 */ 699 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 700 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 701 #elif defined(CONFIG_NAND) 702 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 703 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 704 #else 705 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 706 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 707 #endif 708 709 #if defined(CONFIG_SPIFLASH) 710 #define CONFIG_SYS_QE_FW_ADDR 0x130000 711 #elif defined(CONFIG_SDCARD) 712 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 713 #elif defined(CONFIG_NAND) 714 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 715 #else 716 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 717 #endif 718 719 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 720 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 721 #endif /* CONFIG_NOBQFMAN */ 722 723 #ifdef CONFIG_SYS_DPAA_FMAN 724 #define CONFIG_FMAN_ENET 725 #define CONFIG_PHY_VITESSE 726 #define CONFIG_PHY_REALTEK 727 #endif 728 729 #ifdef CONFIG_FMAN_ENET 730 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 731 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 732 #elif defined(CONFIG_TARGET_T1040D4RDB) 733 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 734 #elif defined(CONFIG_TARGET_T1042D4RDB) 735 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 736 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 737 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 738 #endif 739 740 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 741 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 742 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 743 #else 744 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 745 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 746 #endif 747 748 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 749 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 750 #define CONFIG_VSC9953 751 #define CONFIG_CMD_ETHSW 752 #ifdef CONFIG_TARGET_T1040RDB 753 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 754 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 755 #else 756 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 757 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 758 #endif 759 #endif 760 761 #define CONFIG_MII /* MII PHY management */ 762 #define CONFIG_ETHPRIME "FM1@DTSEC4" 763 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 764 #endif 765 766 /* 767 * Environment 768 */ 769 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 770 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 771 772 /* 773 * Command line configuration. 774 */ 775 #define CONFIG_CMD_ERRATA 776 #define CONFIG_CMD_IRQ 777 #define CONFIG_CMD_REGINFO 778 779 #ifdef CONFIG_PCI 780 #define CONFIG_CMD_PCI 781 #endif 782 783 /* Hash command with SHA acceleration supported in hardware */ 784 #ifdef CONFIG_FSL_CAAM 785 #define CONFIG_CMD_HASH 786 #define CONFIG_SHA_HW_ACCEL 787 #endif 788 789 /* 790 * Miscellaneous configurable options 791 */ 792 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 793 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 794 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 795 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 796 #ifdef CONFIG_CMD_KGDB 797 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 798 #else 799 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 800 #endif 801 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 802 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 803 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 804 805 /* 806 * For booting Linux, the board info and command line data 807 * have to be in the first 64 MB of memory, since this is 808 * the maximum mapped by the Linux kernel during initialization. 809 */ 810 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 811 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 812 813 #ifdef CONFIG_CMD_KGDB 814 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 815 #endif 816 817 /* 818 * Dynamic MTD Partition support with mtdparts 819 */ 820 #ifdef CONFIG_MTD_NOR_FLASH 821 #define CONFIG_MTD_DEVICE 822 #define CONFIG_MTD_PARTITIONS 823 #define CONFIG_CMD_MTDPARTS 824 #define CONFIG_FLASH_CFI_MTD 825 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 826 "spi0=spife110000.0" 827 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 828 "128k(dtb),96m(fs),-(user);"\ 829 "fff800000.flash:2m(uboot),9m(kernel),"\ 830 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 831 "2m(uboot),9m(kernel),128k(dtb),-(user)" 832 #endif 833 834 /* 835 * Environment Configuration 836 */ 837 #define CONFIG_ROOTPATH "/opt/nfsroot" 838 #define CONFIG_BOOTFILE "uImage" 839 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 840 841 /* default location for tftp and bootm */ 842 #define CONFIG_LOADADDR 1000000 843 844 #define __USB_PHY_TYPE utmi 845 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 846 847 #ifdef CONFIG_TARGET_T1040RDB 848 #define FDTFILE "t1040rdb/t1040rdb.dtb" 849 #elif defined(CONFIG_TARGET_T1042RDB_PI) 850 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 851 #elif defined(CONFIG_TARGET_T1042RDB) 852 #define FDTFILE "t1042rdb/t1042rdb.dtb" 853 #elif defined(CONFIG_TARGET_T1040D4RDB) 854 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 855 #elif defined(CONFIG_TARGET_T1042D4RDB) 856 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 857 #endif 858 859 #ifdef CONFIG_FSL_DIU_FB 860 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 861 #else 862 #define DIU_ENVIRONMENT 863 #endif 864 865 #define CONFIG_EXTRA_ENV_SETTINGS \ 866 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 867 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 868 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 869 "netdev=eth0\0" \ 870 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 871 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 872 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 873 "tftpflash=tftpboot $loadaddr $uboot && " \ 874 "protect off $ubootaddr +$filesize && " \ 875 "erase $ubootaddr +$filesize && " \ 876 "cp.b $loadaddr $ubootaddr $filesize && " \ 877 "protect on $ubootaddr +$filesize && " \ 878 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 879 "consoledev=ttyS0\0" \ 880 "ramdiskaddr=2000000\0" \ 881 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 882 "fdtaddr=1e00000\0" \ 883 "fdtfile=" __stringify(FDTFILE) "\0" \ 884 "bdev=sda3\0" 885 886 #define CONFIG_LINUX \ 887 "setenv bootargs root=/dev/ram rw " \ 888 "console=$consoledev,$baudrate $othbootargs;" \ 889 "setenv ramdiskaddr 0x02000000;" \ 890 "setenv fdtaddr 0x00c00000;" \ 891 "setenv loadaddr 0x1000000;" \ 892 "bootm $loadaddr $ramdiskaddr $fdtaddr" 893 894 #define CONFIG_HDBOOT \ 895 "setenv bootargs root=/dev/$bdev rw " \ 896 "console=$consoledev,$baudrate $othbootargs;" \ 897 "tftp $loadaddr $bootfile;" \ 898 "tftp $fdtaddr $fdtfile;" \ 899 "bootm $loadaddr - $fdtaddr" 900 901 #define CONFIG_NFSBOOTCOMMAND \ 902 "setenv bootargs root=/dev/nfs rw " \ 903 "nfsroot=$serverip:$rootpath " \ 904 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 905 "console=$consoledev,$baudrate $othbootargs;" \ 906 "tftp $loadaddr $bootfile;" \ 907 "tftp $fdtaddr $fdtfile;" \ 908 "bootm $loadaddr - $fdtaddr" 909 910 #define CONFIG_RAMBOOTCOMMAND \ 911 "setenv bootargs root=/dev/ram rw " \ 912 "console=$consoledev,$baudrate $othbootargs;" \ 913 "tftp $ramdiskaddr $ramdiskfile;" \ 914 "tftp $loadaddr $bootfile;" \ 915 "tftp $fdtaddr $fdtfile;" \ 916 "bootm $loadaddr $ramdiskaddr $fdtaddr" 917 918 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 919 920 #include <asm/fsl_secure_boot.h> 921 922 #endif /* __CONFIG_H */ 923