1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 /* 10 * T104x RDB board configuration file 11 */ 12 #include <asm/config_mpc85xx.h> 13 14 #ifdef CONFIG_RAMBOOT_PBL 15 16 #ifndef CONFIG_SECURE_BOOT 17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 18 #else 19 #define CONFIG_SYS_FSL_PBL_PBI \ 20 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 21 #endif 22 23 #define CONFIG_SPL_FLUSH_IMAGE 24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 25 #define CONFIG_SPL_PAD_TO 0x40000 26 #define CONFIG_SPL_MAX_SIZE 0x28000 27 #ifdef CONFIG_SPL_BUILD 28 #define CONFIG_SPL_SKIP_RELOCATE 29 #define CONFIG_SPL_COMMON_INIT_DDR 30 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 31 #endif 32 #define RESET_VECTOR_OFFSET 0x27FFC 33 #define BOOT_PAGE_OFFSET 0x27000 34 35 #ifdef CONFIG_NAND 36 #ifdef CONFIG_SECURE_BOOT 37 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 38 /* 39 * HDR would be appended at end of image and copied to DDR along 40 * with U-Boot image. 41 */ 42 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 43 CONFIG_U_BOOT_HDR_SIZE) 44 #else 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 46 #endif 47 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 48 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 49 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 50 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 51 #ifdef CONFIG_TARGET_T1040RDB 52 #define CONFIG_SYS_FSL_PBL_RCW \ 53 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 54 #endif 55 #ifdef CONFIG_TARGET_T1042RDB_PI 56 #define CONFIG_SYS_FSL_PBL_RCW \ 57 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 58 #endif 59 #ifdef CONFIG_TARGET_T1042RDB 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 62 #endif 63 #ifdef CONFIG_TARGET_T1040D4RDB 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 66 #endif 67 #ifdef CONFIG_TARGET_T1042D4RDB 68 #define CONFIG_SYS_FSL_PBL_RCW \ 69 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 70 #endif 71 #define CONFIG_SPL_NAND_BOOT 72 #endif 73 74 #ifdef CONFIG_SPIFLASH 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 76 #define CONFIG_SPL_SPI_FLASH_MINIMAL 77 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 81 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 82 #ifndef CONFIG_SPL_BUILD 83 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 84 #endif 85 #ifdef CONFIG_TARGET_T1040RDB 86 #define CONFIG_SYS_FSL_PBL_RCW \ 87 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 88 #endif 89 #ifdef CONFIG_TARGET_T1042RDB_PI 90 #define CONFIG_SYS_FSL_PBL_RCW \ 91 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 92 #endif 93 #ifdef CONFIG_TARGET_T1042RDB 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_TARGET_T1040D4RDB 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 100 #endif 101 #ifdef CONFIG_TARGET_T1042D4RDB 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 104 #endif 105 #define CONFIG_SPL_SPI_BOOT 106 #endif 107 108 #ifdef CONFIG_SDCARD 109 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 110 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 111 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 112 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 113 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 114 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 115 #ifndef CONFIG_SPL_BUILD 116 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 117 #endif 118 #ifdef CONFIG_TARGET_T1040RDB 119 #define CONFIG_SYS_FSL_PBL_RCW \ 120 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 121 #endif 122 #ifdef CONFIG_TARGET_T1042RDB_PI 123 #define CONFIG_SYS_FSL_PBL_RCW \ 124 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 125 #endif 126 #ifdef CONFIG_TARGET_T1042RDB 127 #define CONFIG_SYS_FSL_PBL_RCW \ 128 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 129 #endif 130 #ifdef CONFIG_TARGET_T1040D4RDB 131 #define CONFIG_SYS_FSL_PBL_RCW \ 132 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 133 #endif 134 #ifdef CONFIG_TARGET_T1042D4RDB 135 #define CONFIG_SYS_FSL_PBL_RCW \ 136 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 137 #endif 138 #define CONFIG_SPL_MMC_BOOT 139 #endif 140 141 #endif 142 143 /* High Level Configuration Options */ 144 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 145 146 /* support deep sleep */ 147 #define CONFIG_DEEP_SLEEP 148 149 #ifndef CONFIG_RESET_VECTOR_ADDRESS 150 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 151 #endif 152 153 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 154 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 155 #define CONFIG_PCI_INDIRECT_BRIDGE 156 #define CONFIG_PCIE1 /* PCIE controller 1 */ 157 #define CONFIG_PCIE2 /* PCIE controller 2 */ 158 #define CONFIG_PCIE3 /* PCIE controller 3 */ 159 #define CONFIG_PCIE4 /* PCIE controller 4 */ 160 161 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 162 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 163 164 #define CONFIG_ENV_OVERWRITE 165 166 #if defined(CONFIG_SPIFLASH) 167 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 168 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 169 #define CONFIG_ENV_SECT_SIZE 0x10000 170 #elif defined(CONFIG_SDCARD) 171 #define CONFIG_SYS_MMC_ENV_DEV 0 172 #define CONFIG_ENV_SIZE 0x2000 173 #define CONFIG_ENV_OFFSET (512 * 0x800) 174 #elif defined(CONFIG_NAND) 175 #ifdef CONFIG_SECURE_BOOT 176 #define CONFIG_RAMBOOT_NAND 177 #define CONFIG_BOOTSCRIPT_COPY_RAM 178 #endif 179 #define CONFIG_ENV_SIZE 0x2000 180 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 181 #else 182 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 183 #define CONFIG_ENV_SIZE 0x2000 184 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 185 #endif 186 187 #define CONFIG_SYS_CLK_FREQ 100000000 188 #define CONFIG_DDR_CLK_FREQ 66666666 189 190 /* 191 * These can be toggled for performance analysis, otherwise use default. 192 */ 193 #define CONFIG_SYS_CACHE_STASHING 194 #define CONFIG_BACKSIDE_L2_CACHE 195 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 196 #define CONFIG_BTB /* toggle branch predition */ 197 #define CONFIG_DDR_ECC 198 #ifdef CONFIG_DDR_ECC 199 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 200 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 201 #endif 202 203 #define CONFIG_ENABLE_36BIT_PHYS 204 205 #define CONFIG_ADDR_MAP 206 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 207 208 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 209 #define CONFIG_SYS_MEMTEST_END 0x00400000 210 211 /* 212 * Config the L3 Cache as L3 SRAM 213 */ 214 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 215 /* 216 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 217 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 218 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 219 */ 220 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 221 #define CONFIG_SYS_L3_SIZE 256 << 10 222 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 223 #ifdef CONFIG_RAMBOOT_PBL 224 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 225 #endif 226 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 227 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 228 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 229 230 #define CONFIG_SYS_DCSRBAR 0xf0000000 231 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 232 233 /* 234 * DDR Setup 235 */ 236 #define CONFIG_VERY_BIG_RAM 237 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 238 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 239 240 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 241 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 242 243 #define CONFIG_DDR_SPD 244 245 #define CONFIG_SYS_SPD_BUS_NUM 0 246 #define SPD_EEPROM_ADDRESS 0x51 247 248 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 249 250 /* 251 * IFC Definitions 252 */ 253 #define CONFIG_SYS_FLASH_BASE 0xe8000000 254 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 255 256 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 257 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 258 CSPR_PORT_SIZE_16 | \ 259 CSPR_MSEL_NOR | \ 260 CSPR_V) 261 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 262 263 /* 264 * TDM Definition 265 */ 266 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 267 268 /* NOR Flash Timing Params */ 269 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 270 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 271 FTIM0_NOR_TEADC(0x5) | \ 272 FTIM0_NOR_TEAHC(0x5)) 273 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 274 FTIM1_NOR_TRAD_NOR(0x1A) |\ 275 FTIM1_NOR_TSEQRAD_NOR(0x13)) 276 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 277 FTIM2_NOR_TCH(0x4) | \ 278 FTIM2_NOR_TWPH(0x0E) | \ 279 FTIM2_NOR_TWP(0x1c)) 280 #define CONFIG_SYS_NOR_FTIM3 0x0 281 282 #define CONFIG_SYS_FLASH_QUIET_TEST 283 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 284 285 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 286 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 287 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 288 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 289 290 #define CONFIG_SYS_FLASH_EMPTY_INFO 291 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 292 293 /* CPLD on IFC */ 294 #define CPLD_LBMAP_MASK 0x3F 295 #define CPLD_BANK_SEL_MASK 0x07 296 #define CPLD_BANK_OVERRIDE 0x40 297 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 298 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 299 #define CPLD_LBMAP_RESET 0xFF 300 #define CPLD_LBMAP_SHIFT 0x03 301 302 #if defined(CONFIG_TARGET_T1042RDB_PI) 303 #define CPLD_DIU_SEL_DFP 0x80 304 #elif defined(CONFIG_TARGET_T1042D4RDB) 305 #define CPLD_DIU_SEL_DFP 0xc0 306 #endif 307 308 #if defined(CONFIG_TARGET_T1040D4RDB) 309 #define CPLD_INT_MASK_ALL 0xFF 310 #define CPLD_INT_MASK_THERM 0x80 311 #define CPLD_INT_MASK_DVI_DFP 0x40 312 #define CPLD_INT_MASK_QSGMII1 0x20 313 #define CPLD_INT_MASK_QSGMII2 0x10 314 #define CPLD_INT_MASK_SGMI1 0x08 315 #define CPLD_INT_MASK_SGMI2 0x04 316 #define CPLD_INT_MASK_TDMR1 0x02 317 #define CPLD_INT_MASK_TDMR2 0x01 318 #endif 319 320 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 321 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 322 #define CONFIG_SYS_CSPR2_EXT (0xf) 323 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 324 | CSPR_PORT_SIZE_8 \ 325 | CSPR_MSEL_GPCM \ 326 | CSPR_V) 327 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 328 #define CONFIG_SYS_CSOR2 0x0 329 /* CPLD Timing parameters for IFC CS2 */ 330 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 331 FTIM0_GPCM_TEADC(0x0e) | \ 332 FTIM0_GPCM_TEAHC(0x0e)) 333 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 334 FTIM1_GPCM_TRAD(0x1f)) 335 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 336 FTIM2_GPCM_TCH(0x8) | \ 337 FTIM2_GPCM_TWP(0x1f)) 338 #define CONFIG_SYS_CS2_FTIM3 0x0 339 340 /* NAND Flash on IFC */ 341 #define CONFIG_NAND_FSL_IFC 342 #define CONFIG_SYS_NAND_BASE 0xff800000 343 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 344 345 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 346 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 347 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 348 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 349 | CSPR_V) 350 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 351 352 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 353 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 354 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 355 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 356 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 357 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 358 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 359 360 #define CONFIG_SYS_NAND_ONFI_DETECTION 361 362 /* ONFI NAND Flash mode0 Timing Params */ 363 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 364 FTIM0_NAND_TWP(0x18) | \ 365 FTIM0_NAND_TWCHT(0x07) | \ 366 FTIM0_NAND_TWH(0x0a)) 367 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 368 FTIM1_NAND_TWBE(0x39) | \ 369 FTIM1_NAND_TRR(0x0e) | \ 370 FTIM1_NAND_TRP(0x18)) 371 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 372 FTIM2_NAND_TREH(0x0a) | \ 373 FTIM2_NAND_TWHRE(0x1e)) 374 #define CONFIG_SYS_NAND_FTIM3 0x0 375 376 #define CONFIG_SYS_NAND_DDR_LAW 11 377 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 378 #define CONFIG_SYS_MAX_NAND_DEVICE 1 379 380 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 381 382 #if defined(CONFIG_NAND) 383 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 384 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 385 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 386 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 387 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 388 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 389 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 390 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 391 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 392 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 393 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 394 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 395 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 396 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 397 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 398 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 399 #else 400 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 401 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 402 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 403 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 404 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 405 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 406 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 407 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 408 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 409 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 410 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 411 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 412 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 413 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 414 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 415 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 416 #endif 417 418 #ifdef CONFIG_SPL_BUILD 419 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 420 #else 421 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 422 #endif 423 424 #if defined(CONFIG_RAMBOOT_PBL) 425 #define CONFIG_SYS_RAMBOOT 426 #endif 427 428 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 429 #if defined(CONFIG_NAND) 430 #define CONFIG_A008044_WORKAROUND 431 #endif 432 #endif 433 434 #define CONFIG_HWCONFIG 435 436 /* define to use L1 as initial stack */ 437 #define CONFIG_L1_INIT_RAM 438 #define CONFIG_SYS_INIT_RAM_LOCK 439 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 442 /* The assembler doesn't like typecast */ 443 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 444 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 445 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 446 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 447 448 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 449 GENERATED_GBL_DATA_SIZE) 450 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 451 452 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 453 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 454 455 /* Serial Port - controlled on board with jumper J8 456 * open - index 2 457 * shorted - index 1 458 */ 459 #define CONFIG_SYS_NS16550_SERIAL 460 #define CONFIG_SYS_NS16550_REG_SIZE 1 461 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 462 463 #define CONFIG_SYS_BAUDRATE_TABLE \ 464 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 465 466 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 467 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 468 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 469 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 470 471 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 472 /* Video */ 473 #define CONFIG_FSL_DIU_FB 474 475 #ifdef CONFIG_FSL_DIU_FB 476 #define CONFIG_FSL_DIU_CH7301 477 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 478 #define CONFIG_VIDEO_LOGO 479 #define CONFIG_VIDEO_BMP_LOGO 480 #endif 481 #endif 482 483 /* I2C */ 484 #define CONFIG_SYS_I2C 485 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 486 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 487 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 488 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 489 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 490 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 491 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 492 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 493 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 494 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 495 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 496 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 497 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 498 499 /* I2C bus multiplexer */ 500 #define I2C_MUX_PCA_ADDR 0x70 501 #define I2C_MUX_CH_DEFAULT 0x8 502 503 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 504 defined(CONFIG_TARGET_T1040D4RDB) || \ 505 defined(CONFIG_TARGET_T1042D4RDB) 506 /* LDI/DVI Encoder for display */ 507 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 508 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 509 510 /* 511 * RTC configuration 512 */ 513 #define RTC 514 #define CONFIG_RTC_DS1337 1 515 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 516 517 /*DVI encoder*/ 518 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 519 #endif 520 521 /* 522 * eSPI - Enhanced SPI 523 */ 524 #define CONFIG_SPI_FLASH_BAR 525 #define CONFIG_SF_DEFAULT_SPEED 10000000 526 #define CONFIG_SF_DEFAULT_MODE 0 527 #define CONFIG_ENV_SPI_BUS 0 528 #define CONFIG_ENV_SPI_CS 0 529 #define CONFIG_ENV_SPI_MAX_HZ 10000000 530 #define CONFIG_ENV_SPI_MODE 0 531 532 /* 533 * General PCI 534 * Memory space is mapped 1-1, but I/O space must start from 0. 535 */ 536 537 #ifdef CONFIG_PCI 538 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 539 #ifdef CONFIG_PCIE1 540 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 541 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 542 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 543 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 544 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 545 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 546 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 547 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 548 #endif 549 550 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 551 #ifdef CONFIG_PCIE2 552 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 553 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 554 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 555 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 556 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 557 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 558 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 559 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 560 #endif 561 562 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 563 #ifdef CONFIG_PCIE3 564 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 565 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 566 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 567 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 568 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 569 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 570 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 571 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 572 #endif 573 574 /* controller 4, Base address 203000 */ 575 #ifdef CONFIG_PCIE4 576 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 577 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 578 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 579 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 580 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 581 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 582 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 583 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 584 #endif 585 586 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 587 #endif /* CONFIG_PCI */ 588 589 /* SATA */ 590 #define CONFIG_FSL_SATA_V2 591 #ifdef CONFIG_FSL_SATA_V2 592 #define CONFIG_SYS_SATA_MAX_DEVICE 1 593 #define CONFIG_SATA1 594 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 595 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 596 597 #define CONFIG_LBA48 598 #endif 599 600 /* 601 * USB 602 */ 603 #define CONFIG_HAS_FSL_DR_USB 604 605 #ifdef CONFIG_HAS_FSL_DR_USB 606 #ifdef CONFIG_USB_EHCI_HCD 607 #define CONFIG_USB_EHCI_FSL 608 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 609 #endif 610 #endif 611 612 #ifdef CONFIG_MMC 613 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 614 #endif 615 616 /* Qman/Bman */ 617 #ifndef CONFIG_NOBQFMAN 618 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 619 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 620 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 621 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 622 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 623 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 624 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 625 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 626 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 627 CONFIG_SYS_BMAN_CENA_SIZE) 628 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 629 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 630 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 631 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 632 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 633 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 634 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 635 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 636 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 637 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 638 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 639 CONFIG_SYS_QMAN_CENA_SIZE) 640 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 641 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 642 643 #define CONFIG_SYS_DPAA_FMAN 644 #define CONFIG_SYS_DPAA_PME 645 646 #define CONFIG_QE 647 #define CONFIG_U_QE 648 649 /* Default address of microcode for the Linux Fman driver */ 650 #if defined(CONFIG_SPIFLASH) 651 /* 652 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 653 * env, so we got 0x110000. 654 */ 655 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 656 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 657 #elif defined(CONFIG_SDCARD) 658 /* 659 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 660 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 661 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 662 */ 663 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 664 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 665 #elif defined(CONFIG_NAND) 666 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 667 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 668 #else 669 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 670 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 671 #endif 672 673 #if defined(CONFIG_SPIFLASH) 674 #define CONFIG_SYS_QE_FW_ADDR 0x130000 675 #elif defined(CONFIG_SDCARD) 676 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 677 #elif defined(CONFIG_NAND) 678 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 679 #else 680 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 681 #endif 682 683 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 684 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 685 #endif /* CONFIG_NOBQFMAN */ 686 687 #ifdef CONFIG_SYS_DPAA_FMAN 688 #define CONFIG_FMAN_ENET 689 #define CONFIG_PHY_VITESSE 690 #define CONFIG_PHY_REALTEK 691 #endif 692 693 #ifdef CONFIG_FMAN_ENET 694 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 695 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 696 #elif defined(CONFIG_TARGET_T1040D4RDB) 697 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 698 #elif defined(CONFIG_TARGET_T1042D4RDB) 699 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 700 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 701 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 702 #endif 703 704 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 705 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 706 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 707 #else 708 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 709 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 710 #endif 711 712 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 713 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 714 #define CONFIG_VSC9953 715 #ifdef CONFIG_TARGET_T1040RDB 716 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 717 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 718 #else 719 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 720 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 721 #endif 722 #endif 723 724 #define CONFIG_ETHPRIME "FM1@DTSEC4" 725 #endif 726 727 /* 728 * Environment 729 */ 730 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 731 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 732 733 /* 734 * Miscellaneous configurable options 735 */ 736 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 737 738 /* 739 * For booting Linux, the board info and command line data 740 * have to be in the first 64 MB of memory, since this is 741 * the maximum mapped by the Linux kernel during initialization. 742 */ 743 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 744 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 745 746 #ifdef CONFIG_CMD_KGDB 747 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 748 #endif 749 750 /* 751 * Dynamic MTD Partition support with mtdparts 752 */ 753 754 /* 755 * Environment Configuration 756 */ 757 #define CONFIG_ROOTPATH "/opt/nfsroot" 758 #define CONFIG_BOOTFILE "uImage" 759 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 760 761 /* default location for tftp and bootm */ 762 #define CONFIG_LOADADDR 1000000 763 764 #define __USB_PHY_TYPE utmi 765 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 766 767 #ifdef CONFIG_TARGET_T1040RDB 768 #define FDTFILE "t1040rdb/t1040rdb.dtb" 769 #elif defined(CONFIG_TARGET_T1042RDB_PI) 770 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 771 #elif defined(CONFIG_TARGET_T1042RDB) 772 #define FDTFILE "t1042rdb/t1042rdb.dtb" 773 #elif defined(CONFIG_TARGET_T1040D4RDB) 774 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 775 #elif defined(CONFIG_TARGET_T1042D4RDB) 776 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 777 #endif 778 779 #ifdef CONFIG_FSL_DIU_FB 780 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 781 #else 782 #define DIU_ENVIRONMENT 783 #endif 784 785 #define CONFIG_EXTRA_ENV_SETTINGS \ 786 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 787 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 788 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 789 "netdev=eth0\0" \ 790 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 791 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 792 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 793 "tftpflash=tftpboot $loadaddr $uboot && " \ 794 "protect off $ubootaddr +$filesize && " \ 795 "erase $ubootaddr +$filesize && " \ 796 "cp.b $loadaddr $ubootaddr $filesize && " \ 797 "protect on $ubootaddr +$filesize && " \ 798 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 799 "consoledev=ttyS0\0" \ 800 "ramdiskaddr=2000000\0" \ 801 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 802 "fdtaddr=1e00000\0" \ 803 "fdtfile=" __stringify(FDTFILE) "\0" \ 804 "bdev=sda3\0" 805 806 #define CONFIG_LINUX \ 807 "setenv bootargs root=/dev/ram rw " \ 808 "console=$consoledev,$baudrate $othbootargs;" \ 809 "setenv ramdiskaddr 0x02000000;" \ 810 "setenv fdtaddr 0x00c00000;" \ 811 "setenv loadaddr 0x1000000;" \ 812 "bootm $loadaddr $ramdiskaddr $fdtaddr" 813 814 #define CONFIG_HDBOOT \ 815 "setenv bootargs root=/dev/$bdev rw " \ 816 "console=$consoledev,$baudrate $othbootargs;" \ 817 "tftp $loadaddr $bootfile;" \ 818 "tftp $fdtaddr $fdtfile;" \ 819 "bootm $loadaddr - $fdtaddr" 820 821 #define CONFIG_NFSBOOTCOMMAND \ 822 "setenv bootargs root=/dev/nfs rw " \ 823 "nfsroot=$serverip:$rootpath " \ 824 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 825 "console=$consoledev,$baudrate $othbootargs;" \ 826 "tftp $loadaddr $bootfile;" \ 827 "tftp $fdtaddr $fdtfile;" \ 828 "bootm $loadaddr - $fdtaddr" 829 830 #define CONFIG_RAMBOOTCOMMAND \ 831 "setenv bootargs root=/dev/ram rw " \ 832 "console=$consoledev,$baudrate $othbootargs;" \ 833 "tftp $ramdiskaddr $ramdiskfile;" \ 834 "tftp $loadaddr $bootfile;" \ 835 "tftp $fdtaddr $fdtfile;" \ 836 "bootm $loadaddr $ramdiskaddr $fdtaddr" 837 838 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 839 840 #include <asm/fsl_secure_boot.h> 841 842 #endif /* __CONFIG_H */ 843