1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #include <asm/config_mpc85xx.h> 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 17 #ifndef CONFIG_SECURE_BOOT 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 19 #else 20 #define CONFIG_SYS_FSL_PBL_PBI \ 21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 22 #endif 23 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x30001000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_SKIP_RELOCATE 32 #define CONFIG_SPL_COMMON_INIT_DDR 33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 34 #define CONFIG_SYS_NO_FLASH 35 #endif 36 #define RESET_VECTOR_OFFSET 0x27FFC 37 #define BOOT_PAGE_OFFSET 0x27000 38 39 #ifdef CONFIG_NAND 40 #ifdef CONFIG_SECURE_BOOT 41 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 42 /* 43 * HDR would be appended at end of image and copied to DDR along 44 * with U-Boot image. 45 */ 46 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 47 CONFIG_U_BOOT_HDR_SIZE) 48 #else 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 50 #endif 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #ifdef CONFIG_TARGET_T1040RDB 56 #define CONFIG_SYS_FSL_PBL_RCW \ 57 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 58 #endif 59 #ifdef CONFIG_TARGET_T1042RDB_PI 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 62 #endif 63 #ifdef CONFIG_TARGET_T1042RDB 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 66 #endif 67 #ifdef CONFIG_TARGET_T1040D4RDB 68 #define CONFIG_SYS_FSL_PBL_RCW \ 69 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 70 #endif 71 #ifdef CONFIG_TARGET_T1042D4RDB 72 #define CONFIG_SYS_FSL_PBL_RCW \ 73 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 74 #endif 75 #define CONFIG_SPL_NAND_BOOT 76 #endif 77 78 #ifdef CONFIG_SPIFLASH 79 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 80 #define CONFIG_SPL_SPI_FLASH_MINIMAL 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #ifdef CONFIG_TARGET_T1040RDB 90 #define CONFIG_SYS_FSL_PBL_RCW \ 91 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 92 #endif 93 #ifdef CONFIG_TARGET_T1042RDB_PI 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_TARGET_T1042RDB 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 100 #endif 101 #ifdef CONFIG_TARGET_T1040D4RDB 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 104 #endif 105 #ifdef CONFIG_TARGET_T1042D4RDB 106 #define CONFIG_SYS_FSL_PBL_RCW \ 107 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 108 #endif 109 #define CONFIG_SPL_SPI_BOOT 110 #endif 111 112 #ifdef CONFIG_SDCARD 113 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 114 #define CONFIG_SPL_MMC_MINIMAL 115 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 116 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 117 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 118 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 119 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 120 #ifndef CONFIG_SPL_BUILD 121 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 122 #endif 123 #ifdef CONFIG_TARGET_T1040RDB 124 #define CONFIG_SYS_FSL_PBL_RCW \ 125 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 126 #endif 127 #ifdef CONFIG_TARGET_T1042RDB_PI 128 #define CONFIG_SYS_FSL_PBL_RCW \ 129 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 130 #endif 131 #ifdef CONFIG_TARGET_T1042RDB 132 #define CONFIG_SYS_FSL_PBL_RCW \ 133 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 134 #endif 135 #ifdef CONFIG_TARGET_T1040D4RDB 136 #define CONFIG_SYS_FSL_PBL_RCW \ 137 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 138 #endif 139 #ifdef CONFIG_TARGET_T1042D4RDB 140 #define CONFIG_SYS_FSL_PBL_RCW \ 141 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 142 #endif 143 #define CONFIG_SPL_MMC_BOOT 144 #endif 145 146 #endif 147 148 /* High Level Configuration Options */ 149 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 150 #define CONFIG_MP /* support multiple processors */ 151 152 /* support deep sleep */ 153 #define CONFIG_DEEP_SLEEP 154 #if defined(CONFIG_DEEP_SLEEP) 155 #define CONFIG_BOARD_EARLY_INIT_F 156 #endif 157 158 #ifndef CONFIG_SYS_TEXT_BASE 159 #define CONFIG_SYS_TEXT_BASE 0xeff40000 160 #endif 161 162 #ifndef CONFIG_RESET_VECTOR_ADDRESS 163 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 164 #endif 165 166 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 167 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 168 #define CONFIG_FSL_IFC /* Enable IFC Support */ 169 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 170 #define CONFIG_PCI_INDIRECT_BRIDGE 171 #define CONFIG_PCIE1 /* PCIE controller 1 */ 172 #define CONFIG_PCIE2 /* PCIE controller 2 */ 173 #define CONFIG_PCIE3 /* PCIE controller 3 */ 174 #define CONFIG_PCIE4 /* PCIE controller 4 */ 175 176 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 177 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 178 179 #define CONFIG_ENV_OVERWRITE 180 181 #ifndef CONFIG_SYS_NO_FLASH 182 #define CONFIG_FLASH_CFI_DRIVER 183 #define CONFIG_SYS_FLASH_CFI 184 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 185 #endif 186 187 #if defined(CONFIG_SPIFLASH) 188 #define CONFIG_SYS_EXTRA_ENV_RELOC 189 #define CONFIG_ENV_IS_IN_SPI_FLASH 190 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 191 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 192 #define CONFIG_ENV_SECT_SIZE 0x10000 193 #elif defined(CONFIG_SDCARD) 194 #define CONFIG_SYS_EXTRA_ENV_RELOC 195 #define CONFIG_ENV_IS_IN_MMC 196 #define CONFIG_SYS_MMC_ENV_DEV 0 197 #define CONFIG_ENV_SIZE 0x2000 198 #define CONFIG_ENV_OFFSET (512 * 0x800) 199 #elif defined(CONFIG_NAND) 200 #ifdef CONFIG_SECURE_BOOT 201 #define CONFIG_RAMBOOT_NAND 202 #define CONFIG_BOOTSCRIPT_COPY_RAM 203 #endif 204 #define CONFIG_SYS_EXTRA_ENV_RELOC 205 #define CONFIG_ENV_IS_IN_NAND 206 #define CONFIG_ENV_SIZE 0x2000 207 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 208 #else 209 #define CONFIG_ENV_IS_IN_FLASH 210 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 211 #define CONFIG_ENV_SIZE 0x2000 212 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 213 #endif 214 215 #define CONFIG_SYS_CLK_FREQ 100000000 216 #define CONFIG_DDR_CLK_FREQ 66666666 217 218 /* 219 * These can be toggled for performance analysis, otherwise use default. 220 */ 221 #define CONFIG_SYS_CACHE_STASHING 222 #define CONFIG_BACKSIDE_L2_CACHE 223 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 224 #define CONFIG_BTB /* toggle branch predition */ 225 #define CONFIG_DDR_ECC 226 #ifdef CONFIG_DDR_ECC 227 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 228 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 229 #endif 230 231 #define CONFIG_ENABLE_36BIT_PHYS 232 233 #define CONFIG_ADDR_MAP 234 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 235 236 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 237 #define CONFIG_SYS_MEMTEST_END 0x00400000 238 #define CONFIG_SYS_ALT_MEMTEST 239 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 240 241 /* 242 * Config the L3 Cache as L3 SRAM 243 */ 244 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 245 /* 246 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 247 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 248 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 249 */ 250 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 251 #define CONFIG_SYS_L3_SIZE 256 << 10 252 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 253 #ifdef CONFIG_RAMBOOT_PBL 254 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 255 #endif 256 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 257 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 258 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 259 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 260 261 #define CONFIG_SYS_DCSRBAR 0xf0000000 262 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 263 264 /* 265 * DDR Setup 266 */ 267 #define CONFIG_VERY_BIG_RAM 268 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 269 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 270 271 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 272 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 273 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 274 275 #define CONFIG_DDR_SPD 276 277 #define CONFIG_SYS_SPD_BUS_NUM 0 278 #define SPD_EEPROM_ADDRESS 0x51 279 280 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 281 282 /* 283 * IFC Definitions 284 */ 285 #define CONFIG_SYS_FLASH_BASE 0xe8000000 286 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 287 288 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 289 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 290 CSPR_PORT_SIZE_16 | \ 291 CSPR_MSEL_NOR | \ 292 CSPR_V) 293 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 294 295 /* 296 * TDM Definition 297 */ 298 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 299 300 /* NOR Flash Timing Params */ 301 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 302 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 303 FTIM0_NOR_TEADC(0x5) | \ 304 FTIM0_NOR_TEAHC(0x5)) 305 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 306 FTIM1_NOR_TRAD_NOR(0x1A) |\ 307 FTIM1_NOR_TSEQRAD_NOR(0x13)) 308 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 309 FTIM2_NOR_TCH(0x4) | \ 310 FTIM2_NOR_TWPH(0x0E) | \ 311 FTIM2_NOR_TWP(0x1c)) 312 #define CONFIG_SYS_NOR_FTIM3 0x0 313 314 #define CONFIG_SYS_FLASH_QUIET_TEST 315 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 316 317 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 318 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 319 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 320 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 321 322 #define CONFIG_SYS_FLASH_EMPTY_INFO 323 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 324 325 /* CPLD on IFC */ 326 #define CPLD_LBMAP_MASK 0x3F 327 #define CPLD_BANK_SEL_MASK 0x07 328 #define CPLD_BANK_OVERRIDE 0x40 329 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 330 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 331 #define CPLD_LBMAP_RESET 0xFF 332 #define CPLD_LBMAP_SHIFT 0x03 333 334 #if defined(CONFIG_TARGET_T1042RDB_PI) 335 #define CPLD_DIU_SEL_DFP 0x80 336 #elif defined(CONFIG_TARGET_T1042D4RDB) 337 #define CPLD_DIU_SEL_DFP 0xc0 338 #endif 339 340 #if defined(CONFIG_TARGET_T1040D4RDB) 341 #define CPLD_INT_MASK_ALL 0xFF 342 #define CPLD_INT_MASK_THERM 0x80 343 #define CPLD_INT_MASK_DVI_DFP 0x40 344 #define CPLD_INT_MASK_QSGMII1 0x20 345 #define CPLD_INT_MASK_QSGMII2 0x10 346 #define CPLD_INT_MASK_SGMI1 0x08 347 #define CPLD_INT_MASK_SGMI2 0x04 348 #define CPLD_INT_MASK_TDMR1 0x02 349 #define CPLD_INT_MASK_TDMR2 0x01 350 #endif 351 352 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 353 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 354 #define CONFIG_SYS_CSPR2_EXT (0xf) 355 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 356 | CSPR_PORT_SIZE_8 \ 357 | CSPR_MSEL_GPCM \ 358 | CSPR_V) 359 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 360 #define CONFIG_SYS_CSOR2 0x0 361 /* CPLD Timing parameters for IFC CS2 */ 362 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 363 FTIM0_GPCM_TEADC(0x0e) | \ 364 FTIM0_GPCM_TEAHC(0x0e)) 365 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 366 FTIM1_GPCM_TRAD(0x1f)) 367 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 368 FTIM2_GPCM_TCH(0x8) | \ 369 FTIM2_GPCM_TWP(0x1f)) 370 #define CONFIG_SYS_CS2_FTIM3 0x0 371 372 /* NAND Flash on IFC */ 373 #define CONFIG_NAND_FSL_IFC 374 #define CONFIG_SYS_NAND_BASE 0xff800000 375 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 376 377 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 378 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 379 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 380 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 381 | CSPR_V) 382 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 383 384 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 385 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 386 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 387 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 388 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 389 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 390 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 391 392 #define CONFIG_SYS_NAND_ONFI_DETECTION 393 394 /* ONFI NAND Flash mode0 Timing Params */ 395 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 396 FTIM0_NAND_TWP(0x18) | \ 397 FTIM0_NAND_TWCHT(0x07) | \ 398 FTIM0_NAND_TWH(0x0a)) 399 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 400 FTIM1_NAND_TWBE(0x39) | \ 401 FTIM1_NAND_TRR(0x0e) | \ 402 FTIM1_NAND_TRP(0x18)) 403 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 404 FTIM2_NAND_TREH(0x0a) | \ 405 FTIM2_NAND_TWHRE(0x1e)) 406 #define CONFIG_SYS_NAND_FTIM3 0x0 407 408 #define CONFIG_SYS_NAND_DDR_LAW 11 409 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 410 #define CONFIG_SYS_MAX_NAND_DEVICE 1 411 #define CONFIG_CMD_NAND 412 413 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 414 415 #if defined(CONFIG_NAND) 416 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 417 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 418 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 419 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 420 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 421 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 422 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 423 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 424 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 425 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 426 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 427 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 428 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 429 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 430 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 431 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 432 #else 433 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 434 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 435 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 436 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 437 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 438 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 439 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 440 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 441 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 442 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 443 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 444 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 445 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 446 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 447 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 448 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 449 #endif 450 451 #ifdef CONFIG_SPL_BUILD 452 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 453 #else 454 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 455 #endif 456 457 #if defined(CONFIG_RAMBOOT_PBL) 458 #define CONFIG_SYS_RAMBOOT 459 #endif 460 461 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 462 #if defined(CONFIG_NAND) 463 #define CONFIG_A008044_WORKAROUND 464 #endif 465 #endif 466 467 #define CONFIG_BOARD_EARLY_INIT_R 468 #define CONFIG_MISC_INIT_R 469 470 #define CONFIG_HWCONFIG 471 472 /* define to use L1 as initial stack */ 473 #define CONFIG_L1_INIT_RAM 474 #define CONFIG_SYS_INIT_RAM_LOCK 475 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 476 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 477 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 478 /* The assembler doesn't like typecast */ 479 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 480 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 481 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 482 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 483 484 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 485 GENERATED_GBL_DATA_SIZE) 486 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 487 488 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 489 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 490 491 /* Serial Port - controlled on board with jumper J8 492 * open - index 2 493 * shorted - index 1 494 */ 495 #define CONFIG_CONS_INDEX 1 496 #define CONFIG_SYS_NS16550_SERIAL 497 #define CONFIG_SYS_NS16550_REG_SIZE 1 498 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 499 500 #define CONFIG_SYS_BAUDRATE_TABLE \ 501 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 502 503 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 504 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 505 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 506 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 507 508 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 509 /* Video */ 510 #define CONFIG_FSL_DIU_FB 511 512 #ifdef CONFIG_FSL_DIU_FB 513 #define CONFIG_FSL_DIU_CH7301 514 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 515 #define CONFIG_CMD_BMP 516 #define CONFIG_VIDEO_LOGO 517 #define CONFIG_VIDEO_BMP_LOGO 518 #endif 519 #endif 520 521 /* I2C */ 522 #define CONFIG_SYS_I2C 523 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 524 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 525 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 526 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 527 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 528 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 529 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 530 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 531 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 532 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 533 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 534 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 535 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 536 537 /* I2C bus multiplexer */ 538 #define I2C_MUX_PCA_ADDR 0x70 539 #define I2C_MUX_CH_DEFAULT 0x8 540 541 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 542 defined(CONFIG_TARGET_T1040D4RDB) || \ 543 defined(CONFIG_TARGET_T1042D4RDB) 544 /* LDI/DVI Encoder for display */ 545 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 546 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 547 548 /* 549 * RTC configuration 550 */ 551 #define RTC 552 #define CONFIG_RTC_DS1337 1 553 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 554 555 /*DVI encoder*/ 556 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 557 #endif 558 559 /* 560 * eSPI - Enhanced SPI 561 */ 562 #define CONFIG_SPI_FLASH_BAR 563 #define CONFIG_SF_DEFAULT_SPEED 10000000 564 #define CONFIG_SF_DEFAULT_MODE 0 565 #define CONFIG_ENV_SPI_BUS 0 566 #define CONFIG_ENV_SPI_CS 0 567 #define CONFIG_ENV_SPI_MAX_HZ 10000000 568 #define CONFIG_ENV_SPI_MODE 0 569 570 /* 571 * General PCI 572 * Memory space is mapped 1-1, but I/O space must start from 0. 573 */ 574 575 #ifdef CONFIG_PCI 576 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 577 #ifdef CONFIG_PCIE1 578 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 579 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 580 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 581 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 582 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 583 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 584 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 585 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 586 #endif 587 588 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 589 #ifdef CONFIG_PCIE2 590 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 591 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 592 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 593 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 594 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 595 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 596 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 597 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 598 #endif 599 600 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 601 #ifdef CONFIG_PCIE3 602 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 603 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 604 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 605 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 606 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 607 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 608 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 609 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 610 #endif 611 612 /* controller 4, Base address 203000 */ 613 #ifdef CONFIG_PCIE4 614 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 615 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 616 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 617 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 618 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 619 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 620 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 621 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 622 #endif 623 624 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 625 #define CONFIG_DOS_PARTITION 626 #endif /* CONFIG_PCI */ 627 628 /* SATA */ 629 #define CONFIG_FSL_SATA_V2 630 #ifdef CONFIG_FSL_SATA_V2 631 #define CONFIG_LIBATA 632 #define CONFIG_FSL_SATA 633 634 #define CONFIG_SYS_SATA_MAX_DEVICE 1 635 #define CONFIG_SATA1 636 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 637 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 638 639 #define CONFIG_LBA48 640 #define CONFIG_CMD_SATA 641 #define CONFIG_DOS_PARTITION 642 #endif 643 644 /* 645 * USB 646 */ 647 #define CONFIG_HAS_FSL_DR_USB 648 649 #ifdef CONFIG_HAS_FSL_DR_USB 650 #define CONFIG_USB_EHCI 651 652 #ifdef CONFIG_USB_EHCI 653 #define CONFIG_USB_EHCI_FSL 654 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 655 #endif 656 #endif 657 658 #ifdef CONFIG_MMC 659 #define CONFIG_FSL_ESDHC 660 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 661 #define CONFIG_GENERIC_MMC 662 #define CONFIG_DOS_PARTITION 663 #endif 664 665 /* Qman/Bman */ 666 #ifndef CONFIG_NOBQFMAN 667 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 668 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 669 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 670 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 671 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 672 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 673 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 674 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 675 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 676 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 677 CONFIG_SYS_BMAN_CENA_SIZE) 678 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 679 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 680 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 681 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 682 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 683 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 684 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 685 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 686 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 687 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 688 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 689 CONFIG_SYS_QMAN_CENA_SIZE) 690 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 691 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 692 693 #define CONFIG_SYS_DPAA_FMAN 694 #define CONFIG_SYS_DPAA_PME 695 696 #define CONFIG_QE 697 #define CONFIG_U_QE 698 699 /* Default address of microcode for the Linux Fman driver */ 700 #if defined(CONFIG_SPIFLASH) 701 /* 702 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 703 * env, so we got 0x110000. 704 */ 705 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 706 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 707 #elif defined(CONFIG_SDCARD) 708 /* 709 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 710 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 711 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 712 */ 713 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 714 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 715 #elif defined(CONFIG_NAND) 716 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 717 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 718 #else 719 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 720 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 721 #endif 722 723 #if defined(CONFIG_SPIFLASH) 724 #define CONFIG_SYS_QE_FW_ADDR 0x130000 725 #elif defined(CONFIG_SDCARD) 726 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 727 #elif defined(CONFIG_NAND) 728 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 729 #else 730 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 731 #endif 732 733 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 734 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 735 #endif /* CONFIG_NOBQFMAN */ 736 737 #ifdef CONFIG_SYS_DPAA_FMAN 738 #define CONFIG_FMAN_ENET 739 #define CONFIG_PHY_VITESSE 740 #define CONFIG_PHY_REALTEK 741 #endif 742 743 #ifdef CONFIG_FMAN_ENET 744 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 745 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 746 #elif defined(CONFIG_TARGET_T1040D4RDB) 747 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 748 #elif defined(CONFIG_TARGET_T1042D4RDB) 749 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 750 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 751 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 752 #endif 753 754 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 755 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 756 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 757 #else 758 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 759 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 760 #endif 761 762 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 763 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 764 #define CONFIG_VSC9953 765 #define CONFIG_CMD_ETHSW 766 #ifdef CONFIG_TARGET_T1040RDB 767 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 768 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 769 #else 770 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 771 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 772 #endif 773 #endif 774 775 #define CONFIG_MII /* MII PHY management */ 776 #define CONFIG_ETHPRIME "FM1@DTSEC4" 777 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 778 #endif 779 780 /* 781 * Environment 782 */ 783 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 784 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 785 786 /* 787 * Command line configuration. 788 */ 789 #ifdef CONFIG_TARGET_T1042RDB_PI 790 #define CONFIG_CMD_DATE 791 #endif 792 #define CONFIG_CMD_ERRATA 793 #define CONFIG_CMD_IRQ 794 #define CONFIG_CMD_REGINFO 795 796 #ifdef CONFIG_PCI 797 #define CONFIG_CMD_PCI 798 #endif 799 800 /* Hash command with SHA acceleration supported in hardware */ 801 #ifdef CONFIG_FSL_CAAM 802 #define CONFIG_CMD_HASH 803 #define CONFIG_SHA_HW_ACCEL 804 #endif 805 806 /* 807 * Miscellaneous configurable options 808 */ 809 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 810 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 811 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 812 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 813 #ifdef CONFIG_CMD_KGDB 814 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 815 #else 816 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 817 #endif 818 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 819 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 820 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 821 822 /* 823 * For booting Linux, the board info and command line data 824 * have to be in the first 64 MB of memory, since this is 825 * the maximum mapped by the Linux kernel during initialization. 826 */ 827 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 828 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 829 830 #ifdef CONFIG_CMD_KGDB 831 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 832 #endif 833 834 /* 835 * Dynamic MTD Partition support with mtdparts 836 */ 837 #ifndef CONFIG_SYS_NO_FLASH 838 #define CONFIG_MTD_DEVICE 839 #define CONFIG_MTD_PARTITIONS 840 #define CONFIG_CMD_MTDPARTS 841 #define CONFIG_FLASH_CFI_MTD 842 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 843 "spi0=spife110000.0" 844 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 845 "128k(dtb),96m(fs),-(user);"\ 846 "fff800000.flash:2m(uboot),9m(kernel),"\ 847 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 848 "2m(uboot),9m(kernel),128k(dtb),-(user)" 849 #endif 850 851 /* 852 * Environment Configuration 853 */ 854 #define CONFIG_ROOTPATH "/opt/nfsroot" 855 #define CONFIG_BOOTFILE "uImage" 856 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 857 858 /* default location for tftp and bootm */ 859 #define CONFIG_LOADADDR 1000000 860 861 862 #define CONFIG_BAUDRATE 115200 863 864 #define __USB_PHY_TYPE utmi 865 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 866 867 #ifdef CONFIG_TARGET_T1040RDB 868 #define FDTFILE "t1040rdb/t1040rdb.dtb" 869 #elif defined(CONFIG_TARGET_T1042RDB_PI) 870 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 871 #elif defined(CONFIG_TARGET_T1042RDB) 872 #define FDTFILE "t1042rdb/t1042rdb.dtb" 873 #elif defined(CONFIG_TARGET_T1040D4RDB) 874 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 875 #elif defined(CONFIG_TARGET_T1042D4RDB) 876 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 877 #endif 878 879 #ifdef CONFIG_FSL_DIU_FB 880 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 881 #else 882 #define DIU_ENVIRONMENT 883 #endif 884 885 #define CONFIG_EXTRA_ENV_SETTINGS \ 886 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 887 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 888 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 889 "netdev=eth0\0" \ 890 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 891 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 892 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 893 "tftpflash=tftpboot $loadaddr $uboot && " \ 894 "protect off $ubootaddr +$filesize && " \ 895 "erase $ubootaddr +$filesize && " \ 896 "cp.b $loadaddr $ubootaddr $filesize && " \ 897 "protect on $ubootaddr +$filesize && " \ 898 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 899 "consoledev=ttyS0\0" \ 900 "ramdiskaddr=2000000\0" \ 901 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 902 "fdtaddr=1e00000\0" \ 903 "fdtfile=" __stringify(FDTFILE) "\0" \ 904 "bdev=sda3\0" 905 906 #define CONFIG_LINUX \ 907 "setenv bootargs root=/dev/ram rw " \ 908 "console=$consoledev,$baudrate $othbootargs;" \ 909 "setenv ramdiskaddr 0x02000000;" \ 910 "setenv fdtaddr 0x00c00000;" \ 911 "setenv loadaddr 0x1000000;" \ 912 "bootm $loadaddr $ramdiskaddr $fdtaddr" 913 914 #define CONFIG_HDBOOT \ 915 "setenv bootargs root=/dev/$bdev rw " \ 916 "console=$consoledev,$baudrate $othbootargs;" \ 917 "tftp $loadaddr $bootfile;" \ 918 "tftp $fdtaddr $fdtfile;" \ 919 "bootm $loadaddr - $fdtaddr" 920 921 #define CONFIG_NFSBOOTCOMMAND \ 922 "setenv bootargs root=/dev/nfs rw " \ 923 "nfsroot=$serverip:$rootpath " \ 924 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 925 "console=$consoledev,$baudrate $othbootargs;" \ 926 "tftp $loadaddr $bootfile;" \ 927 "tftp $fdtaddr $fdtfile;" \ 928 "bootm $loadaddr - $fdtaddr" 929 930 #define CONFIG_RAMBOOTCOMMAND \ 931 "setenv bootargs root=/dev/ram rw " \ 932 "console=$consoledev,$baudrate $othbootargs;" \ 933 "tftp $ramdiskaddr $ramdiskfile;" \ 934 "tftp $loadaddr $bootfile;" \ 935 "tftp $fdtaddr $fdtfile;" \ 936 "bootm $loadaddr $ramdiskaddr $fdtaddr" 937 938 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 939 940 #include <asm/fsl_secure_boot.h> 941 942 #endif /* __CONFIG_H */ 943