1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #include <asm/config_mpc85xx.h> 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 17 #ifndef CONFIG_SECURE_BOOT 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 19 #else 20 #define CONFIG_SYS_FSL_PBL_PBI \ 21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 22 #endif 23 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 27 #define CONFIG_SPL_PAD_TO 0x40000 28 #define CONFIG_SPL_MAX_SIZE 0x28000 29 #ifdef CONFIG_SPL_BUILD 30 #define CONFIG_SPL_SKIP_RELOCATE 31 #define CONFIG_SPL_COMMON_INIT_DDR 32 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 33 #endif 34 #define RESET_VECTOR_OFFSET 0x27FFC 35 #define BOOT_PAGE_OFFSET 0x27000 36 37 #ifdef CONFIG_NAND 38 #ifdef CONFIG_SECURE_BOOT 39 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 40 /* 41 * HDR would be appended at end of image and copied to DDR along 42 * with U-Boot image. 43 */ 44 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 45 CONFIG_U_BOOT_HDR_SIZE) 46 #else 47 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 48 #endif 49 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 50 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 51 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 52 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 53 #ifdef CONFIG_TARGET_T1040RDB 54 #define CONFIG_SYS_FSL_PBL_RCW \ 55 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 56 #endif 57 #ifdef CONFIG_TARGET_T1042RDB_PI 58 #define CONFIG_SYS_FSL_PBL_RCW \ 59 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 60 #endif 61 #ifdef CONFIG_TARGET_T1042RDB 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 64 #endif 65 #ifdef CONFIG_TARGET_T1040D4RDB 66 #define CONFIG_SYS_FSL_PBL_RCW \ 67 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 68 #endif 69 #ifdef CONFIG_TARGET_T1042D4RDB 70 #define CONFIG_SYS_FSL_PBL_RCW \ 71 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 72 #endif 73 #define CONFIG_SPL_NAND_BOOT 74 #endif 75 76 #ifdef CONFIG_SPIFLASH 77 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 78 #define CONFIG_SPL_SPI_FLASH_MINIMAL 79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 83 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 84 #ifndef CONFIG_SPL_BUILD 85 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 86 #endif 87 #ifdef CONFIG_TARGET_T1040RDB 88 #define CONFIG_SYS_FSL_PBL_RCW \ 89 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 90 #endif 91 #ifdef CONFIG_TARGET_T1042RDB_PI 92 #define CONFIG_SYS_FSL_PBL_RCW \ 93 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 94 #endif 95 #ifdef CONFIG_TARGET_T1042RDB 96 #define CONFIG_SYS_FSL_PBL_RCW \ 97 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 98 #endif 99 #ifdef CONFIG_TARGET_T1040D4RDB 100 #define CONFIG_SYS_FSL_PBL_RCW \ 101 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 102 #endif 103 #ifdef CONFIG_TARGET_T1042D4RDB 104 #define CONFIG_SYS_FSL_PBL_RCW \ 105 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 106 #endif 107 #define CONFIG_SPL_SPI_BOOT 108 #endif 109 110 #ifdef CONFIG_SDCARD 111 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 112 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 113 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 114 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 115 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 116 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 117 #ifndef CONFIG_SPL_BUILD 118 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 119 #endif 120 #ifdef CONFIG_TARGET_T1040RDB 121 #define CONFIG_SYS_FSL_PBL_RCW \ 122 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 123 #endif 124 #ifdef CONFIG_TARGET_T1042RDB_PI 125 #define CONFIG_SYS_FSL_PBL_RCW \ 126 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 127 #endif 128 #ifdef CONFIG_TARGET_T1042RDB 129 #define CONFIG_SYS_FSL_PBL_RCW \ 130 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 131 #endif 132 #ifdef CONFIG_TARGET_T1040D4RDB 133 #define CONFIG_SYS_FSL_PBL_RCW \ 134 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 135 #endif 136 #ifdef CONFIG_TARGET_T1042D4RDB 137 #define CONFIG_SYS_FSL_PBL_RCW \ 138 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 139 #endif 140 #define CONFIG_SPL_MMC_BOOT 141 #endif 142 143 #endif 144 145 /* High Level Configuration Options */ 146 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 147 #define CONFIG_MP /* support multiple processors */ 148 149 /* support deep sleep */ 150 #define CONFIG_DEEP_SLEEP 151 152 #ifndef CONFIG_RESET_VECTOR_ADDRESS 153 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 154 #endif 155 156 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 157 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 158 #define CONFIG_PCI_INDIRECT_BRIDGE 159 #define CONFIG_PCIE1 /* PCIE controller 1 */ 160 #define CONFIG_PCIE2 /* PCIE controller 2 */ 161 #define CONFIG_PCIE3 /* PCIE controller 3 */ 162 #define CONFIG_PCIE4 /* PCIE controller 4 */ 163 164 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 165 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 166 167 #define CONFIG_ENV_OVERWRITE 168 169 #ifdef CONFIG_MTD_NOR_FLASH 170 #define CONFIG_FLASH_CFI_DRIVER 171 #define CONFIG_SYS_FLASH_CFI 172 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 173 #endif 174 175 #if defined(CONFIG_SPIFLASH) 176 #define CONFIG_SYS_EXTRA_ENV_RELOC 177 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 178 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 179 #define CONFIG_ENV_SECT_SIZE 0x10000 180 #elif defined(CONFIG_SDCARD) 181 #define CONFIG_SYS_EXTRA_ENV_RELOC 182 #define CONFIG_SYS_MMC_ENV_DEV 0 183 #define CONFIG_ENV_SIZE 0x2000 184 #define CONFIG_ENV_OFFSET (512 * 0x800) 185 #elif defined(CONFIG_NAND) 186 #ifdef CONFIG_SECURE_BOOT 187 #define CONFIG_RAMBOOT_NAND 188 #define CONFIG_BOOTSCRIPT_COPY_RAM 189 #endif 190 #define CONFIG_SYS_EXTRA_ENV_RELOC 191 #define CONFIG_ENV_SIZE 0x2000 192 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 193 #else 194 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 195 #define CONFIG_ENV_SIZE 0x2000 196 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 197 #endif 198 199 #define CONFIG_SYS_CLK_FREQ 100000000 200 #define CONFIG_DDR_CLK_FREQ 66666666 201 202 /* 203 * These can be toggled for performance analysis, otherwise use default. 204 */ 205 #define CONFIG_SYS_CACHE_STASHING 206 #define CONFIG_BACKSIDE_L2_CACHE 207 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 208 #define CONFIG_BTB /* toggle branch predition */ 209 #define CONFIG_DDR_ECC 210 #ifdef CONFIG_DDR_ECC 211 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 212 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 213 #endif 214 215 #define CONFIG_ENABLE_36BIT_PHYS 216 217 #define CONFIG_ADDR_MAP 218 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 219 220 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 221 #define CONFIG_SYS_MEMTEST_END 0x00400000 222 223 /* 224 * Config the L3 Cache as L3 SRAM 225 */ 226 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 227 /* 228 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 229 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 230 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 231 */ 232 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 233 #define CONFIG_SYS_L3_SIZE 256 << 10 234 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 235 #ifdef CONFIG_RAMBOOT_PBL 236 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 237 #endif 238 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 239 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 240 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 241 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 242 243 #define CONFIG_SYS_DCSRBAR 0xf0000000 244 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 245 246 /* 247 * DDR Setup 248 */ 249 #define CONFIG_VERY_BIG_RAM 250 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 251 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 252 253 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 254 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 255 256 #define CONFIG_DDR_SPD 257 258 #define CONFIG_SYS_SPD_BUS_NUM 0 259 #define SPD_EEPROM_ADDRESS 0x51 260 261 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 262 263 /* 264 * IFC Definitions 265 */ 266 #define CONFIG_SYS_FLASH_BASE 0xe8000000 267 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 268 269 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 270 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 271 CSPR_PORT_SIZE_16 | \ 272 CSPR_MSEL_NOR | \ 273 CSPR_V) 274 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 275 276 /* 277 * TDM Definition 278 */ 279 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 280 281 /* NOR Flash Timing Params */ 282 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 283 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 284 FTIM0_NOR_TEADC(0x5) | \ 285 FTIM0_NOR_TEAHC(0x5)) 286 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 287 FTIM1_NOR_TRAD_NOR(0x1A) |\ 288 FTIM1_NOR_TSEQRAD_NOR(0x13)) 289 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 290 FTIM2_NOR_TCH(0x4) | \ 291 FTIM2_NOR_TWPH(0x0E) | \ 292 FTIM2_NOR_TWP(0x1c)) 293 #define CONFIG_SYS_NOR_FTIM3 0x0 294 295 #define CONFIG_SYS_FLASH_QUIET_TEST 296 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 297 298 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 299 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 300 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 301 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 302 303 #define CONFIG_SYS_FLASH_EMPTY_INFO 304 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 305 306 /* CPLD on IFC */ 307 #define CPLD_LBMAP_MASK 0x3F 308 #define CPLD_BANK_SEL_MASK 0x07 309 #define CPLD_BANK_OVERRIDE 0x40 310 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 311 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 312 #define CPLD_LBMAP_RESET 0xFF 313 #define CPLD_LBMAP_SHIFT 0x03 314 315 #if defined(CONFIG_TARGET_T1042RDB_PI) 316 #define CPLD_DIU_SEL_DFP 0x80 317 #elif defined(CONFIG_TARGET_T1042D4RDB) 318 #define CPLD_DIU_SEL_DFP 0xc0 319 #endif 320 321 #if defined(CONFIG_TARGET_T1040D4RDB) 322 #define CPLD_INT_MASK_ALL 0xFF 323 #define CPLD_INT_MASK_THERM 0x80 324 #define CPLD_INT_MASK_DVI_DFP 0x40 325 #define CPLD_INT_MASK_QSGMII1 0x20 326 #define CPLD_INT_MASK_QSGMII2 0x10 327 #define CPLD_INT_MASK_SGMI1 0x08 328 #define CPLD_INT_MASK_SGMI2 0x04 329 #define CPLD_INT_MASK_TDMR1 0x02 330 #define CPLD_INT_MASK_TDMR2 0x01 331 #endif 332 333 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 334 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 335 #define CONFIG_SYS_CSPR2_EXT (0xf) 336 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 337 | CSPR_PORT_SIZE_8 \ 338 | CSPR_MSEL_GPCM \ 339 | CSPR_V) 340 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 341 #define CONFIG_SYS_CSOR2 0x0 342 /* CPLD Timing parameters for IFC CS2 */ 343 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 344 FTIM0_GPCM_TEADC(0x0e) | \ 345 FTIM0_GPCM_TEAHC(0x0e)) 346 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 347 FTIM1_GPCM_TRAD(0x1f)) 348 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 349 FTIM2_GPCM_TCH(0x8) | \ 350 FTIM2_GPCM_TWP(0x1f)) 351 #define CONFIG_SYS_CS2_FTIM3 0x0 352 353 /* NAND Flash on IFC */ 354 #define CONFIG_NAND_FSL_IFC 355 #define CONFIG_SYS_NAND_BASE 0xff800000 356 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 357 358 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 359 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 360 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 361 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 362 | CSPR_V) 363 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 364 365 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 366 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 367 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 368 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 369 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 370 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 371 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 372 373 #define CONFIG_SYS_NAND_ONFI_DETECTION 374 375 /* ONFI NAND Flash mode0 Timing Params */ 376 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 377 FTIM0_NAND_TWP(0x18) | \ 378 FTIM0_NAND_TWCHT(0x07) | \ 379 FTIM0_NAND_TWH(0x0a)) 380 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 381 FTIM1_NAND_TWBE(0x39) | \ 382 FTIM1_NAND_TRR(0x0e) | \ 383 FTIM1_NAND_TRP(0x18)) 384 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 385 FTIM2_NAND_TREH(0x0a) | \ 386 FTIM2_NAND_TWHRE(0x1e)) 387 #define CONFIG_SYS_NAND_FTIM3 0x0 388 389 #define CONFIG_SYS_NAND_DDR_LAW 11 390 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 391 #define CONFIG_SYS_MAX_NAND_DEVICE 1 392 393 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 394 395 #if defined(CONFIG_NAND) 396 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 397 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 398 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 399 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 400 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 401 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 402 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 403 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 404 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 405 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 406 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 407 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 408 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 409 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 410 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 411 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 412 #else 413 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 414 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 415 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 416 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 417 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 418 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 419 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 420 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 421 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 422 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 423 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 424 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 425 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 426 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 427 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 428 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 429 #endif 430 431 #ifdef CONFIG_SPL_BUILD 432 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 433 #else 434 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 435 #endif 436 437 #if defined(CONFIG_RAMBOOT_PBL) 438 #define CONFIG_SYS_RAMBOOT 439 #endif 440 441 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 442 #if defined(CONFIG_NAND) 443 #define CONFIG_A008044_WORKAROUND 444 #endif 445 #endif 446 447 #define CONFIG_MISC_INIT_R 448 449 #define CONFIG_HWCONFIG 450 451 /* define to use L1 as initial stack */ 452 #define CONFIG_L1_INIT_RAM 453 #define CONFIG_SYS_INIT_RAM_LOCK 454 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 455 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 457 /* The assembler doesn't like typecast */ 458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 459 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 460 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 461 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 462 463 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 464 GENERATED_GBL_DATA_SIZE) 465 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 466 467 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 468 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 469 470 /* Serial Port - controlled on board with jumper J8 471 * open - index 2 472 * shorted - index 1 473 */ 474 #define CONFIG_SYS_NS16550_SERIAL 475 #define CONFIG_SYS_NS16550_REG_SIZE 1 476 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 477 478 #define CONFIG_SYS_BAUDRATE_TABLE \ 479 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 480 481 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 482 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 483 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 484 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 485 486 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 487 /* Video */ 488 #define CONFIG_FSL_DIU_FB 489 490 #ifdef CONFIG_FSL_DIU_FB 491 #define CONFIG_FSL_DIU_CH7301 492 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 493 #define CONFIG_VIDEO_LOGO 494 #define CONFIG_VIDEO_BMP_LOGO 495 #endif 496 #endif 497 498 /* I2C */ 499 #define CONFIG_SYS_I2C 500 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 501 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 502 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 503 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 504 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 505 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 506 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 507 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 508 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 509 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 510 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 511 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 512 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 513 514 /* I2C bus multiplexer */ 515 #define I2C_MUX_PCA_ADDR 0x70 516 #define I2C_MUX_CH_DEFAULT 0x8 517 518 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 519 defined(CONFIG_TARGET_T1040D4RDB) || \ 520 defined(CONFIG_TARGET_T1042D4RDB) 521 /* LDI/DVI Encoder for display */ 522 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 523 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 524 525 /* 526 * RTC configuration 527 */ 528 #define RTC 529 #define CONFIG_RTC_DS1337 1 530 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 531 532 /*DVI encoder*/ 533 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 534 #endif 535 536 /* 537 * eSPI - Enhanced SPI 538 */ 539 #define CONFIG_SPI_FLASH_BAR 540 #define CONFIG_SF_DEFAULT_SPEED 10000000 541 #define CONFIG_SF_DEFAULT_MODE 0 542 #define CONFIG_ENV_SPI_BUS 0 543 #define CONFIG_ENV_SPI_CS 0 544 #define CONFIG_ENV_SPI_MAX_HZ 10000000 545 #define CONFIG_ENV_SPI_MODE 0 546 547 /* 548 * General PCI 549 * Memory space is mapped 1-1, but I/O space must start from 0. 550 */ 551 552 #ifdef CONFIG_PCI 553 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 554 #ifdef CONFIG_PCIE1 555 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 556 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 557 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 558 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 559 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 560 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 561 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 562 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 563 #endif 564 565 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 566 #ifdef CONFIG_PCIE2 567 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 568 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 569 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 570 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 571 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 572 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 573 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 574 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 575 #endif 576 577 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 578 #ifdef CONFIG_PCIE3 579 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 580 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 581 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 582 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 583 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 584 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 585 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 586 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 587 #endif 588 589 /* controller 4, Base address 203000 */ 590 #ifdef CONFIG_PCIE4 591 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 592 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 593 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 594 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 595 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 596 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 597 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 598 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 599 #endif 600 601 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 602 #endif /* CONFIG_PCI */ 603 604 /* SATA */ 605 #define CONFIG_FSL_SATA_V2 606 #ifdef CONFIG_FSL_SATA_V2 607 #define CONFIG_SYS_SATA_MAX_DEVICE 1 608 #define CONFIG_SATA1 609 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 610 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 611 612 #define CONFIG_LBA48 613 #endif 614 615 /* 616 * USB 617 */ 618 #define CONFIG_HAS_FSL_DR_USB 619 620 #ifdef CONFIG_HAS_FSL_DR_USB 621 #ifdef CONFIG_USB_EHCI_HCD 622 #define CONFIG_USB_EHCI_FSL 623 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 624 #define CONFIG_EHCI_DESC_BIG_ENDIAN 625 #endif 626 #endif 627 628 #ifdef CONFIG_MMC 629 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 630 #endif 631 632 /* Qman/Bman */ 633 #ifndef CONFIG_NOBQFMAN 634 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 635 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 636 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 637 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 638 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 639 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 640 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 641 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 642 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 643 CONFIG_SYS_BMAN_CENA_SIZE) 644 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 645 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 646 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 647 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 648 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 649 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 650 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 651 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 652 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 653 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 654 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 655 CONFIG_SYS_QMAN_CENA_SIZE) 656 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 657 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 658 659 #define CONFIG_SYS_DPAA_FMAN 660 #define CONFIG_SYS_DPAA_PME 661 662 #define CONFIG_QE 663 #define CONFIG_U_QE 664 665 /* Default address of microcode for the Linux Fman driver */ 666 #if defined(CONFIG_SPIFLASH) 667 /* 668 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 669 * env, so we got 0x110000. 670 */ 671 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 672 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 673 #elif defined(CONFIG_SDCARD) 674 /* 675 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 676 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 677 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 678 */ 679 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 680 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 681 #elif defined(CONFIG_NAND) 682 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 683 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 684 #else 685 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 686 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 687 #endif 688 689 #if defined(CONFIG_SPIFLASH) 690 #define CONFIG_SYS_QE_FW_ADDR 0x130000 691 #elif defined(CONFIG_SDCARD) 692 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 693 #elif defined(CONFIG_NAND) 694 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 695 #else 696 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 697 #endif 698 699 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 700 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 701 #endif /* CONFIG_NOBQFMAN */ 702 703 #ifdef CONFIG_SYS_DPAA_FMAN 704 #define CONFIG_FMAN_ENET 705 #define CONFIG_PHY_VITESSE 706 #define CONFIG_PHY_REALTEK 707 #endif 708 709 #ifdef CONFIG_FMAN_ENET 710 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 711 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 712 #elif defined(CONFIG_TARGET_T1040D4RDB) 713 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 714 #elif defined(CONFIG_TARGET_T1042D4RDB) 715 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 716 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 717 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 718 #endif 719 720 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 721 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 722 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 723 #else 724 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 725 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 726 #endif 727 728 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 729 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 730 #define CONFIG_VSC9953 731 #ifdef CONFIG_TARGET_T1040RDB 732 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 733 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 734 #else 735 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 736 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 737 #endif 738 #endif 739 740 #define CONFIG_MII /* MII PHY management */ 741 #define CONFIG_ETHPRIME "FM1@DTSEC4" 742 #endif 743 744 /* 745 * Environment 746 */ 747 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 748 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 749 750 /* 751 * Miscellaneous configurable options 752 */ 753 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 754 755 /* 756 * For booting Linux, the board info and command line data 757 * have to be in the first 64 MB of memory, since this is 758 * the maximum mapped by the Linux kernel during initialization. 759 */ 760 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 761 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 762 763 #ifdef CONFIG_CMD_KGDB 764 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 765 #endif 766 767 /* 768 * Dynamic MTD Partition support with mtdparts 769 */ 770 #ifdef CONFIG_MTD_NOR_FLASH 771 #define CONFIG_MTD_DEVICE 772 #define CONFIG_MTD_PARTITIONS 773 #define CONFIG_FLASH_CFI_MTD 774 #endif 775 776 /* 777 * Environment Configuration 778 */ 779 #define CONFIG_ROOTPATH "/opt/nfsroot" 780 #define CONFIG_BOOTFILE "uImage" 781 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 782 783 /* default location for tftp and bootm */ 784 #define CONFIG_LOADADDR 1000000 785 786 #define __USB_PHY_TYPE utmi 787 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 788 789 #ifdef CONFIG_TARGET_T1040RDB 790 #define FDTFILE "t1040rdb/t1040rdb.dtb" 791 #elif defined(CONFIG_TARGET_T1042RDB_PI) 792 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 793 #elif defined(CONFIG_TARGET_T1042RDB) 794 #define FDTFILE "t1042rdb/t1042rdb.dtb" 795 #elif defined(CONFIG_TARGET_T1040D4RDB) 796 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 797 #elif defined(CONFIG_TARGET_T1042D4RDB) 798 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 799 #endif 800 801 #ifdef CONFIG_FSL_DIU_FB 802 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 803 #else 804 #define DIU_ENVIRONMENT 805 #endif 806 807 #define CONFIG_EXTRA_ENV_SETTINGS \ 808 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 809 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 810 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 811 "netdev=eth0\0" \ 812 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 813 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 814 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 815 "tftpflash=tftpboot $loadaddr $uboot && " \ 816 "protect off $ubootaddr +$filesize && " \ 817 "erase $ubootaddr +$filesize && " \ 818 "cp.b $loadaddr $ubootaddr $filesize && " \ 819 "protect on $ubootaddr +$filesize && " \ 820 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 821 "consoledev=ttyS0\0" \ 822 "ramdiskaddr=2000000\0" \ 823 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 824 "fdtaddr=1e00000\0" \ 825 "fdtfile=" __stringify(FDTFILE) "\0" \ 826 "bdev=sda3\0" 827 828 #define CONFIG_LINUX \ 829 "setenv bootargs root=/dev/ram rw " \ 830 "console=$consoledev,$baudrate $othbootargs;" \ 831 "setenv ramdiskaddr 0x02000000;" \ 832 "setenv fdtaddr 0x00c00000;" \ 833 "setenv loadaddr 0x1000000;" \ 834 "bootm $loadaddr $ramdiskaddr $fdtaddr" 835 836 #define CONFIG_HDBOOT \ 837 "setenv bootargs root=/dev/$bdev rw " \ 838 "console=$consoledev,$baudrate $othbootargs;" \ 839 "tftp $loadaddr $bootfile;" \ 840 "tftp $fdtaddr $fdtfile;" \ 841 "bootm $loadaddr - $fdtaddr" 842 843 #define CONFIG_NFSBOOTCOMMAND \ 844 "setenv bootargs root=/dev/nfs rw " \ 845 "nfsroot=$serverip:$rootpath " \ 846 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 847 "console=$consoledev,$baudrate $othbootargs;" \ 848 "tftp $loadaddr $bootfile;" \ 849 "tftp $fdtaddr $fdtfile;" \ 850 "bootm $loadaddr - $fdtaddr" 851 852 #define CONFIG_RAMBOOTCOMMAND \ 853 "setenv bootargs root=/dev/ram rw " \ 854 "console=$consoledev,$baudrate $othbootargs;" \ 855 "tftp $ramdiskaddr $ramdiskfile;" \ 856 "tftp $loadaddr $bootfile;" \ 857 "tftp $fdtaddr $fdtfile;" \ 858 "bootm $loadaddr $ramdiskaddr $fdtaddr" 859 860 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 861 862 #include <asm/fsl_secure_boot.h> 863 864 #endif /* __CONFIG_H */ 865