1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #define CONFIG_E500 /* BOOKE e500 family */ 17 #include <asm/config_mpc85xx.h> 18 19 #ifdef CONFIG_RAMBOOT_PBL 20 21 #ifndef CONFIG_SECURE_BOOT 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 23 #else 24 #define CONFIG_SYS_FSL_PBL_PBI \ 25 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 26 #endif 27 28 #ifdef CONFIG_T1040RDB 29 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 30 #endif 31 #ifdef CONFIG_T1042RDB_PI 32 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 33 #endif 34 #ifdef CONFIG_T1042RDB 35 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 36 #endif 37 #ifdef CONFIG_T1040D4RDB 38 #define CONFIG_SYS_FSL_PBL_RCW \ 39 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg 40 #endif 41 #ifdef CONFIG_T1042D4RDB 42 #define CONFIG_SYS_FSL_PBL_RCW \ 43 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg 44 #endif 45 46 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 47 #define CONFIG_SPL_ENV_SUPPORT 48 #define CONFIG_SPL_SERIAL_SUPPORT 49 #define CONFIG_SPL_FLUSH_IMAGE 50 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 51 #define CONFIG_SPL_LIBGENERIC_SUPPORT 52 #define CONFIG_SPL_LIBCOMMON_SUPPORT 53 #define CONFIG_SPL_I2C_SUPPORT 54 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 55 #define CONFIG_FSL_LAW /* Use common FSL init code */ 56 #define CONFIG_SYS_TEXT_BASE 0x30001000 57 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 58 #define CONFIG_SPL_PAD_TO 0x40000 59 #define CONFIG_SPL_MAX_SIZE 0x28000 60 #ifdef CONFIG_SPL_BUILD 61 #define CONFIG_SPL_SKIP_RELOCATE 62 #define CONFIG_SPL_COMMON_INIT_DDR 63 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 64 #define CONFIG_SYS_NO_FLASH 65 #endif 66 #define RESET_VECTOR_OFFSET 0x27FFC 67 #define BOOT_PAGE_OFFSET 0x27000 68 69 #ifdef CONFIG_NAND 70 #define CONFIG_SPL_NAND_SUPPORT 71 #ifdef CONFIG_SECURE_BOOT 72 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 73 /* 74 * HDR would be appended at end of image and copied to DDR along 75 * with U-Boot image. 76 */ 77 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 78 CONFIG_U_BOOT_HDR_SIZE) 79 #else 80 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 81 #endif 82 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 83 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 84 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 86 #define CONFIG_SPL_NAND_BOOT 87 #endif 88 89 #ifdef CONFIG_SPIFLASH 90 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 91 #define CONFIG_SPL_SPI_SUPPORT 92 #define CONFIG_SPL_SPI_FLASH_SUPPORT 93 #define CONFIG_SPL_SPI_FLASH_MINIMAL 94 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 95 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 96 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 97 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 98 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 99 #ifndef CONFIG_SPL_BUILD 100 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 101 #endif 102 #define CONFIG_SPL_SPI_BOOT 103 #endif 104 105 #ifdef CONFIG_SDCARD 106 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 107 #define CONFIG_SPL_MMC_SUPPORT 108 #define CONFIG_SPL_MMC_MINIMAL 109 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 110 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 111 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 112 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 113 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 114 #ifndef CONFIG_SPL_BUILD 115 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 116 #endif 117 #define CONFIG_SPL_MMC_BOOT 118 #endif 119 120 #endif 121 122 /* High Level Configuration Options */ 123 #define CONFIG_BOOKE 124 #define CONFIG_E500MC /* BOOKE e500mc family */ 125 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 126 #define CONFIG_MP /* support multiple processors */ 127 128 /* support deep sleep */ 129 #define CONFIG_DEEP_SLEEP 130 #if defined(CONFIG_DEEP_SLEEP) 131 #define CONFIG_BOARD_EARLY_INIT_F 132 #define CONFIG_SILENT_CONSOLE 133 #endif 134 135 #ifndef CONFIG_SYS_TEXT_BASE 136 #define CONFIG_SYS_TEXT_BASE 0xeff40000 137 #endif 138 139 #ifndef CONFIG_RESET_VECTOR_ADDRESS 140 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 141 #endif 142 143 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 144 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 145 #define CONFIG_FSL_IFC /* Enable IFC Support */ 146 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 147 #define CONFIG_PCI /* Enable PCI/PCIE */ 148 #define CONFIG_PCI_INDIRECT_BRIDGE 149 #define CONFIG_PCIE1 /* PCIE controller 1 */ 150 #define CONFIG_PCIE2 /* PCIE controller 2 */ 151 #define CONFIG_PCIE3 /* PCIE controller 3 */ 152 #define CONFIG_PCIE4 /* PCIE controller 4 */ 153 154 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 155 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 156 157 #define CONFIG_FSL_LAW /* Use common FSL init code */ 158 159 #define CONFIG_ENV_OVERWRITE 160 161 #ifndef CONFIG_SYS_NO_FLASH 162 #define CONFIG_FLASH_CFI_DRIVER 163 #define CONFIG_SYS_FLASH_CFI 164 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 165 #endif 166 167 #if defined(CONFIG_SPIFLASH) 168 #define CONFIG_SYS_EXTRA_ENV_RELOC 169 #define CONFIG_ENV_IS_IN_SPI_FLASH 170 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 171 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 172 #define CONFIG_ENV_SECT_SIZE 0x10000 173 #elif defined(CONFIG_SDCARD) 174 #define CONFIG_SYS_EXTRA_ENV_RELOC 175 #define CONFIG_ENV_IS_IN_MMC 176 #define CONFIG_SYS_MMC_ENV_DEV 0 177 #define CONFIG_ENV_SIZE 0x2000 178 #define CONFIG_ENV_OFFSET (512 * 0x800) 179 #elif defined(CONFIG_NAND) 180 #ifdef CONFIG_SECURE_BOOT 181 #define CONFIG_RAMBOOT_NAND 182 #define CONFIG_BOOTSCRIPT_COPY_RAM 183 #endif 184 #define CONFIG_SYS_EXTRA_ENV_RELOC 185 #define CONFIG_ENV_IS_IN_NAND 186 #define CONFIG_ENV_SIZE 0x2000 187 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 188 #else 189 #define CONFIG_ENV_IS_IN_FLASH 190 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 191 #define CONFIG_ENV_SIZE 0x2000 192 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 193 #endif 194 195 #define CONFIG_SYS_CLK_FREQ 100000000 196 #define CONFIG_DDR_CLK_FREQ 66666666 197 198 /* 199 * These can be toggled for performance analysis, otherwise use default. 200 */ 201 #define CONFIG_SYS_CACHE_STASHING 202 #define CONFIG_BACKSIDE_L2_CACHE 203 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 204 #define CONFIG_BTB /* toggle branch predition */ 205 #define CONFIG_DDR_ECC 206 #ifdef CONFIG_DDR_ECC 207 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 208 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 209 #endif 210 211 #define CONFIG_ENABLE_36BIT_PHYS 212 213 #define CONFIG_ADDR_MAP 214 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 215 216 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 217 #define CONFIG_SYS_MEMTEST_END 0x00400000 218 #define CONFIG_SYS_ALT_MEMTEST 219 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 220 221 /* 222 * Config the L3 Cache as L3 SRAM 223 */ 224 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 225 /* 226 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 227 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 228 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 229 */ 230 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 231 #define CONFIG_SYS_L3_SIZE 256 << 10 232 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 233 #ifdef CONFIG_RAMBOOT_PBL 234 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 235 #endif 236 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 237 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 238 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 239 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 240 241 #define CONFIG_SYS_DCSRBAR 0xf0000000 242 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 243 244 /* 245 * DDR Setup 246 */ 247 #define CONFIG_VERY_BIG_RAM 248 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 249 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 250 251 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 252 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 253 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 254 255 #define CONFIG_DDR_SPD 256 #ifndef CONFIG_SYS_FSL_DDR4 257 #define CONFIG_SYS_FSL_DDR3 258 #endif 259 260 #define CONFIG_SYS_SPD_BUS_NUM 0 261 #define SPD_EEPROM_ADDRESS 0x51 262 263 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 264 265 /* 266 * IFC Definitions 267 */ 268 #define CONFIG_SYS_FLASH_BASE 0xe8000000 269 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 270 271 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 272 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 273 CSPR_PORT_SIZE_16 | \ 274 CSPR_MSEL_NOR | \ 275 CSPR_V) 276 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 277 278 /* 279 * TDM Definition 280 */ 281 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 282 283 /* NOR Flash Timing Params */ 284 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 285 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 286 FTIM0_NOR_TEADC(0x5) | \ 287 FTIM0_NOR_TEAHC(0x5)) 288 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 289 FTIM1_NOR_TRAD_NOR(0x1A) |\ 290 FTIM1_NOR_TSEQRAD_NOR(0x13)) 291 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 292 FTIM2_NOR_TCH(0x4) | \ 293 FTIM2_NOR_TWPH(0x0E) | \ 294 FTIM2_NOR_TWP(0x1c)) 295 #define CONFIG_SYS_NOR_FTIM3 0x0 296 297 #define CONFIG_SYS_FLASH_QUIET_TEST 298 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 299 300 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 301 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 302 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 303 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 304 305 #define CONFIG_SYS_FLASH_EMPTY_INFO 306 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 307 308 /* CPLD on IFC */ 309 #define CPLD_LBMAP_MASK 0x3F 310 #define CPLD_BANK_SEL_MASK 0x07 311 #define CPLD_BANK_OVERRIDE 0x40 312 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 313 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 314 #define CPLD_LBMAP_RESET 0xFF 315 #define CPLD_LBMAP_SHIFT 0x03 316 317 #if defined(CONFIG_T1042RDB_PI) 318 #define CPLD_DIU_SEL_DFP 0x80 319 #elif defined(CONFIG_T1042D4RDB) 320 #define CPLD_DIU_SEL_DFP 0xc0 321 #endif 322 323 #if defined(CONFIG_T1040D4RDB) 324 #define CPLD_INT_MASK_ALL 0xFF 325 #define CPLD_INT_MASK_THERM 0x80 326 #define CPLD_INT_MASK_DVI_DFP 0x40 327 #define CPLD_INT_MASK_QSGMII1 0x20 328 #define CPLD_INT_MASK_QSGMII2 0x10 329 #define CPLD_INT_MASK_SGMI1 0x08 330 #define CPLD_INT_MASK_SGMI2 0x04 331 #define CPLD_INT_MASK_TDMR1 0x02 332 #define CPLD_INT_MASK_TDMR2 0x01 333 #endif 334 335 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 336 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 337 #define CONFIG_SYS_CSPR2_EXT (0xf) 338 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 339 | CSPR_PORT_SIZE_8 \ 340 | CSPR_MSEL_GPCM \ 341 | CSPR_V) 342 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 343 #define CONFIG_SYS_CSOR2 0x0 344 /* CPLD Timing parameters for IFC CS2 */ 345 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 346 FTIM0_GPCM_TEADC(0x0e) | \ 347 FTIM0_GPCM_TEAHC(0x0e)) 348 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 349 FTIM1_GPCM_TRAD(0x1f)) 350 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 351 FTIM2_GPCM_TCH(0x8) | \ 352 FTIM2_GPCM_TWP(0x1f)) 353 #define CONFIG_SYS_CS2_FTIM3 0x0 354 355 /* NAND Flash on IFC */ 356 #define CONFIG_NAND_FSL_IFC 357 #define CONFIG_SYS_NAND_BASE 0xff800000 358 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 359 360 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 361 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 362 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 363 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 364 | CSPR_V) 365 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 366 367 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 368 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 369 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 370 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 371 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 372 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 373 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 374 375 #define CONFIG_SYS_NAND_ONFI_DETECTION 376 377 /* ONFI NAND Flash mode0 Timing Params */ 378 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 379 FTIM0_NAND_TWP(0x18) | \ 380 FTIM0_NAND_TWCHT(0x07) | \ 381 FTIM0_NAND_TWH(0x0a)) 382 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 383 FTIM1_NAND_TWBE(0x39) | \ 384 FTIM1_NAND_TRR(0x0e) | \ 385 FTIM1_NAND_TRP(0x18)) 386 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 387 FTIM2_NAND_TREH(0x0a) | \ 388 FTIM2_NAND_TWHRE(0x1e)) 389 #define CONFIG_SYS_NAND_FTIM3 0x0 390 391 #define CONFIG_SYS_NAND_DDR_LAW 11 392 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 393 #define CONFIG_SYS_MAX_NAND_DEVICE 1 394 #define CONFIG_CMD_NAND 395 396 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 397 398 #if defined(CONFIG_NAND) 399 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 400 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 401 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 402 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 403 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 404 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 405 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 406 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 407 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 408 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 409 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 410 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 411 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 412 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 413 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 414 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 415 #else 416 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 417 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 418 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 419 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 420 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 421 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 422 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 423 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 424 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 425 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 426 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 427 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 428 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 429 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 430 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 431 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 432 #endif 433 434 #ifdef CONFIG_SPL_BUILD 435 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 436 #else 437 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 438 #endif 439 440 #if defined(CONFIG_RAMBOOT_PBL) 441 #define CONFIG_SYS_RAMBOOT 442 #endif 443 444 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 445 #if defined(CONFIG_NAND) 446 #define CONFIG_A008044_WORKAROUND 447 #endif 448 #endif 449 450 #define CONFIG_BOARD_EARLY_INIT_R 451 #define CONFIG_MISC_INIT_R 452 453 #define CONFIG_HWCONFIG 454 455 /* define to use L1 as initial stack */ 456 #define CONFIG_L1_INIT_RAM 457 #define CONFIG_SYS_INIT_RAM_LOCK 458 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 461 /* The assembler doesn't like typecast */ 462 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 463 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 464 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 465 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 466 467 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 468 GENERATED_GBL_DATA_SIZE) 469 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 470 471 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 472 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 473 474 /* Serial Port - controlled on board with jumper J8 475 * open - index 2 476 * shorted - index 1 477 */ 478 #define CONFIG_CONS_INDEX 1 479 #define CONFIG_SYS_NS16550_SERIAL 480 #define CONFIG_SYS_NS16550_REG_SIZE 1 481 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 482 483 #define CONFIG_SYS_BAUDRATE_TABLE \ 484 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 485 486 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 487 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 488 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 489 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 490 #ifndef CONFIG_SPL_BUILD 491 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 492 #endif 493 494 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB) 495 /* Video */ 496 #define CONFIG_FSL_DIU_FB 497 498 #ifdef CONFIG_FSL_DIU_FB 499 #define CONFIG_FSL_DIU_CH7301 500 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 501 #define CONFIG_VIDEO 502 #define CONFIG_CMD_BMP 503 #define CONFIG_CFB_CONSOLE 504 #define CONFIG_CFB_CONSOLE_ANSI 505 #define CONFIG_VIDEO_SW_CURSOR 506 #define CONFIG_VGA_AS_SINGLE_DEVICE 507 #define CONFIG_VIDEO_LOGO 508 #define CONFIG_VIDEO_BMP_LOGO 509 #endif 510 #endif 511 512 /* I2C */ 513 #define CONFIG_SYS_I2C 514 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 515 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 516 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 517 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 518 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 519 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 520 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 521 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 522 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 523 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 524 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 525 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 526 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 527 528 /* I2C bus multiplexer */ 529 #define I2C_MUX_PCA_ADDR 0x70 530 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 531 #define I2C_MUX_CH_DEFAULT 0x8 532 #endif 533 534 #if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB) 535 /* LDI/DVI Encoder for display */ 536 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 537 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 538 539 /* 540 * RTC configuration 541 */ 542 #define RTC 543 #define CONFIG_RTC_DS1337 1 544 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 545 546 /*DVI encoder*/ 547 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 548 #endif 549 550 /* 551 * eSPI - Enhanced SPI 552 */ 553 #define CONFIG_SPI_FLASH_BAR 554 #define CONFIG_SF_DEFAULT_SPEED 10000000 555 #define CONFIG_SF_DEFAULT_MODE 0 556 #define CONFIG_ENV_SPI_BUS 0 557 #define CONFIG_ENV_SPI_CS 0 558 #define CONFIG_ENV_SPI_MAX_HZ 10000000 559 #define CONFIG_ENV_SPI_MODE 0 560 561 /* 562 * General PCI 563 * Memory space is mapped 1-1, but I/O space must start from 0. 564 */ 565 566 #ifdef CONFIG_PCI 567 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 568 #ifdef CONFIG_PCIE1 569 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 570 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 571 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 572 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 573 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 574 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 575 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 576 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 577 #endif 578 579 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 580 #ifdef CONFIG_PCIE2 581 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 582 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 583 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 584 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 585 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 586 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 587 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 588 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 589 #endif 590 591 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 592 #ifdef CONFIG_PCIE3 593 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 594 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 595 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 596 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 597 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 598 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 599 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 600 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 601 #endif 602 603 /* controller 4, Base address 203000 */ 604 #ifdef CONFIG_PCIE4 605 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 606 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 607 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 608 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 609 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 610 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 611 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 612 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 613 #endif 614 615 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 616 617 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 618 #define CONFIG_DOS_PARTITION 619 #endif /* CONFIG_PCI */ 620 621 /* SATA */ 622 #define CONFIG_FSL_SATA_V2 623 #ifdef CONFIG_FSL_SATA_V2 624 #define CONFIG_LIBATA 625 #define CONFIG_FSL_SATA 626 627 #define CONFIG_SYS_SATA_MAX_DEVICE 1 628 #define CONFIG_SATA1 629 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 630 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 631 632 #define CONFIG_LBA48 633 #define CONFIG_CMD_SATA 634 #define CONFIG_DOS_PARTITION 635 #endif 636 637 /* 638 * USB 639 */ 640 #define CONFIG_HAS_FSL_DR_USB 641 642 #ifdef CONFIG_HAS_FSL_DR_USB 643 #define CONFIG_USB_EHCI 644 645 #ifdef CONFIG_USB_EHCI 646 #define CONFIG_USB_STORAGE 647 #define CONFIG_USB_EHCI_FSL 648 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 649 #endif 650 #endif 651 652 #define CONFIG_MMC 653 654 #ifdef CONFIG_MMC 655 #define CONFIG_FSL_ESDHC 656 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 657 #define CONFIG_GENERIC_MMC 658 #define CONFIG_DOS_PARTITION 659 #endif 660 661 /* Qman/Bman */ 662 #ifndef CONFIG_NOBQFMAN 663 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 664 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 665 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 666 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 667 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 668 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 669 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 670 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 671 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 672 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 673 CONFIG_SYS_BMAN_CENA_SIZE) 674 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 675 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 676 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 677 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 678 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 679 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 680 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 681 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 682 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 683 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 684 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 685 CONFIG_SYS_QMAN_CENA_SIZE) 686 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 687 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 688 689 #define CONFIG_SYS_DPAA_FMAN 690 #define CONFIG_SYS_DPAA_PME 691 692 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 693 #define CONFIG_QE 694 #define CONFIG_U_QE 695 #endif 696 697 /* Default address of microcode for the Linux Fman driver */ 698 #if defined(CONFIG_SPIFLASH) 699 /* 700 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 701 * env, so we got 0x110000. 702 */ 703 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 704 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 705 #elif defined(CONFIG_SDCARD) 706 /* 707 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 708 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 709 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 710 */ 711 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 712 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 713 #elif defined(CONFIG_NAND) 714 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 715 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 716 #else 717 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 718 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 719 #endif 720 721 #if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB) 722 #if defined(CONFIG_SPIFLASH) 723 #define CONFIG_SYS_QE_FW_ADDR 0x130000 724 #elif defined(CONFIG_SDCARD) 725 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 726 #elif defined(CONFIG_NAND) 727 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 728 #else 729 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 730 #endif 731 #endif 732 733 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 734 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 735 #endif /* CONFIG_NOBQFMAN */ 736 737 #ifdef CONFIG_SYS_DPAA_FMAN 738 #define CONFIG_FMAN_ENET 739 #define CONFIG_PHY_VITESSE 740 #define CONFIG_PHY_REALTEK 741 #endif 742 743 #ifdef CONFIG_FMAN_ENET 744 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 745 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 746 #elif defined(CONFIG_T1040D4RDB) 747 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 748 #elif defined(CONFIG_T1042D4RDB) 749 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 750 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 751 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 752 #endif 753 754 #ifdef CONFIG_T104XD4RDB 755 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 756 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 757 #else 758 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 759 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 760 #endif 761 762 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 763 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB) 764 #define CONFIG_VSC9953 765 #define CONFIG_CMD_ETHSW 766 #ifdef CONFIG_T1040RDB 767 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 768 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 769 #else 770 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 771 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 772 #endif 773 #endif 774 775 #define CONFIG_MII /* MII PHY management */ 776 #define CONFIG_ETHPRIME "FM1@DTSEC4" 777 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 778 #endif 779 780 /* 781 * Environment 782 */ 783 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 784 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 785 786 /* 787 * Command line configuration. 788 */ 789 #ifdef CONFIG_T1042RDB_PI 790 #define CONFIG_CMD_DATE 791 #endif 792 #define CONFIG_CMD_ERRATA 793 #define CONFIG_CMD_IRQ 794 #define CONFIG_CMD_REGINFO 795 796 #ifdef CONFIG_PCI 797 #define CONFIG_CMD_PCI 798 #endif 799 800 /* Hash command with SHA acceleration supported in hardware */ 801 #ifdef CONFIG_FSL_CAAM 802 #define CONFIG_CMD_HASH 803 #define CONFIG_SHA_HW_ACCEL 804 #endif 805 806 /* 807 * Miscellaneous configurable options 808 */ 809 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 810 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 811 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 812 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 813 #ifdef CONFIG_CMD_KGDB 814 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 815 #else 816 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 817 #endif 818 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 819 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 820 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 821 822 /* 823 * For booting Linux, the board info and command line data 824 * have to be in the first 64 MB of memory, since this is 825 * the maximum mapped by the Linux kernel during initialization. 826 */ 827 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 828 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 829 830 #ifdef CONFIG_CMD_KGDB 831 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 832 #endif 833 834 /* 835 * Dynamic MTD Partition support with mtdparts 836 */ 837 #ifndef CONFIG_SYS_NO_FLASH 838 #define CONFIG_MTD_DEVICE 839 #define CONFIG_MTD_PARTITIONS 840 #define CONFIG_CMD_MTDPARTS 841 #define CONFIG_FLASH_CFI_MTD 842 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 843 "spi0=spife110000.0" 844 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 845 "128k(dtb),96m(fs),-(user);"\ 846 "fff800000.flash:2m(uboot),9m(kernel),"\ 847 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 848 "2m(uboot),9m(kernel),128k(dtb),-(user)" 849 #endif 850 851 /* 852 * Environment Configuration 853 */ 854 #define CONFIG_ROOTPATH "/opt/nfsroot" 855 #define CONFIG_BOOTFILE "uImage" 856 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 857 858 /* default location for tftp and bootm */ 859 #define CONFIG_LOADADDR 1000000 860 861 862 #define CONFIG_BAUDRATE 115200 863 864 #define __USB_PHY_TYPE utmi 865 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 866 867 #ifdef CONFIG_T1040RDB 868 #define FDTFILE "t1040rdb/t1040rdb.dtb" 869 #elif defined(CONFIG_T1042RDB_PI) 870 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 871 #elif defined(CONFIG_T1042RDB) 872 #define FDTFILE "t1042rdb/t1042rdb.dtb" 873 #elif defined(CONFIG_T1040D4RDB) 874 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 875 #elif defined(CONFIG_T1042D4RDB) 876 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 877 #endif 878 879 #ifdef CONFIG_FSL_DIU_FB 880 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 881 #else 882 #define DIU_ENVIRONMENT 883 #endif 884 885 #define CONFIG_EXTRA_ENV_SETTINGS \ 886 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 887 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 888 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 889 "netdev=eth0\0" \ 890 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 891 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 892 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 893 "tftpflash=tftpboot $loadaddr $uboot && " \ 894 "protect off $ubootaddr +$filesize && " \ 895 "erase $ubootaddr +$filesize && " \ 896 "cp.b $loadaddr $ubootaddr $filesize && " \ 897 "protect on $ubootaddr +$filesize && " \ 898 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 899 "consoledev=ttyS0\0" \ 900 "ramdiskaddr=2000000\0" \ 901 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 902 "fdtaddr=1e00000\0" \ 903 "fdtfile=" __stringify(FDTFILE) "\0" \ 904 "bdev=sda3\0" 905 906 #define CONFIG_LINUX \ 907 "setenv bootargs root=/dev/ram rw " \ 908 "console=$consoledev,$baudrate $othbootargs;" \ 909 "setenv ramdiskaddr 0x02000000;" \ 910 "setenv fdtaddr 0x00c00000;" \ 911 "setenv loadaddr 0x1000000;" \ 912 "bootm $loadaddr $ramdiskaddr $fdtaddr" 913 914 #define CONFIG_HDBOOT \ 915 "setenv bootargs root=/dev/$bdev rw " \ 916 "console=$consoledev,$baudrate $othbootargs;" \ 917 "tftp $loadaddr $bootfile;" \ 918 "tftp $fdtaddr $fdtfile;" \ 919 "bootm $loadaddr - $fdtaddr" 920 921 #define CONFIG_NFSBOOTCOMMAND \ 922 "setenv bootargs root=/dev/nfs rw " \ 923 "nfsroot=$serverip:$rootpath " \ 924 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 925 "console=$consoledev,$baudrate $othbootargs;" \ 926 "tftp $loadaddr $bootfile;" \ 927 "tftp $fdtaddr $fdtfile;" \ 928 "bootm $loadaddr - $fdtaddr" 929 930 #define CONFIG_RAMBOOTCOMMAND \ 931 "setenv bootargs root=/dev/ram rw " \ 932 "console=$consoledev,$baudrate $othbootargs;" \ 933 "tftp $ramdiskaddr $ramdiskfile;" \ 934 "tftp $loadaddr $bootfile;" \ 935 "tftp $fdtaddr $fdtfile;" \ 936 "bootm $loadaddr $ramdiskaddr $fdtaddr" 937 938 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 939 940 #include <asm/fsl_secure_boot.h> 941 942 #endif /* __CONFIG_H */ 943