1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #include <asm/config_mpc85xx.h> 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 17 #ifndef CONFIG_SECURE_BOOT 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 19 #else 20 #define CONFIG_SYS_FSL_PBL_PBI \ 21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 22 #endif 23 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x30001000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_SKIP_RELOCATE 32 #define CONFIG_SPL_COMMON_INIT_DDR 33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 34 #define CONFIG_SYS_NO_FLASH 35 #endif 36 #define RESET_VECTOR_OFFSET 0x27FFC 37 #define BOOT_PAGE_OFFSET 0x27000 38 39 #ifdef CONFIG_NAND 40 #ifdef CONFIG_SECURE_BOOT 41 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 42 /* 43 * HDR would be appended at end of image and copied to DDR along 44 * with U-Boot image. 45 */ 46 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 47 CONFIG_U_BOOT_HDR_SIZE) 48 #else 49 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 50 #endif 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #ifdef CONFIG_TARGET_T1040RDB 56 #define CONFIG_SYS_FSL_PBL_RCW \ 57 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 58 #endif 59 #ifdef CONFIG_TARGET_T1042RDB_PI 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 62 #endif 63 #ifdef CONFIG_TARGET_T1042RDB 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 66 #endif 67 #ifdef CONFIG_TARGET_T1040D4RDB 68 #define CONFIG_SYS_FSL_PBL_RCW \ 69 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 70 #endif 71 #ifdef CONFIG_TARGET_T1042D4RDB 72 #define CONFIG_SYS_FSL_PBL_RCW \ 73 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 74 #endif 75 #define CONFIG_SPL_NAND_BOOT 76 #endif 77 78 #ifdef CONFIG_SPIFLASH 79 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 80 #define CONFIG_SPL_SPI_FLASH_MINIMAL 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 84 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 85 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 86 #ifndef CONFIG_SPL_BUILD 87 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 88 #endif 89 #ifdef CONFIG_TARGET_T1040RDB 90 #define CONFIG_SYS_FSL_PBL_RCW \ 91 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 92 #endif 93 #ifdef CONFIG_TARGET_T1042RDB_PI 94 #define CONFIG_SYS_FSL_PBL_RCW \ 95 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 96 #endif 97 #ifdef CONFIG_TARGET_T1042RDB 98 #define CONFIG_SYS_FSL_PBL_RCW \ 99 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 100 #endif 101 #ifdef CONFIG_TARGET_T1040D4RDB 102 #define CONFIG_SYS_FSL_PBL_RCW \ 103 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 104 #endif 105 #ifdef CONFIG_TARGET_T1042D4RDB 106 #define CONFIG_SYS_FSL_PBL_RCW \ 107 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 108 #endif 109 #define CONFIG_SPL_SPI_BOOT 110 #endif 111 112 #ifdef CONFIG_SDCARD 113 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 114 #define CONFIG_SPL_MMC_MINIMAL 115 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 116 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 117 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 118 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 119 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 120 #ifndef CONFIG_SPL_BUILD 121 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 122 #endif 123 #ifdef CONFIG_TARGET_T1040RDB 124 #define CONFIG_SYS_FSL_PBL_RCW \ 125 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 126 #endif 127 #ifdef CONFIG_TARGET_T1042RDB_PI 128 #define CONFIG_SYS_FSL_PBL_RCW \ 129 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 130 #endif 131 #ifdef CONFIG_TARGET_T1042RDB 132 #define CONFIG_SYS_FSL_PBL_RCW \ 133 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 134 #endif 135 #ifdef CONFIG_TARGET_T1040D4RDB 136 #define CONFIG_SYS_FSL_PBL_RCW \ 137 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 138 #endif 139 #ifdef CONFIG_TARGET_T1042D4RDB 140 #define CONFIG_SYS_FSL_PBL_RCW \ 141 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 142 #endif 143 #define CONFIG_SPL_MMC_BOOT 144 #endif 145 146 #endif 147 148 /* High Level Configuration Options */ 149 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 150 #define CONFIG_MP /* support multiple processors */ 151 152 /* support deep sleep */ 153 #define CONFIG_DEEP_SLEEP 154 155 #ifndef CONFIG_SYS_TEXT_BASE 156 #define CONFIG_SYS_TEXT_BASE 0xeff40000 157 #endif 158 159 #ifndef CONFIG_RESET_VECTOR_ADDRESS 160 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 161 #endif 162 163 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 164 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 165 #define CONFIG_FSL_IFC /* Enable IFC Support */ 166 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 167 #define CONFIG_PCI_INDIRECT_BRIDGE 168 #define CONFIG_PCIE1 /* PCIE controller 1 */ 169 #define CONFIG_PCIE2 /* PCIE controller 2 */ 170 #define CONFIG_PCIE3 /* PCIE controller 3 */ 171 #define CONFIG_PCIE4 /* PCIE controller 4 */ 172 173 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 174 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 175 176 #define CONFIG_ENV_OVERWRITE 177 178 #ifndef CONFIG_SYS_NO_FLASH 179 #define CONFIG_FLASH_CFI_DRIVER 180 #define CONFIG_SYS_FLASH_CFI 181 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 182 #endif 183 184 #if defined(CONFIG_SPIFLASH) 185 #define CONFIG_SYS_EXTRA_ENV_RELOC 186 #define CONFIG_ENV_IS_IN_SPI_FLASH 187 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 188 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 189 #define CONFIG_ENV_SECT_SIZE 0x10000 190 #elif defined(CONFIG_SDCARD) 191 #define CONFIG_SYS_EXTRA_ENV_RELOC 192 #define CONFIG_ENV_IS_IN_MMC 193 #define CONFIG_SYS_MMC_ENV_DEV 0 194 #define CONFIG_ENV_SIZE 0x2000 195 #define CONFIG_ENV_OFFSET (512 * 0x800) 196 #elif defined(CONFIG_NAND) 197 #ifdef CONFIG_SECURE_BOOT 198 #define CONFIG_RAMBOOT_NAND 199 #define CONFIG_BOOTSCRIPT_COPY_RAM 200 #endif 201 #define CONFIG_SYS_EXTRA_ENV_RELOC 202 #define CONFIG_ENV_IS_IN_NAND 203 #define CONFIG_ENV_SIZE 0x2000 204 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 205 #else 206 #define CONFIG_ENV_IS_IN_FLASH 207 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 208 #define CONFIG_ENV_SIZE 0x2000 209 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 210 #endif 211 212 #define CONFIG_SYS_CLK_FREQ 100000000 213 #define CONFIG_DDR_CLK_FREQ 66666666 214 215 /* 216 * These can be toggled for performance analysis, otherwise use default. 217 */ 218 #define CONFIG_SYS_CACHE_STASHING 219 #define CONFIG_BACKSIDE_L2_CACHE 220 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 221 #define CONFIG_BTB /* toggle branch predition */ 222 #define CONFIG_DDR_ECC 223 #ifdef CONFIG_DDR_ECC 224 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 225 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 226 #endif 227 228 #define CONFIG_ENABLE_36BIT_PHYS 229 230 #define CONFIG_ADDR_MAP 231 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 232 233 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 234 #define CONFIG_SYS_MEMTEST_END 0x00400000 235 #define CONFIG_SYS_ALT_MEMTEST 236 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 237 238 /* 239 * Config the L3 Cache as L3 SRAM 240 */ 241 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 242 /* 243 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 244 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 245 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 246 */ 247 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 248 #define CONFIG_SYS_L3_SIZE 256 << 10 249 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 250 #ifdef CONFIG_RAMBOOT_PBL 251 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 252 #endif 253 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 254 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 255 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 256 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 257 258 #define CONFIG_SYS_DCSRBAR 0xf0000000 259 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 260 261 /* 262 * DDR Setup 263 */ 264 #define CONFIG_VERY_BIG_RAM 265 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 266 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 267 268 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 269 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 270 271 #define CONFIG_DDR_SPD 272 273 #define CONFIG_SYS_SPD_BUS_NUM 0 274 #define SPD_EEPROM_ADDRESS 0x51 275 276 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 277 278 /* 279 * IFC Definitions 280 */ 281 #define CONFIG_SYS_FLASH_BASE 0xe8000000 282 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 283 284 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 285 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 286 CSPR_PORT_SIZE_16 | \ 287 CSPR_MSEL_NOR | \ 288 CSPR_V) 289 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 290 291 /* 292 * TDM Definition 293 */ 294 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 295 296 /* NOR Flash Timing Params */ 297 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 298 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 299 FTIM0_NOR_TEADC(0x5) | \ 300 FTIM0_NOR_TEAHC(0x5)) 301 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 302 FTIM1_NOR_TRAD_NOR(0x1A) |\ 303 FTIM1_NOR_TSEQRAD_NOR(0x13)) 304 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 305 FTIM2_NOR_TCH(0x4) | \ 306 FTIM2_NOR_TWPH(0x0E) | \ 307 FTIM2_NOR_TWP(0x1c)) 308 #define CONFIG_SYS_NOR_FTIM3 0x0 309 310 #define CONFIG_SYS_FLASH_QUIET_TEST 311 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 312 313 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 314 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 315 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 316 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 317 318 #define CONFIG_SYS_FLASH_EMPTY_INFO 319 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 320 321 /* CPLD on IFC */ 322 #define CPLD_LBMAP_MASK 0x3F 323 #define CPLD_BANK_SEL_MASK 0x07 324 #define CPLD_BANK_OVERRIDE 0x40 325 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 326 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 327 #define CPLD_LBMAP_RESET 0xFF 328 #define CPLD_LBMAP_SHIFT 0x03 329 330 #if defined(CONFIG_TARGET_T1042RDB_PI) 331 #define CPLD_DIU_SEL_DFP 0x80 332 #elif defined(CONFIG_TARGET_T1042D4RDB) 333 #define CPLD_DIU_SEL_DFP 0xc0 334 #endif 335 336 #if defined(CONFIG_TARGET_T1040D4RDB) 337 #define CPLD_INT_MASK_ALL 0xFF 338 #define CPLD_INT_MASK_THERM 0x80 339 #define CPLD_INT_MASK_DVI_DFP 0x40 340 #define CPLD_INT_MASK_QSGMII1 0x20 341 #define CPLD_INT_MASK_QSGMII2 0x10 342 #define CPLD_INT_MASK_SGMI1 0x08 343 #define CPLD_INT_MASK_SGMI2 0x04 344 #define CPLD_INT_MASK_TDMR1 0x02 345 #define CPLD_INT_MASK_TDMR2 0x01 346 #endif 347 348 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 349 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 350 #define CONFIG_SYS_CSPR2_EXT (0xf) 351 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 352 | CSPR_PORT_SIZE_8 \ 353 | CSPR_MSEL_GPCM \ 354 | CSPR_V) 355 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 356 #define CONFIG_SYS_CSOR2 0x0 357 /* CPLD Timing parameters for IFC CS2 */ 358 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 359 FTIM0_GPCM_TEADC(0x0e) | \ 360 FTIM0_GPCM_TEAHC(0x0e)) 361 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 362 FTIM1_GPCM_TRAD(0x1f)) 363 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 364 FTIM2_GPCM_TCH(0x8) | \ 365 FTIM2_GPCM_TWP(0x1f)) 366 #define CONFIG_SYS_CS2_FTIM3 0x0 367 368 /* NAND Flash on IFC */ 369 #define CONFIG_NAND_FSL_IFC 370 #define CONFIG_SYS_NAND_BASE 0xff800000 371 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 372 373 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 374 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 375 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 376 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 377 | CSPR_V) 378 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 379 380 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 381 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 382 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 383 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 384 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 385 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 386 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 387 388 #define CONFIG_SYS_NAND_ONFI_DETECTION 389 390 /* ONFI NAND Flash mode0 Timing Params */ 391 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 392 FTIM0_NAND_TWP(0x18) | \ 393 FTIM0_NAND_TWCHT(0x07) | \ 394 FTIM0_NAND_TWH(0x0a)) 395 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 396 FTIM1_NAND_TWBE(0x39) | \ 397 FTIM1_NAND_TRR(0x0e) | \ 398 FTIM1_NAND_TRP(0x18)) 399 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 400 FTIM2_NAND_TREH(0x0a) | \ 401 FTIM2_NAND_TWHRE(0x1e)) 402 #define CONFIG_SYS_NAND_FTIM3 0x0 403 404 #define CONFIG_SYS_NAND_DDR_LAW 11 405 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 406 #define CONFIG_SYS_MAX_NAND_DEVICE 1 407 #define CONFIG_CMD_NAND 408 409 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 410 411 #if defined(CONFIG_NAND) 412 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 413 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 414 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 415 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 416 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 417 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 418 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 419 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 420 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 421 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 422 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 423 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 424 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 425 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 426 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 427 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 428 #else 429 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 430 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 431 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 432 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 433 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 434 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 435 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 436 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 437 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 438 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 439 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 440 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 441 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 442 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 443 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 444 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 445 #endif 446 447 #ifdef CONFIG_SPL_BUILD 448 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 449 #else 450 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 451 #endif 452 453 #if defined(CONFIG_RAMBOOT_PBL) 454 #define CONFIG_SYS_RAMBOOT 455 #endif 456 457 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 458 #if defined(CONFIG_NAND) 459 #define CONFIG_A008044_WORKAROUND 460 #endif 461 #endif 462 463 #define CONFIG_BOARD_EARLY_INIT_R 464 #define CONFIG_MISC_INIT_R 465 466 #define CONFIG_HWCONFIG 467 468 /* define to use L1 as initial stack */ 469 #define CONFIG_L1_INIT_RAM 470 #define CONFIG_SYS_INIT_RAM_LOCK 471 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 472 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 473 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 474 /* The assembler doesn't like typecast */ 475 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 476 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 477 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 478 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 479 480 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 481 GENERATED_GBL_DATA_SIZE) 482 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 483 484 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 485 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 486 487 /* Serial Port - controlled on board with jumper J8 488 * open - index 2 489 * shorted - index 1 490 */ 491 #define CONFIG_CONS_INDEX 1 492 #define CONFIG_SYS_NS16550_SERIAL 493 #define CONFIG_SYS_NS16550_REG_SIZE 1 494 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 495 496 #define CONFIG_SYS_BAUDRATE_TABLE \ 497 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 498 499 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 500 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 501 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 502 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 503 504 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 505 /* Video */ 506 #define CONFIG_FSL_DIU_FB 507 508 #ifdef CONFIG_FSL_DIU_FB 509 #define CONFIG_FSL_DIU_CH7301 510 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 511 #define CONFIG_CMD_BMP 512 #define CONFIG_VIDEO_LOGO 513 #define CONFIG_VIDEO_BMP_LOGO 514 #endif 515 #endif 516 517 /* I2C */ 518 #define CONFIG_SYS_I2C 519 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 520 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 521 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 522 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 523 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 524 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 525 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 526 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 527 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 528 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 529 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 530 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 531 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 532 533 /* I2C bus multiplexer */ 534 #define I2C_MUX_PCA_ADDR 0x70 535 #define I2C_MUX_CH_DEFAULT 0x8 536 537 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 538 defined(CONFIG_TARGET_T1040D4RDB) || \ 539 defined(CONFIG_TARGET_T1042D4RDB) 540 /* LDI/DVI Encoder for display */ 541 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 542 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 543 544 /* 545 * RTC configuration 546 */ 547 #define RTC 548 #define CONFIG_RTC_DS1337 1 549 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 550 551 /*DVI encoder*/ 552 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 553 #endif 554 555 /* 556 * eSPI - Enhanced SPI 557 */ 558 #define CONFIG_SPI_FLASH_BAR 559 #define CONFIG_SF_DEFAULT_SPEED 10000000 560 #define CONFIG_SF_DEFAULT_MODE 0 561 #define CONFIG_ENV_SPI_BUS 0 562 #define CONFIG_ENV_SPI_CS 0 563 #define CONFIG_ENV_SPI_MAX_HZ 10000000 564 #define CONFIG_ENV_SPI_MODE 0 565 566 /* 567 * General PCI 568 * Memory space is mapped 1-1, but I/O space must start from 0. 569 */ 570 571 #ifdef CONFIG_PCI 572 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 573 #ifdef CONFIG_PCIE1 574 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 575 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 576 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 577 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 578 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 579 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 580 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 581 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 582 #endif 583 584 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 585 #ifdef CONFIG_PCIE2 586 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 587 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 588 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 589 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 590 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 591 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 592 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 593 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 594 #endif 595 596 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 597 #ifdef CONFIG_PCIE3 598 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 599 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 600 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 601 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 602 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 603 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 604 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 605 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 606 #endif 607 608 /* controller 4, Base address 203000 */ 609 #ifdef CONFIG_PCIE4 610 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 611 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 612 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 613 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 614 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 615 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 616 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 617 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 618 #endif 619 620 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 621 #endif /* CONFIG_PCI */ 622 623 /* SATA */ 624 #define CONFIG_FSL_SATA_V2 625 #ifdef CONFIG_FSL_SATA_V2 626 #define CONFIG_LIBATA 627 #define CONFIG_FSL_SATA 628 629 #define CONFIG_SYS_SATA_MAX_DEVICE 1 630 #define CONFIG_SATA1 631 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 632 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 633 634 #define CONFIG_LBA48 635 #define CONFIG_CMD_SATA 636 #endif 637 638 /* 639 * USB 640 */ 641 #define CONFIG_HAS_FSL_DR_USB 642 643 #ifdef CONFIG_HAS_FSL_DR_USB 644 #define CONFIG_USB_EHCI 645 646 #ifdef CONFIG_USB_EHCI 647 #define CONFIG_USB_EHCI_FSL 648 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 649 #endif 650 #endif 651 652 #ifdef CONFIG_MMC 653 #define CONFIG_FSL_ESDHC 654 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 655 #define CONFIG_GENERIC_MMC 656 #endif 657 658 /* Qman/Bman */ 659 #ifndef CONFIG_NOBQFMAN 660 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 661 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 662 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 663 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 664 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 665 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 666 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 667 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 668 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 669 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 670 CONFIG_SYS_BMAN_CENA_SIZE) 671 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 672 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 673 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 674 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 675 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 676 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 677 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 678 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 679 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 680 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 681 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 682 CONFIG_SYS_QMAN_CENA_SIZE) 683 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 684 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 685 686 #define CONFIG_SYS_DPAA_FMAN 687 #define CONFIG_SYS_DPAA_PME 688 689 #define CONFIG_QE 690 #define CONFIG_U_QE 691 692 /* Default address of microcode for the Linux Fman driver */ 693 #if defined(CONFIG_SPIFLASH) 694 /* 695 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 696 * env, so we got 0x110000. 697 */ 698 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 699 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 700 #elif defined(CONFIG_SDCARD) 701 /* 702 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 703 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 704 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 705 */ 706 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 707 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 708 #elif defined(CONFIG_NAND) 709 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 710 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 711 #else 712 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 713 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 714 #endif 715 716 #if defined(CONFIG_SPIFLASH) 717 #define CONFIG_SYS_QE_FW_ADDR 0x130000 718 #elif defined(CONFIG_SDCARD) 719 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 720 #elif defined(CONFIG_NAND) 721 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 722 #else 723 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 724 #endif 725 726 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 727 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 728 #endif /* CONFIG_NOBQFMAN */ 729 730 #ifdef CONFIG_SYS_DPAA_FMAN 731 #define CONFIG_FMAN_ENET 732 #define CONFIG_PHY_VITESSE 733 #define CONFIG_PHY_REALTEK 734 #endif 735 736 #ifdef CONFIG_FMAN_ENET 737 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 738 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 739 #elif defined(CONFIG_TARGET_T1040D4RDB) 740 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 741 #elif defined(CONFIG_TARGET_T1042D4RDB) 742 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 743 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 744 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 745 #endif 746 747 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 748 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 749 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 750 #else 751 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 752 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 753 #endif 754 755 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 756 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 757 #define CONFIG_VSC9953 758 #define CONFIG_CMD_ETHSW 759 #ifdef CONFIG_TARGET_T1040RDB 760 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 761 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 762 #else 763 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 764 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 765 #endif 766 #endif 767 768 #define CONFIG_MII /* MII PHY management */ 769 #define CONFIG_ETHPRIME "FM1@DTSEC4" 770 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 771 #endif 772 773 /* 774 * Environment 775 */ 776 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 777 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 778 779 /* 780 * Command line configuration. 781 */ 782 #ifdef CONFIG_TARGET_T1042RDB_PI 783 #define CONFIG_CMD_DATE 784 #endif 785 #define CONFIG_CMD_ERRATA 786 #define CONFIG_CMD_IRQ 787 #define CONFIG_CMD_REGINFO 788 789 #ifdef CONFIG_PCI 790 #define CONFIG_CMD_PCI 791 #endif 792 793 /* Hash command with SHA acceleration supported in hardware */ 794 #ifdef CONFIG_FSL_CAAM 795 #define CONFIG_CMD_HASH 796 #define CONFIG_SHA_HW_ACCEL 797 #endif 798 799 /* 800 * Miscellaneous configurable options 801 */ 802 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 803 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 804 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 805 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 806 #ifdef CONFIG_CMD_KGDB 807 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 808 #else 809 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 810 #endif 811 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 812 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 813 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 814 815 /* 816 * For booting Linux, the board info and command line data 817 * have to be in the first 64 MB of memory, since this is 818 * the maximum mapped by the Linux kernel during initialization. 819 */ 820 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 821 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 822 823 #ifdef CONFIG_CMD_KGDB 824 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 825 #endif 826 827 /* 828 * Dynamic MTD Partition support with mtdparts 829 */ 830 #ifndef CONFIG_SYS_NO_FLASH 831 #define CONFIG_MTD_DEVICE 832 #define CONFIG_MTD_PARTITIONS 833 #define CONFIG_CMD_MTDPARTS 834 #define CONFIG_FLASH_CFI_MTD 835 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 836 "spi0=spife110000.0" 837 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 838 "128k(dtb),96m(fs),-(user);"\ 839 "fff800000.flash:2m(uboot),9m(kernel),"\ 840 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 841 "2m(uboot),9m(kernel),128k(dtb),-(user)" 842 #endif 843 844 /* 845 * Environment Configuration 846 */ 847 #define CONFIG_ROOTPATH "/opt/nfsroot" 848 #define CONFIG_BOOTFILE "uImage" 849 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 850 851 /* default location for tftp and bootm */ 852 #define CONFIG_LOADADDR 1000000 853 854 855 #define CONFIG_BAUDRATE 115200 856 857 #define __USB_PHY_TYPE utmi 858 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 859 860 #ifdef CONFIG_TARGET_T1040RDB 861 #define FDTFILE "t1040rdb/t1040rdb.dtb" 862 #elif defined(CONFIG_TARGET_T1042RDB_PI) 863 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 864 #elif defined(CONFIG_TARGET_T1042RDB) 865 #define FDTFILE "t1042rdb/t1042rdb.dtb" 866 #elif defined(CONFIG_TARGET_T1040D4RDB) 867 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 868 #elif defined(CONFIG_TARGET_T1042D4RDB) 869 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 870 #endif 871 872 #ifdef CONFIG_FSL_DIU_FB 873 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 874 #else 875 #define DIU_ENVIRONMENT 876 #endif 877 878 #define CONFIG_EXTRA_ENV_SETTINGS \ 879 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 880 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 881 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 882 "netdev=eth0\0" \ 883 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 884 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 885 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 886 "tftpflash=tftpboot $loadaddr $uboot && " \ 887 "protect off $ubootaddr +$filesize && " \ 888 "erase $ubootaddr +$filesize && " \ 889 "cp.b $loadaddr $ubootaddr $filesize && " \ 890 "protect on $ubootaddr +$filesize && " \ 891 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 892 "consoledev=ttyS0\0" \ 893 "ramdiskaddr=2000000\0" \ 894 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 895 "fdtaddr=1e00000\0" \ 896 "fdtfile=" __stringify(FDTFILE) "\0" \ 897 "bdev=sda3\0" 898 899 #define CONFIG_LINUX \ 900 "setenv bootargs root=/dev/ram rw " \ 901 "console=$consoledev,$baudrate $othbootargs;" \ 902 "setenv ramdiskaddr 0x02000000;" \ 903 "setenv fdtaddr 0x00c00000;" \ 904 "setenv loadaddr 0x1000000;" \ 905 "bootm $loadaddr $ramdiskaddr $fdtaddr" 906 907 #define CONFIG_HDBOOT \ 908 "setenv bootargs root=/dev/$bdev rw " \ 909 "console=$consoledev,$baudrate $othbootargs;" \ 910 "tftp $loadaddr $bootfile;" \ 911 "tftp $fdtaddr $fdtfile;" \ 912 "bootm $loadaddr - $fdtaddr" 913 914 #define CONFIG_NFSBOOTCOMMAND \ 915 "setenv bootargs root=/dev/nfs rw " \ 916 "nfsroot=$serverip:$rootpath " \ 917 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 918 "console=$consoledev,$baudrate $othbootargs;" \ 919 "tftp $loadaddr $bootfile;" \ 920 "tftp $fdtaddr $fdtfile;" \ 921 "bootm $loadaddr - $fdtaddr" 922 923 #define CONFIG_RAMBOOTCOMMAND \ 924 "setenv bootargs root=/dev/ram rw " \ 925 "console=$consoledev,$baudrate $othbootargs;" \ 926 "tftp $ramdiskaddr $ramdiskfile;" \ 927 "tftp $loadaddr $bootfile;" \ 928 "tftp $fdtaddr $fdtfile;" \ 929 "bootm $loadaddr $ramdiskaddr $fdtaddr" 930 931 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 932 933 #include <asm/fsl_secure_boot.h> 934 935 #endif /* __CONFIG_H */ 936