1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_SYS_GENERIC_BOARD 16 #define CONFIG_DISPLAY_BOARDINFO 17 18 #define CONFIG_E500 /* BOOKE e500 family */ 19 #include <asm/config_mpc85xx.h> 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 23 #ifdef CONFIG_T1040RDB 24 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 25 #endif 26 #ifdef CONFIG_T1042RDB_PI 27 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 28 #endif 29 #ifdef CONFIG_T1042RDB 30 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 31 #endif 32 33 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 34 #define CONFIG_SPL_ENV_SUPPORT 35 #define CONFIG_SPL_SERIAL_SUPPORT 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SPL_LIBGENERIC_SUPPORT 39 #define CONFIG_SPL_LIBCOMMON_SUPPORT 40 #define CONFIG_SPL_I2C_SUPPORT 41 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 42 #define CONFIG_FSL_LAW /* Use common FSL init code */ 43 #define CONFIG_SYS_TEXT_BASE 0x30001000 44 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 45 #define CONFIG_SPL_PAD_TO 0x40000 46 #define CONFIG_SPL_MAX_SIZE 0x28000 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SPL_SKIP_RELOCATE 49 #define CONFIG_SPL_COMMON_INIT_DDR 50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 51 #define CONFIG_SYS_NO_FLASH 52 #endif 53 #define RESET_VECTOR_OFFSET 0x27FFC 54 #define BOOT_PAGE_OFFSET 0x27000 55 56 #ifdef CONFIG_NAND 57 #define CONFIG_SPL_NAND_SUPPORT 58 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 59 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 60 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 61 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 62 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 63 #define CONFIG_SPL_NAND_BOOT 64 #endif 65 66 #ifdef CONFIG_SPIFLASH 67 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 68 #define CONFIG_SPL_SPI_SUPPORT 69 #define CONFIG_SPL_SPI_FLASH_SUPPORT 70 #define CONFIG_SPL_SPI_FLASH_MINIMAL 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 76 #ifndef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 78 #endif 79 #define CONFIG_SPL_SPI_BOOT 80 #endif 81 82 #ifdef CONFIG_SDCARD 83 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 84 #define CONFIG_SPL_MMC_SUPPORT 85 #define CONFIG_SPL_MMC_MINIMAL 86 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 87 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 88 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 89 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 91 #ifndef CONFIG_SPL_BUILD 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #endif 94 #define CONFIG_SPL_MMC_BOOT 95 #endif 96 97 #endif 98 99 /* High Level Configuration Options */ 100 #define CONFIG_BOOKE 101 #define CONFIG_E500MC /* BOOKE e500mc family */ 102 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 103 #define CONFIG_MP /* support multiple processors */ 104 105 /* support deep sleep */ 106 #define CONFIG_DEEP_SLEEP 107 #if defined(CONFIG_DEEP_SLEEP) 108 #define CONFIG_BOARD_EARLY_INIT_F 109 #define CONFIG_SILENT_CONSOLE 110 #endif 111 112 #ifndef CONFIG_SYS_TEXT_BASE 113 #define CONFIG_SYS_TEXT_BASE 0xeff40000 114 #endif 115 116 #ifndef CONFIG_RESET_VECTOR_ADDRESS 117 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 118 #endif 119 120 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 121 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 122 #define CONFIG_FSL_IFC /* Enable IFC Support */ 123 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 124 #define CONFIG_PCI /* Enable PCI/PCIE */ 125 #define CONFIG_PCI_INDIRECT_BRIDGE 126 #define CONFIG_PCIE1 /* PCIE controler 1 */ 127 #define CONFIG_PCIE2 /* PCIE controler 2 */ 128 #define CONFIG_PCIE3 /* PCIE controler 3 */ 129 #define CONFIG_PCIE4 /* PCIE controler 4 */ 130 131 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 132 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 133 134 #define CONFIG_FSL_LAW /* Use common FSL init code */ 135 136 #define CONFIG_ENV_OVERWRITE 137 138 #ifndef CONFIG_SYS_NO_FLASH 139 #define CONFIG_FLASH_CFI_DRIVER 140 #define CONFIG_SYS_FLASH_CFI 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 142 #endif 143 144 #if defined(CONFIG_SPIFLASH) 145 #define CONFIG_SYS_EXTRA_ENV_RELOC 146 #define CONFIG_ENV_IS_IN_SPI_FLASH 147 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 148 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 149 #define CONFIG_ENV_SECT_SIZE 0x10000 150 #elif defined(CONFIG_SDCARD) 151 #define CONFIG_SYS_EXTRA_ENV_RELOC 152 #define CONFIG_ENV_IS_IN_MMC 153 #define CONFIG_SYS_MMC_ENV_DEV 0 154 #define CONFIG_ENV_SIZE 0x2000 155 #define CONFIG_ENV_OFFSET (512 * 0x800) 156 #elif defined(CONFIG_NAND) 157 #define CONFIG_SYS_EXTRA_ENV_RELOC 158 #define CONFIG_ENV_IS_IN_NAND 159 #define CONFIG_ENV_SIZE 0x2000 160 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 161 #else 162 #define CONFIG_ENV_IS_IN_FLASH 163 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 164 #define CONFIG_ENV_SIZE 0x2000 165 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 166 #endif 167 168 #define CONFIG_SYS_CLK_FREQ 100000000 169 #define CONFIG_DDR_CLK_FREQ 66666666 170 171 /* 172 * These can be toggled for performance analysis, otherwise use default. 173 */ 174 #define CONFIG_SYS_CACHE_STASHING 175 #define CONFIG_BACKSIDE_L2_CACHE 176 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 177 #define CONFIG_BTB /* toggle branch predition */ 178 #define CONFIG_DDR_ECC 179 #ifdef CONFIG_DDR_ECC 180 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 181 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 182 #endif 183 184 #define CONFIG_ENABLE_36BIT_PHYS 185 186 #define CONFIG_ADDR_MAP 187 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 188 189 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 190 #define CONFIG_SYS_MEMTEST_END 0x00400000 191 #define CONFIG_SYS_ALT_MEMTEST 192 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 193 194 /* 195 * Config the L3 Cache as L3 SRAM 196 */ 197 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 198 #define CONFIG_SYS_L3_SIZE 256 << 10 199 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 200 #ifdef CONFIG_RAMBOOT_PBL 201 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 202 #endif 203 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 204 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 205 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 206 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 207 208 #define CONFIG_SYS_DCSRBAR 0xf0000000 209 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 210 211 /* 212 * DDR Setup 213 */ 214 #define CONFIG_VERY_BIG_RAM 215 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 216 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 217 218 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 219 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 220 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 221 222 #define CONFIG_DDR_SPD 223 #define CONFIG_SYS_DDR_RAW_TIMING 224 #define CONFIG_SYS_FSL_DDR3 225 226 #define CONFIG_SYS_SPD_BUS_NUM 0 227 #define SPD_EEPROM_ADDRESS 0x51 228 229 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 230 231 /* 232 * IFC Definitions 233 */ 234 #define CONFIG_SYS_FLASH_BASE 0xe8000000 235 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 236 237 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 238 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 239 CSPR_PORT_SIZE_16 | \ 240 CSPR_MSEL_NOR | \ 241 CSPR_V) 242 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 243 244 /* 245 * TDM Definition 246 */ 247 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 248 249 /* NOR Flash Timing Params */ 250 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 251 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 252 FTIM0_NOR_TEADC(0x5) | \ 253 FTIM0_NOR_TEAHC(0x5)) 254 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 255 FTIM1_NOR_TRAD_NOR(0x1A) |\ 256 FTIM1_NOR_TSEQRAD_NOR(0x13)) 257 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 258 FTIM2_NOR_TCH(0x4) | \ 259 FTIM2_NOR_TWPH(0x0E) | \ 260 FTIM2_NOR_TWP(0x1c)) 261 #define CONFIG_SYS_NOR_FTIM3 0x0 262 263 #define CONFIG_SYS_FLASH_QUIET_TEST 264 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 265 266 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 267 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 268 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 269 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 270 271 #define CONFIG_SYS_FLASH_EMPTY_INFO 272 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 273 274 /* CPLD on IFC */ 275 #define CPLD_LBMAP_MASK 0x3F 276 #define CPLD_BANK_SEL_MASK 0x07 277 #define CPLD_BANK_OVERRIDE 0x40 278 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 279 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 280 #define CPLD_LBMAP_RESET 0xFF 281 #define CPLD_LBMAP_SHIFT 0x03 282 #ifdef CONFIG_T1042RDB_PI 283 #define CPLD_DIU_SEL_DFP 0x80 284 #endif 285 286 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 287 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 288 #define CONFIG_SYS_CSPR2_EXT (0xf) 289 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 290 | CSPR_PORT_SIZE_8 \ 291 | CSPR_MSEL_GPCM \ 292 | CSPR_V) 293 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 294 #define CONFIG_SYS_CSOR2 0x0 295 /* CPLD Timing parameters for IFC CS2 */ 296 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 297 FTIM0_GPCM_TEADC(0x0e) | \ 298 FTIM0_GPCM_TEAHC(0x0e)) 299 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 300 FTIM1_GPCM_TRAD(0x1f)) 301 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 302 FTIM2_GPCM_TCH(0x8) | \ 303 FTIM2_GPCM_TWP(0x1f)) 304 #define CONFIG_SYS_CS2_FTIM3 0x0 305 306 /* NAND Flash on IFC */ 307 #define CONFIG_NAND_FSL_IFC 308 #define CONFIG_SYS_NAND_BASE 0xff800000 309 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 310 311 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 312 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 313 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 314 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 315 | CSPR_V) 316 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 317 318 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 319 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 320 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 321 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 322 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 323 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 324 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 325 326 #define CONFIG_SYS_NAND_ONFI_DETECTION 327 328 /* ONFI NAND Flash mode0 Timing Params */ 329 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 330 FTIM0_NAND_TWP(0x18) | \ 331 FTIM0_NAND_TWCHT(0x07) | \ 332 FTIM0_NAND_TWH(0x0a)) 333 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 334 FTIM1_NAND_TWBE(0x39) | \ 335 FTIM1_NAND_TRR(0x0e) | \ 336 FTIM1_NAND_TRP(0x18)) 337 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 338 FTIM2_NAND_TREH(0x0a) | \ 339 FTIM2_NAND_TWHRE(0x1e)) 340 #define CONFIG_SYS_NAND_FTIM3 0x0 341 342 #define CONFIG_SYS_NAND_DDR_LAW 11 343 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 344 #define CONFIG_SYS_MAX_NAND_DEVICE 1 345 #define CONFIG_MTD_NAND_VERIFY_WRITE 346 #define CONFIG_CMD_NAND 347 348 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 349 350 #if defined(CONFIG_NAND) 351 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 352 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 353 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 354 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 355 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 356 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 357 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 358 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 359 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 360 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 361 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 362 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 363 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 364 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 365 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 366 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 367 #else 368 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 369 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 370 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 371 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 372 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 373 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 374 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 375 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 376 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 377 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 378 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 379 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 380 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 381 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 382 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 383 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 384 #endif 385 386 #ifdef CONFIG_SPL_BUILD 387 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 388 #else 389 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 390 #endif 391 392 #if defined(CONFIG_RAMBOOT_PBL) 393 #define CONFIG_SYS_RAMBOOT 394 #endif 395 396 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 397 #if defined(CONFIG_NAND) 398 #define CONFIG_A008044_WORKAROUND 399 #endif 400 #endif 401 402 #define CONFIG_BOARD_EARLY_INIT_R 403 #define CONFIG_MISC_INIT_R 404 405 #define CONFIG_HWCONFIG 406 407 /* define to use L1 as initial stack */ 408 #define CONFIG_L1_INIT_RAM 409 #define CONFIG_SYS_INIT_RAM_LOCK 410 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 411 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 412 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 413 /* The assembler doesn't like typecast */ 414 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 415 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 416 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 417 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 418 419 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 420 GENERATED_GBL_DATA_SIZE) 421 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 422 423 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 424 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 425 426 /* Serial Port - controlled on board with jumper J8 427 * open - index 2 428 * shorted - index 1 429 */ 430 #define CONFIG_CONS_INDEX 1 431 #define CONFIG_SYS_NS16550 432 #define CONFIG_SYS_NS16550_SERIAL 433 #define CONFIG_SYS_NS16550_REG_SIZE 1 434 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 435 436 #define CONFIG_SYS_BAUDRATE_TABLE \ 437 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 438 439 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 440 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 441 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 442 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 443 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 444 #ifndef CONFIG_SPL_BUILD 445 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 446 #endif 447 448 /* Use the HUSH parser */ 449 #define CONFIG_SYS_HUSH_PARSER 450 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 451 452 #ifdef CONFIG_T1042RDB_PI 453 /* Video */ 454 #define CONFIG_FSL_DIU_FB 455 456 #ifdef CONFIG_FSL_DIU_FB 457 #define CONFIG_FSL_DIU_CH7301 458 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 459 #define CONFIG_VIDEO 460 #define CONFIG_CMD_BMP 461 #define CONFIG_CFB_CONSOLE 462 #define CONFIG_CFB_CONSOLE_ANSI 463 #define CONFIG_VIDEO_SW_CURSOR 464 #define CONFIG_VGA_AS_SINGLE_DEVICE 465 #define CONFIG_VIDEO_LOGO 466 #define CONFIG_VIDEO_BMP_LOGO 467 #endif 468 #endif 469 470 /* pass open firmware flat tree */ 471 #define CONFIG_OF_LIBFDT 472 #define CONFIG_OF_BOARD_SETUP 473 #define CONFIG_OF_STDOUT_VIA_ALIAS 474 475 /* new uImage format support */ 476 #define CONFIG_FIT 477 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 478 479 /* I2C */ 480 #define CONFIG_SYS_I2C 481 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 482 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 483 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 484 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 485 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 486 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 487 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 488 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 489 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 490 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 491 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 492 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 493 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 494 495 /* I2C bus multiplexer */ 496 #define I2C_MUX_PCA_ADDR 0x70 497 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 498 #define I2C_MUX_CH_DEFAULT 0x8 499 #endif 500 501 #ifdef CONFIG_T1042RDB_PI 502 /* LDI/DVI Encoder for display */ 503 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 504 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 505 506 /* 507 * RTC configuration 508 */ 509 #define RTC 510 #define CONFIG_RTC_DS1337 1 511 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 512 513 /*DVI encoder*/ 514 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 515 #endif 516 517 /* 518 * eSPI - Enhanced SPI 519 */ 520 #define CONFIG_FSL_ESPI 521 #define CONFIG_SPI_FLASH 522 #define CONFIG_SPI_FLASH_STMICRO 523 #define CONFIG_SPI_FLASH_BAR 524 #define CONFIG_CMD_SF 525 #define CONFIG_SF_DEFAULT_SPEED 10000000 526 #define CONFIG_SF_DEFAULT_MODE 0 527 #define CONFIG_ENV_SPI_BUS 0 528 #define CONFIG_ENV_SPI_CS 0 529 #define CONFIG_ENV_SPI_MAX_HZ 10000000 530 #define CONFIG_ENV_SPI_MODE 0 531 532 /* 533 * General PCI 534 * Memory space is mapped 1-1, but I/O space must start from 0. 535 */ 536 537 #ifdef CONFIG_PCI 538 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 539 #ifdef CONFIG_PCIE1 540 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 541 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 542 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 543 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 544 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 545 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 546 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 547 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 548 #endif 549 550 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 551 #ifdef CONFIG_PCIE2 552 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 553 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 554 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 555 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 556 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 557 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 558 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 559 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 560 #endif 561 562 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 563 #ifdef CONFIG_PCIE3 564 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 565 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 566 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 567 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 568 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 569 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 570 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 571 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 572 #endif 573 574 /* controller 4, Base address 203000 */ 575 #ifdef CONFIG_PCIE4 576 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 577 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 578 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 579 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 580 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 581 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 582 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 583 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 584 #endif 585 586 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 587 #define CONFIG_E1000 588 589 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 590 #define CONFIG_DOS_PARTITION 591 #endif /* CONFIG_PCI */ 592 593 /* SATA */ 594 #define CONFIG_FSL_SATA_V2 595 #ifdef CONFIG_FSL_SATA_V2 596 #define CONFIG_LIBATA 597 #define CONFIG_FSL_SATA 598 599 #define CONFIG_SYS_SATA_MAX_DEVICE 1 600 #define CONFIG_SATA1 601 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 602 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 603 604 #define CONFIG_LBA48 605 #define CONFIG_CMD_SATA 606 #define CONFIG_DOS_PARTITION 607 #define CONFIG_CMD_EXT2 608 #endif 609 610 /* 611 * USB 612 */ 613 #define CONFIG_HAS_FSL_DR_USB 614 615 #ifdef CONFIG_HAS_FSL_DR_USB 616 #define CONFIG_USB_EHCI 617 618 #ifdef CONFIG_USB_EHCI 619 #define CONFIG_CMD_USB 620 #define CONFIG_USB_STORAGE 621 #define CONFIG_USB_EHCI_FSL 622 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 623 #define CONFIG_CMD_EXT2 624 #endif 625 #endif 626 627 #define CONFIG_MMC 628 629 #ifdef CONFIG_MMC 630 #define CONFIG_FSL_ESDHC 631 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 632 #define CONFIG_CMD_MMC 633 #define CONFIG_GENERIC_MMC 634 #define CONFIG_CMD_EXT2 635 #define CONFIG_CMD_FAT 636 #define CONFIG_DOS_PARTITION 637 #endif 638 639 /* Qman/Bman */ 640 #ifndef CONFIG_NOBQFMAN 641 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 642 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 643 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 644 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 645 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 646 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 647 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 648 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 649 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 650 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 651 CONFIG_SYS_BMAN_CENA_SIZE) 652 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 653 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 654 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 655 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 656 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 657 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 658 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 659 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 660 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 661 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 662 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 663 CONFIG_SYS_QMAN_CENA_SIZE) 664 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 665 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 666 667 #define CONFIG_SYS_DPAA_FMAN 668 #define CONFIG_SYS_DPAA_PME 669 670 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 671 #define CONFIG_QE 672 #define CONFIG_U_QE 673 #endif 674 675 /* Default address of microcode for the Linux Fman driver */ 676 #if defined(CONFIG_SPIFLASH) 677 /* 678 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 679 * env, so we got 0x110000. 680 */ 681 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 682 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 683 #elif defined(CONFIG_SDCARD) 684 /* 685 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 686 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 687 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 688 */ 689 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 690 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 691 #elif defined(CONFIG_NAND) 692 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 693 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 694 #else 695 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 696 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 697 #endif 698 699 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 700 #if defined(CONFIG_SPIFLASH) 701 #define CONFIG_SYS_QE_FW_ADDR 0x130000 702 #elif defined(CONFIG_SDCARD) 703 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 704 #elif defined(CONFIG_NAND) 705 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 706 #else 707 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 708 #endif 709 #endif 710 711 712 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 713 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 714 #endif /* CONFIG_NOBQFMAN */ 715 716 #ifdef CONFIG_SYS_DPAA_FMAN 717 #define CONFIG_FMAN_ENET 718 #define CONFIG_PHY_VITESSE 719 #define CONFIG_PHY_REALTEK 720 #endif 721 722 #ifdef CONFIG_FMAN_ENET 723 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 724 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 725 #endif 726 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 727 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 728 729 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 730 #ifdef CONFIG_T1040RDB 731 #define CONFIG_VSC9953 732 #define CONFIG_VSC9953_CMD 733 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 734 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 735 #endif 736 737 #define CONFIG_MII /* MII PHY management */ 738 #define CONFIG_ETHPRIME "FM1@DTSEC4" 739 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 740 #endif 741 742 /* 743 * Environment 744 */ 745 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 746 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 747 748 /* 749 * Command line configuration. 750 */ 751 #include <config_cmd_default.h> 752 753 #ifdef CONFIG_T1042RDB_PI 754 #define CONFIG_CMD_DATE 755 #endif 756 #define CONFIG_CMD_DHCP 757 #define CONFIG_CMD_ELF 758 #define CONFIG_CMD_ERRATA 759 #define CONFIG_CMD_GREPENV 760 #define CONFIG_CMD_IRQ 761 #define CONFIG_CMD_I2C 762 #define CONFIG_CMD_MII 763 #define CONFIG_CMD_PING 764 #define CONFIG_CMD_REGINFO 765 #define CONFIG_CMD_SETEXPR 766 767 #ifdef CONFIG_PCI 768 #define CONFIG_CMD_PCI 769 #define CONFIG_CMD_NET 770 #endif 771 772 /* Hash command with SHA acceleration supported in hardware */ 773 #ifdef CONFIG_FSL_CAAM 774 #define CONFIG_CMD_HASH 775 #define CONFIG_SHA_HW_ACCEL 776 #endif 777 778 /* 779 * Miscellaneous configurable options 780 */ 781 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 782 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 783 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 784 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 785 #ifdef CONFIG_CMD_KGDB 786 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 787 #else 788 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 789 #endif 790 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 791 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 792 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 793 794 /* 795 * For booting Linux, the board info and command line data 796 * have to be in the first 64 MB of memory, since this is 797 * the maximum mapped by the Linux kernel during initialization. 798 */ 799 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 800 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 801 802 #ifdef CONFIG_CMD_KGDB 803 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 804 #endif 805 806 /* 807 * Dynamic MTD Partition support with mtdparts 808 */ 809 #ifndef CONFIG_SYS_NO_FLASH 810 #define CONFIG_MTD_DEVICE 811 #define CONFIG_MTD_PARTITIONS 812 #define CONFIG_CMD_MTDPARTS 813 #define CONFIG_FLASH_CFI_MTD 814 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 815 "spi0=spife110000.0" 816 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 817 "128k(dtb),96m(fs),-(user);"\ 818 "fff800000.flash:2m(uboot),9m(kernel),"\ 819 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 820 "2m(uboot),9m(kernel),128k(dtb),-(user)" 821 #endif 822 823 /* 824 * Environment Configuration 825 */ 826 #define CONFIG_ROOTPATH "/opt/nfsroot" 827 #define CONFIG_BOOTFILE "uImage" 828 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 829 830 /* default location for tftp and bootm */ 831 #define CONFIG_LOADADDR 1000000 832 833 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ 834 835 #define CONFIG_BAUDRATE 115200 836 837 #define __USB_PHY_TYPE utmi 838 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 839 840 #ifdef CONFIG_T1040RDB 841 #define FDTFILE "t1040rdb/t1040rdb.dtb" 842 #elif defined(CONFIG_T1042RDB_PI) 843 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 844 #elif defined(CONFIG_T1042RDB) 845 #define FDTFILE "t1042rdb/t1042rdb.dtb" 846 #endif 847 848 #ifdef CONFIG_FSL_DIU_FB 849 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 850 #else 851 #define DIU_ENVIRONMENT 852 #endif 853 854 #define CONFIG_EXTRA_ENV_SETTINGS \ 855 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 856 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 857 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 858 "netdev=eth0\0" \ 859 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 860 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 861 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 862 "tftpflash=tftpboot $loadaddr $uboot && " \ 863 "protect off $ubootaddr +$filesize && " \ 864 "erase $ubootaddr +$filesize && " \ 865 "cp.b $loadaddr $ubootaddr $filesize && " \ 866 "protect on $ubootaddr +$filesize && " \ 867 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 868 "consoledev=ttyS0\0" \ 869 "ramdiskaddr=2000000\0" \ 870 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 871 "fdtaddr=c00000\0" \ 872 "fdtfile=" __stringify(FDTFILE) "\0" \ 873 "bdev=sda3\0" 874 875 #define CONFIG_LINUX \ 876 "setenv bootargs root=/dev/ram rw " \ 877 "console=$consoledev,$baudrate $othbootargs;" \ 878 "setenv ramdiskaddr 0x02000000;" \ 879 "setenv fdtaddr 0x00c00000;" \ 880 "setenv loadaddr 0x1000000;" \ 881 "bootm $loadaddr $ramdiskaddr $fdtaddr" 882 883 #define CONFIG_HDBOOT \ 884 "setenv bootargs root=/dev/$bdev rw " \ 885 "console=$consoledev,$baudrate $othbootargs;" \ 886 "tftp $loadaddr $bootfile;" \ 887 "tftp $fdtaddr $fdtfile;" \ 888 "bootm $loadaddr - $fdtaddr" 889 890 #define CONFIG_NFSBOOTCOMMAND \ 891 "setenv bootargs root=/dev/nfs rw " \ 892 "nfsroot=$serverip:$rootpath " \ 893 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 894 "console=$consoledev,$baudrate $othbootargs;" \ 895 "tftp $loadaddr $bootfile;" \ 896 "tftp $fdtaddr $fdtfile;" \ 897 "bootm $loadaddr - $fdtaddr" 898 899 #define CONFIG_RAMBOOTCOMMAND \ 900 "setenv bootargs root=/dev/ram rw " \ 901 "console=$consoledev,$baudrate $othbootargs;" \ 902 "tftp $ramdiskaddr $ramdiskfile;" \ 903 "tftp $loadaddr $bootfile;" \ 904 "tftp $fdtaddr $fdtfile;" \ 905 "bootm $loadaddr $ramdiskaddr $fdtaddr" 906 907 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 908 909 #ifdef CONFIG_SECURE_BOOT 910 #include <asm/fsl_secure_boot.h> 911 #define CONFIG_CMD_BLOB 912 #endif 913 914 #endif /* __CONFIG_H */ 915