1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #include <asm/config_mpc85xx.h> 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 17 #ifndef CONFIG_SECURE_BOOT 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 19 #else 20 #define CONFIG_SYS_FSL_PBL_PBI \ 21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 22 #endif 23 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x30001000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_SKIP_RELOCATE 32 #define CONFIG_SPL_COMMON_INIT_DDR 33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 34 #endif 35 #define RESET_VECTOR_OFFSET 0x27FFC 36 #define BOOT_PAGE_OFFSET 0x27000 37 38 #ifdef CONFIG_NAND 39 #ifdef CONFIG_SECURE_BOOT 40 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 41 /* 42 * HDR would be appended at end of image and copied to DDR along 43 * with U-Boot image. 44 */ 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 46 CONFIG_U_BOOT_HDR_SIZE) 47 #else 48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 49 #endif 50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #ifdef CONFIG_TARGET_T1040RDB 55 #define CONFIG_SYS_FSL_PBL_RCW \ 56 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 57 #endif 58 #ifdef CONFIG_TARGET_T1042RDB_PI 59 #define CONFIG_SYS_FSL_PBL_RCW \ 60 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 61 #endif 62 #ifdef CONFIG_TARGET_T1042RDB 63 #define CONFIG_SYS_FSL_PBL_RCW \ 64 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 65 #endif 66 #ifdef CONFIG_TARGET_T1040D4RDB 67 #define CONFIG_SYS_FSL_PBL_RCW \ 68 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 69 #endif 70 #ifdef CONFIG_TARGET_T1042D4RDB 71 #define CONFIG_SYS_FSL_PBL_RCW \ 72 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 73 #endif 74 #define CONFIG_SPL_NAND_BOOT 75 #endif 76 77 #ifdef CONFIG_SPIFLASH 78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 79 #define CONFIG_SPL_SPI_FLASH_MINIMAL 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 85 #ifndef CONFIG_SPL_BUILD 86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 87 #endif 88 #ifdef CONFIG_TARGET_T1040RDB 89 #define CONFIG_SYS_FSL_PBL_RCW \ 90 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 91 #endif 92 #ifdef CONFIG_TARGET_T1042RDB_PI 93 #define CONFIG_SYS_FSL_PBL_RCW \ 94 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 95 #endif 96 #ifdef CONFIG_TARGET_T1042RDB 97 #define CONFIG_SYS_FSL_PBL_RCW \ 98 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 99 #endif 100 #ifdef CONFIG_TARGET_T1040D4RDB 101 #define CONFIG_SYS_FSL_PBL_RCW \ 102 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 103 #endif 104 #ifdef CONFIG_TARGET_T1042D4RDB 105 #define CONFIG_SYS_FSL_PBL_RCW \ 106 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 107 #endif 108 #define CONFIG_SPL_SPI_BOOT 109 #endif 110 111 #ifdef CONFIG_SDCARD 112 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 113 #define CONFIG_SPL_MMC_MINIMAL 114 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 115 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 116 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 117 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 118 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 119 #ifndef CONFIG_SPL_BUILD 120 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 121 #endif 122 #ifdef CONFIG_TARGET_T1040RDB 123 #define CONFIG_SYS_FSL_PBL_RCW \ 124 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 125 #endif 126 #ifdef CONFIG_TARGET_T1042RDB_PI 127 #define CONFIG_SYS_FSL_PBL_RCW \ 128 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 129 #endif 130 #ifdef CONFIG_TARGET_T1042RDB 131 #define CONFIG_SYS_FSL_PBL_RCW \ 132 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 133 #endif 134 #ifdef CONFIG_TARGET_T1040D4RDB 135 #define CONFIG_SYS_FSL_PBL_RCW \ 136 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 137 #endif 138 #ifdef CONFIG_TARGET_T1042D4RDB 139 #define CONFIG_SYS_FSL_PBL_RCW \ 140 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 141 #endif 142 #define CONFIG_SPL_MMC_BOOT 143 #endif 144 145 #endif 146 147 /* High Level Configuration Options */ 148 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 149 #define CONFIG_MP /* support multiple processors */ 150 151 /* support deep sleep */ 152 #define CONFIG_DEEP_SLEEP 153 154 #ifndef CONFIG_SYS_TEXT_BASE 155 #define CONFIG_SYS_TEXT_BASE 0xeff40000 156 #endif 157 158 #ifndef CONFIG_RESET_VECTOR_ADDRESS 159 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 160 #endif 161 162 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 163 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 164 #define CONFIG_PCI_INDIRECT_BRIDGE 165 #define CONFIG_PCIE1 /* PCIE controller 1 */ 166 #define CONFIG_PCIE2 /* PCIE controller 2 */ 167 #define CONFIG_PCIE3 /* PCIE controller 3 */ 168 #define CONFIG_PCIE4 /* PCIE controller 4 */ 169 170 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 171 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 172 173 #define CONFIG_ENV_OVERWRITE 174 175 #ifdef CONFIG_MTD_NOR_FLASH 176 #define CONFIG_FLASH_CFI_DRIVER 177 #define CONFIG_SYS_FLASH_CFI 178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 179 #endif 180 181 #if defined(CONFIG_SPIFLASH) 182 #define CONFIG_SYS_EXTRA_ENV_RELOC 183 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 184 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 185 #define CONFIG_ENV_SECT_SIZE 0x10000 186 #elif defined(CONFIG_SDCARD) 187 #define CONFIG_SYS_EXTRA_ENV_RELOC 188 #define CONFIG_SYS_MMC_ENV_DEV 0 189 #define CONFIG_ENV_SIZE 0x2000 190 #define CONFIG_ENV_OFFSET (512 * 0x800) 191 #elif defined(CONFIG_NAND) 192 #ifdef CONFIG_SECURE_BOOT 193 #define CONFIG_RAMBOOT_NAND 194 #define CONFIG_BOOTSCRIPT_COPY_RAM 195 #endif 196 #define CONFIG_SYS_EXTRA_ENV_RELOC 197 #define CONFIG_ENV_SIZE 0x2000 198 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 199 #else 200 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 201 #define CONFIG_ENV_SIZE 0x2000 202 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 203 #endif 204 205 #define CONFIG_SYS_CLK_FREQ 100000000 206 #define CONFIG_DDR_CLK_FREQ 66666666 207 208 /* 209 * These can be toggled for performance analysis, otherwise use default. 210 */ 211 #define CONFIG_SYS_CACHE_STASHING 212 #define CONFIG_BACKSIDE_L2_CACHE 213 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 214 #define CONFIG_BTB /* toggle branch predition */ 215 #define CONFIG_DDR_ECC 216 #ifdef CONFIG_DDR_ECC 217 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 218 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 219 #endif 220 221 #define CONFIG_ENABLE_36BIT_PHYS 222 223 #define CONFIG_ADDR_MAP 224 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 225 226 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 227 #define CONFIG_SYS_MEMTEST_END 0x00400000 228 #define CONFIG_SYS_ALT_MEMTEST 229 230 /* 231 * Config the L3 Cache as L3 SRAM 232 */ 233 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 234 /* 235 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 236 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 237 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 238 */ 239 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 240 #define CONFIG_SYS_L3_SIZE 256 << 10 241 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 242 #ifdef CONFIG_RAMBOOT_PBL 243 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 244 #endif 245 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 246 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 247 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 248 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 249 250 #define CONFIG_SYS_DCSRBAR 0xf0000000 251 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 252 253 /* 254 * DDR Setup 255 */ 256 #define CONFIG_VERY_BIG_RAM 257 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 258 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 259 260 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 261 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 262 263 #define CONFIG_DDR_SPD 264 265 #define CONFIG_SYS_SPD_BUS_NUM 0 266 #define SPD_EEPROM_ADDRESS 0x51 267 268 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 269 270 /* 271 * IFC Definitions 272 */ 273 #define CONFIG_SYS_FLASH_BASE 0xe8000000 274 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 275 276 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 277 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 278 CSPR_PORT_SIZE_16 | \ 279 CSPR_MSEL_NOR | \ 280 CSPR_V) 281 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 282 283 /* 284 * TDM Definition 285 */ 286 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 287 288 /* NOR Flash Timing Params */ 289 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 290 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 291 FTIM0_NOR_TEADC(0x5) | \ 292 FTIM0_NOR_TEAHC(0x5)) 293 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 294 FTIM1_NOR_TRAD_NOR(0x1A) |\ 295 FTIM1_NOR_TSEQRAD_NOR(0x13)) 296 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 297 FTIM2_NOR_TCH(0x4) | \ 298 FTIM2_NOR_TWPH(0x0E) | \ 299 FTIM2_NOR_TWP(0x1c)) 300 #define CONFIG_SYS_NOR_FTIM3 0x0 301 302 #define CONFIG_SYS_FLASH_QUIET_TEST 303 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 304 305 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 306 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 307 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 308 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 309 310 #define CONFIG_SYS_FLASH_EMPTY_INFO 311 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 312 313 /* CPLD on IFC */ 314 #define CPLD_LBMAP_MASK 0x3F 315 #define CPLD_BANK_SEL_MASK 0x07 316 #define CPLD_BANK_OVERRIDE 0x40 317 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 318 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 319 #define CPLD_LBMAP_RESET 0xFF 320 #define CPLD_LBMAP_SHIFT 0x03 321 322 #if defined(CONFIG_TARGET_T1042RDB_PI) 323 #define CPLD_DIU_SEL_DFP 0x80 324 #elif defined(CONFIG_TARGET_T1042D4RDB) 325 #define CPLD_DIU_SEL_DFP 0xc0 326 #endif 327 328 #if defined(CONFIG_TARGET_T1040D4RDB) 329 #define CPLD_INT_MASK_ALL 0xFF 330 #define CPLD_INT_MASK_THERM 0x80 331 #define CPLD_INT_MASK_DVI_DFP 0x40 332 #define CPLD_INT_MASK_QSGMII1 0x20 333 #define CPLD_INT_MASK_QSGMII2 0x10 334 #define CPLD_INT_MASK_SGMI1 0x08 335 #define CPLD_INT_MASK_SGMI2 0x04 336 #define CPLD_INT_MASK_TDMR1 0x02 337 #define CPLD_INT_MASK_TDMR2 0x01 338 #endif 339 340 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 341 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 342 #define CONFIG_SYS_CSPR2_EXT (0xf) 343 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 344 | CSPR_PORT_SIZE_8 \ 345 | CSPR_MSEL_GPCM \ 346 | CSPR_V) 347 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 348 #define CONFIG_SYS_CSOR2 0x0 349 /* CPLD Timing parameters for IFC CS2 */ 350 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 351 FTIM0_GPCM_TEADC(0x0e) | \ 352 FTIM0_GPCM_TEAHC(0x0e)) 353 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 354 FTIM1_GPCM_TRAD(0x1f)) 355 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 356 FTIM2_GPCM_TCH(0x8) | \ 357 FTIM2_GPCM_TWP(0x1f)) 358 #define CONFIG_SYS_CS2_FTIM3 0x0 359 360 /* NAND Flash on IFC */ 361 #define CONFIG_NAND_FSL_IFC 362 #define CONFIG_SYS_NAND_BASE 0xff800000 363 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 364 365 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 366 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 367 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 368 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 369 | CSPR_V) 370 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 371 372 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 373 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 374 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 375 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 376 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 377 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 378 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 379 380 #define CONFIG_SYS_NAND_ONFI_DETECTION 381 382 /* ONFI NAND Flash mode0 Timing Params */ 383 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 384 FTIM0_NAND_TWP(0x18) | \ 385 FTIM0_NAND_TWCHT(0x07) | \ 386 FTIM0_NAND_TWH(0x0a)) 387 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 388 FTIM1_NAND_TWBE(0x39) | \ 389 FTIM1_NAND_TRR(0x0e) | \ 390 FTIM1_NAND_TRP(0x18)) 391 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 392 FTIM2_NAND_TREH(0x0a) | \ 393 FTIM2_NAND_TWHRE(0x1e)) 394 #define CONFIG_SYS_NAND_FTIM3 0x0 395 396 #define CONFIG_SYS_NAND_DDR_LAW 11 397 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 398 #define CONFIG_SYS_MAX_NAND_DEVICE 1 399 400 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 401 402 #if defined(CONFIG_NAND) 403 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 404 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 405 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 406 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 407 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 408 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 409 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 410 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 411 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 412 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 413 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 414 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 415 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 416 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 417 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 418 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 419 #else 420 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 421 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 422 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 423 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 424 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 425 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 426 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 427 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 428 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 429 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 430 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 431 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 432 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 433 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 434 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 435 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 436 #endif 437 438 #ifdef CONFIG_SPL_BUILD 439 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 440 #else 441 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 442 #endif 443 444 #if defined(CONFIG_RAMBOOT_PBL) 445 #define CONFIG_SYS_RAMBOOT 446 #endif 447 448 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 449 #if defined(CONFIG_NAND) 450 #define CONFIG_A008044_WORKAROUND 451 #endif 452 #endif 453 454 #define CONFIG_BOARD_EARLY_INIT_R 455 #define CONFIG_MISC_INIT_R 456 457 #define CONFIG_HWCONFIG 458 459 /* define to use L1 as initial stack */ 460 #define CONFIG_L1_INIT_RAM 461 #define CONFIG_SYS_INIT_RAM_LOCK 462 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 465 /* The assembler doesn't like typecast */ 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 467 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 468 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 469 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 470 471 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 472 GENERATED_GBL_DATA_SIZE) 473 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 474 475 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 476 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 477 478 /* Serial Port - controlled on board with jumper J8 479 * open - index 2 480 * shorted - index 1 481 */ 482 #define CONFIG_CONS_INDEX 1 483 #define CONFIG_SYS_NS16550_SERIAL 484 #define CONFIG_SYS_NS16550_REG_SIZE 1 485 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 486 487 #define CONFIG_SYS_BAUDRATE_TABLE \ 488 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 489 490 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 491 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 492 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 493 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 494 495 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 496 /* Video */ 497 #define CONFIG_FSL_DIU_FB 498 499 #ifdef CONFIG_FSL_DIU_FB 500 #define CONFIG_FSL_DIU_CH7301 501 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 502 #define CONFIG_VIDEO_LOGO 503 #define CONFIG_VIDEO_BMP_LOGO 504 #endif 505 #endif 506 507 /* I2C */ 508 #define CONFIG_SYS_I2C 509 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 510 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 511 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 512 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 513 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 514 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 515 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 516 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 517 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 518 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 519 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 520 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 521 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 522 523 /* I2C bus multiplexer */ 524 #define I2C_MUX_PCA_ADDR 0x70 525 #define I2C_MUX_CH_DEFAULT 0x8 526 527 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 528 defined(CONFIG_TARGET_T1040D4RDB) || \ 529 defined(CONFIG_TARGET_T1042D4RDB) 530 /* LDI/DVI Encoder for display */ 531 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 532 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 533 534 /* 535 * RTC configuration 536 */ 537 #define RTC 538 #define CONFIG_RTC_DS1337 1 539 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 540 541 /*DVI encoder*/ 542 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 543 #endif 544 545 /* 546 * eSPI - Enhanced SPI 547 */ 548 #define CONFIG_SPI_FLASH_BAR 549 #define CONFIG_SF_DEFAULT_SPEED 10000000 550 #define CONFIG_SF_DEFAULT_MODE 0 551 #define CONFIG_ENV_SPI_BUS 0 552 #define CONFIG_ENV_SPI_CS 0 553 #define CONFIG_ENV_SPI_MAX_HZ 10000000 554 #define CONFIG_ENV_SPI_MODE 0 555 556 /* 557 * General PCI 558 * Memory space is mapped 1-1, but I/O space must start from 0. 559 */ 560 561 #ifdef CONFIG_PCI 562 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 563 #ifdef CONFIG_PCIE1 564 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 565 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 566 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 567 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 568 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 569 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 570 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 571 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 572 #endif 573 574 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 575 #ifdef CONFIG_PCIE2 576 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 577 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 578 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 579 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 580 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 581 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 582 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 583 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 584 #endif 585 586 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 587 #ifdef CONFIG_PCIE3 588 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 589 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 590 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 591 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 592 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 593 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 594 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 595 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 596 #endif 597 598 /* controller 4, Base address 203000 */ 599 #ifdef CONFIG_PCIE4 600 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 601 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 602 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 603 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 604 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 605 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 606 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 607 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 608 #endif 609 610 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 611 #endif /* CONFIG_PCI */ 612 613 /* SATA */ 614 #define CONFIG_FSL_SATA_V2 615 #ifdef CONFIG_FSL_SATA_V2 616 #define CONFIG_SYS_SATA_MAX_DEVICE 1 617 #define CONFIG_SATA1 618 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 619 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 620 621 #define CONFIG_LBA48 622 #endif 623 624 /* 625 * USB 626 */ 627 #define CONFIG_HAS_FSL_DR_USB 628 629 #ifdef CONFIG_HAS_FSL_DR_USB 630 #ifdef CONFIG_USB_EHCI_HCD 631 #define CONFIG_USB_EHCI_FSL 632 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 633 #define CONFIG_EHCI_DESC_BIG_ENDIAN 634 #endif 635 #endif 636 637 #ifdef CONFIG_MMC 638 #define CONFIG_FSL_ESDHC 639 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 640 #endif 641 642 /* Qman/Bman */ 643 #ifndef CONFIG_NOBQFMAN 644 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 645 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 646 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 647 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 648 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 649 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 650 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 651 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 652 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 653 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 654 CONFIG_SYS_BMAN_CENA_SIZE) 655 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 656 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 657 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 658 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 659 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 660 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 661 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 662 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 663 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 664 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 665 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 666 CONFIG_SYS_QMAN_CENA_SIZE) 667 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 668 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 669 670 #define CONFIG_SYS_DPAA_FMAN 671 #define CONFIG_SYS_DPAA_PME 672 673 #define CONFIG_QE 674 #define CONFIG_U_QE 675 676 /* Default address of microcode for the Linux Fman driver */ 677 #if defined(CONFIG_SPIFLASH) 678 /* 679 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 680 * env, so we got 0x110000. 681 */ 682 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 683 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 684 #elif defined(CONFIG_SDCARD) 685 /* 686 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 687 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 688 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 689 */ 690 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 691 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 692 #elif defined(CONFIG_NAND) 693 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 694 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 695 #else 696 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 697 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 698 #endif 699 700 #if defined(CONFIG_SPIFLASH) 701 #define CONFIG_SYS_QE_FW_ADDR 0x130000 702 #elif defined(CONFIG_SDCARD) 703 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 704 #elif defined(CONFIG_NAND) 705 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 706 #else 707 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 708 #endif 709 710 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 711 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 712 #endif /* CONFIG_NOBQFMAN */ 713 714 #ifdef CONFIG_SYS_DPAA_FMAN 715 #define CONFIG_FMAN_ENET 716 #define CONFIG_PHY_VITESSE 717 #define CONFIG_PHY_REALTEK 718 #endif 719 720 #ifdef CONFIG_FMAN_ENET 721 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 722 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 723 #elif defined(CONFIG_TARGET_T1040D4RDB) 724 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 725 #elif defined(CONFIG_TARGET_T1042D4RDB) 726 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 727 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 728 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 729 #endif 730 731 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 732 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 733 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 734 #else 735 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 736 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 737 #endif 738 739 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 740 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 741 #define CONFIG_VSC9953 742 #ifdef CONFIG_TARGET_T1040RDB 743 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 744 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 745 #else 746 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 747 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 748 #endif 749 #endif 750 751 #define CONFIG_MII /* MII PHY management */ 752 #define CONFIG_ETHPRIME "FM1@DTSEC4" 753 #endif 754 755 /* 756 * Environment 757 */ 758 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 759 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 760 761 /* 762 * Miscellaneous configurable options 763 */ 764 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 765 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 766 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 767 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 768 769 /* 770 * For booting Linux, the board info and command line data 771 * have to be in the first 64 MB of memory, since this is 772 * the maximum mapped by the Linux kernel during initialization. 773 */ 774 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 775 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 776 777 #ifdef CONFIG_CMD_KGDB 778 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 779 #endif 780 781 /* 782 * Dynamic MTD Partition support with mtdparts 783 */ 784 #ifdef CONFIG_MTD_NOR_FLASH 785 #define CONFIG_MTD_DEVICE 786 #define CONFIG_MTD_PARTITIONS 787 #define CONFIG_FLASH_CFI_MTD 788 #endif 789 790 /* 791 * Environment Configuration 792 */ 793 #define CONFIG_ROOTPATH "/opt/nfsroot" 794 #define CONFIG_BOOTFILE "uImage" 795 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 796 797 /* default location for tftp and bootm */ 798 #define CONFIG_LOADADDR 1000000 799 800 #define __USB_PHY_TYPE utmi 801 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 802 803 #ifdef CONFIG_TARGET_T1040RDB 804 #define FDTFILE "t1040rdb/t1040rdb.dtb" 805 #elif defined(CONFIG_TARGET_T1042RDB_PI) 806 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 807 #elif defined(CONFIG_TARGET_T1042RDB) 808 #define FDTFILE "t1042rdb/t1042rdb.dtb" 809 #elif defined(CONFIG_TARGET_T1040D4RDB) 810 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 811 #elif defined(CONFIG_TARGET_T1042D4RDB) 812 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 813 #endif 814 815 #ifdef CONFIG_FSL_DIU_FB 816 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 817 #else 818 #define DIU_ENVIRONMENT 819 #endif 820 821 #define CONFIG_EXTRA_ENV_SETTINGS \ 822 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 823 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 824 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 825 "netdev=eth0\0" \ 826 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 827 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 828 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 829 "tftpflash=tftpboot $loadaddr $uboot && " \ 830 "protect off $ubootaddr +$filesize && " \ 831 "erase $ubootaddr +$filesize && " \ 832 "cp.b $loadaddr $ubootaddr $filesize && " \ 833 "protect on $ubootaddr +$filesize && " \ 834 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 835 "consoledev=ttyS0\0" \ 836 "ramdiskaddr=2000000\0" \ 837 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 838 "fdtaddr=1e00000\0" \ 839 "fdtfile=" __stringify(FDTFILE) "\0" \ 840 "bdev=sda3\0" 841 842 #define CONFIG_LINUX \ 843 "setenv bootargs root=/dev/ram rw " \ 844 "console=$consoledev,$baudrate $othbootargs;" \ 845 "setenv ramdiskaddr 0x02000000;" \ 846 "setenv fdtaddr 0x00c00000;" \ 847 "setenv loadaddr 0x1000000;" \ 848 "bootm $loadaddr $ramdiskaddr $fdtaddr" 849 850 #define CONFIG_HDBOOT \ 851 "setenv bootargs root=/dev/$bdev rw " \ 852 "console=$consoledev,$baudrate $othbootargs;" \ 853 "tftp $loadaddr $bootfile;" \ 854 "tftp $fdtaddr $fdtfile;" \ 855 "bootm $loadaddr - $fdtaddr" 856 857 #define CONFIG_NFSBOOTCOMMAND \ 858 "setenv bootargs root=/dev/nfs rw " \ 859 "nfsroot=$serverip:$rootpath " \ 860 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 861 "console=$consoledev,$baudrate $othbootargs;" \ 862 "tftp $loadaddr $bootfile;" \ 863 "tftp $fdtaddr $fdtfile;" \ 864 "bootm $loadaddr - $fdtaddr" 865 866 #define CONFIG_RAMBOOTCOMMAND \ 867 "setenv bootargs root=/dev/ram rw " \ 868 "console=$consoledev,$baudrate $othbootargs;" \ 869 "tftp $ramdiskaddr $ramdiskfile;" \ 870 "tftp $loadaddr $bootfile;" \ 871 "tftp $fdtaddr $fdtfile;" \ 872 "bootm $loadaddr $ramdiskaddr $fdtaddr" 873 874 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 875 876 #include <asm/fsl_secure_boot.h> 877 878 #endif /* __CONFIG_H */ 879